Abstract is missing.
- A fast and high-capacity electromagnetic solution for highspeed IC designHoule Gan, Dan Jiao. 1-6 [doi]
- Impedance extraction for 3-D structures with multiple dielectrics using preconditioned boundary element methodYang Yi, Peng Li, Vivek Sarin, Weiping Shi. 7-10 [doi]
- Statistical analysis of RF circuits using combined circuit simulator-full wave field solver approachArun V. Sathanur, Ritochit Chakraborty, Vikram Jandhyala. 11-17 [doi]
- Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chipZhonghai Lu, Axel Jantsch. 18-25 [doi]
- Run-time adaptive on-chip communication schemeMohammad Abdullah Al Faruque, Thomas Ebi, Jörg Henkel. 26-31 [doi]
- Using functional independence conditions to optimize the performance of latency-insensitive systemsCheng-Hong Li, Luca P. Carloni. 32-39 [doi]
- A geometric approach for early power grid verification using current constraintsImad A. Ferzli, Farid N. Najm, Lars Kruse. 40-47 [doi]
- Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networksNing Mi, Sheldon X.-D. Tan, Pu Liu, Jian Cui, Yici Cai, Xianlong Hong. 48-53 [doi]
- Parallel domain decomposition for simulation of large-scale power gridsKai Sun, Quming Zhou, Kartik Mohanram, Danny C. Sorensen. 54-59 [doi]
- Fast exact Toffoli network synthesis of reversible logicRobert Wille, Daniel Große. 60-64 [doi]
- A novel synthesis algorithm for reversible circuitsMehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani. 65-68 [doi]
- Checking equivalence of quantum circuits and statesGeorge F. Viamontes, Igor L. Markov, John P. Hayes. 69-74 [doi]
- A self-adjusting clock tree architecture to cope with temperature variationsJieyi Long, Ja Chun Ku, Seda Ogrenci Memik, Yehea I. Ismail. 75-82 [doi]
- Exploiting STI stress for performanceAndrew B. Kahng, Puneet Sharma, Rasit Onur Topaloglu. 83-90 [doi]
- Automating post-silicon debugging and repairKai-Hui Chang, Igor L. Markov, Valeria Bertacco. 91-98 [doi]
- Practical method for obtaining a feasible integer solution in hierarchical layout optimizationXiaoping Tang, Xin Yuan, Michael S. Gray. 99-104 [doi]
- Monte-Carlo driven stochastic optimization framework for handling fabrication variabilityVishal Khandelwal, Ankur Srivastava. 105-110 [doi]
- Gate sizing by Lagrangian relaxation revisitedJia Wang, Debasish Das, Hai Zhou. 111-118 [doi]
- An efficient algorithm for statistical circuit optimization using Lagrangian relaxationI-Jye Lin, Yao-Wen Chang. 119-124 [doi]
- Unified adaptivity optimization of clock and logic signalsShiyan Hu, Jiang Hu. 125-130 [doi]
- Incremental component implementation selection: enabling ECO in compositional system synthesisSoheil Ghiasi. 131-134 [doi]
- Exploiting hierarchy and structure to efficiently solve graph coloring as SATMiroslav N. Velev. 135-142 [doi]
- Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectorsSivaram Gopalakrishnan, Priyank Kalla, M. Brandon Meredith, Florian Enescu. 143-148 [doi]
- Enhancing design robustness with reliability-aware resynthesis and logic simulationSmita Krishnaswamy, Stephen Plaza, Igor L. Markov, John P. Hayes. 149-154 [doi]
- Data locality enhancement for CMPsMahmut T. Kandemir. 155-159 [doi]
- Mapping model with inter-array memory sharing for multidimensional signal processingIlie I. Luican, Hongwei Zhu, Florin Balasa. 160-165 [doi]
- Increasing data-bandwidth to instruction-set extensions through register clusteringKingshuk Karuri, Anupam Chattopadhyay, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr. 166-171 [doi]
- Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP designPhilip Brisk, Ajay K. Verma, Paolo Ienne. 172-179 [doi]
- An efficient algorithm for time separation of events in concurrent systemsPeggy B. McGee, Steven M. Nowick. 180-187 [doi]
- Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gatesYu Hu, Satyaki Das, Steven Trimberger, Lei He. 188-193 [doi]
- Device and architecture concurrent optimization for FPGA transient soft error rateYan Lin, Lei He. 194-198 [doi]
- Design methodology to trade off power, output quality and error resiliency: application to color interpolation filteringGeorgios Karakonstantis, Nilanjan Banerjee, Kaushik Roy, Chaitali Chakrabarti. 199-204 [doi]
- Thermal-aware Steiner routing for 3D stacked ICsMohit Pathak, Sung Kyu Lim. 205-211 [doi]
- Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffsRoshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen. 212-219 [doi]
- Strategies for improving the parametric yield and profits of 3D ICsCesare Ferri, Sherief Reda, R. Iris Bahar. 220-226 [doi]
- Scalable exploration of functional dependency by interpolation and incremental SAT solvingChih-Chun Lee, Jie-Hong Roland Jiang, Chung-Yang Huang, Alan Mishchenko. 227-233 [doi]
- Incremental learning approach and SAT model for Boolean matching with don t caresKuo-Hua Wang, Chung-Ming Chan. 234-239 [doi]
- A performance-driven QBF-based iterative logic array representation with applications to verification, debug and testHratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Marco Benedetti, Duncan Smith. 240-245 [doi]
- The coming of age of physical synthesisCharles J. Alpert, Chris C. N. Chu, Paul G. Villarrubia. 246-249 [doi]
- An incremental learning framework for estimating signal controllability in unit-level verificationCharles H.-P. Wen, Li-C. Wang, Jayanta Bhadra. 250-257 [doi]
- Stimulus generation for constrained random simulationNathan Kitchen, Andreas Kuehlmann. 258-265 [doi]
- Probabilistic decision diagrams for exact probabilistic analysisAfshin Abdollahi. 266-272 [doi]
- Computation of minimal counterexamples by using black box techniques and symbolic methodsTobias Nopper, Christoph Scholl, Bernd Becker. 273-280 [doi]
- Approximation algorithm for the temperature-aware scheduling problemSushu Zhang, Karam S. Chatha. 281-288 [doi]
- Procrastination determination for periodic real-time tasks in leakage-aware dynamic voltage scaling systemsJian-Jia Chen, Tei-Wei Kuo. 289-294 [doi]
- The FAST methodology for high-speed SoC/computer simulationDerek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Patil, William H. Reinhart, Darrel Eric Johnson, Zheng Xu. 295-302 [doi]
- A novel SoC design methodology combining adaptive software and reconfigurable hardwareMarco D. Santambrogio, Seda Ogrenci Memik, Vincenzo Rana, Umut A. Acar, Donatella Sciuto. 303-308 [doi]
- Can nano-photonic silicon circuits become an INTRA-chip interconnect technology?Eli Yablonovitch. 309 [doi]
- Hybrid CEGAR: combining variable hiding and predicate abstractionChao Wang, Hyondeuk Kim, Aarti Gupta. 310-317 [doi]
- Automated refinement checking of concurrent systemsSudipta Kundu, Sorin Lerner, Rajesh Gupta. 318-325 [doi]
- Inductive equivalence checking under retiming and resynthesisJie-Hong Roland Jiang, Wei-Lun Hung. 326-333 [doi]
- A frequency-domain technique for statistical timing analysis of clock meshesRuilin Wang, Cheng-Kok Koh. 334-339 [doi]
- Clustering based pruning for statistical criticality computation under process variationsHushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan. 340-343 [doi]
- Timing budgeting under arbitrary process variationsRuiming Chen, Hai Zhou. 344-349 [doi]
- Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mappingYu Hu, Victor Shih, Rupak Majumdar, Lei He. 350-353 [doi]
- Combinational and sequential mapping with priority cutsAlan Mishchenko, Sungmin Cho, Satrajit Chatterjee, Robert K. Brayton. 354-361 [doi]
- A general model for performance optimization of sequential systemsDmitry Bufistov, Jordi Cortadella, Michael Kishinevsky, Sachin S. Sapatnekar. 362-369 [doi]
- Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domainsLei Cheng, Deming Chen, Martin D. F. Wong, Mike Hutton, Jason Govig. 370-375 [doi]
- Skew aware polarity assignment in clock treePo-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang. 376-379 [doi]
- Efficient multi-layer obstacle-avoiding rectilinear Steiner tree constructionChung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu, Meng-Xiang Li, Yao-Wen Chang. 380-385 [doi]
- A simultaneous bus orientation and bused pin flipping algorithmFan Mo, Robert K. Brayton. 386-389 [doi]
- Optimal bus sequencing for escape routing in dense PCBsHui Kong, Tan Yan, Martin D. F. Wong, Muhammet Mustafa Ozdal. 390-395 [doi]
- Untangling twisted nets for bus routingTan Yan, Martin D. F. Wong. 396-400 [doi]
- Low-overhead design technique for calibration of maximum frequency at multiple operating pointsSomnath Paul, Sivasubramaniam Krishnamurthy, Hamid Mahmoodi, Swarup Bhunia. 401-404 [doi]
- Variation-aware performance verification using at-speed structural test and statistical timingVikram Iyengar, Jinjun Xiong, Subbayyan Venkatesan, Vladimir Zolotov, David E. Lackey, Peter A. Habitz, Chandu Visweswariah. 405-412 [doi]
- Estimation of delay test quality and its application to test generationSeiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo. 413-417 [doi]
- Efficient path delay test generation based on stuck-at test generation using checker circuitryTsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara. 418-423 [doi]
- Timing variation-aware high-level synthesisJongyoon Jung, Taewhan Kim. 424-428 [doi]
- Early planning for clock skew scheduling during register bindingMin Ni, Seda Ogrenci Memik. 429-434 [doi]
- Compatibility path based binding algorithm for interconnect reduction in high level synthesisTaemin Kim, Xun Liu. 435-441 [doi]
- Operation chaining asynchronous pipelined circuitsGirish Venkataramani, Seth Copen Goldstein. 442-449 [doi]
- Adaptive post-silicon tuning for analog circuits: concept, analysis and optimizationXin Li, Brian Taylor, YuTsun Chien, Lawrence T. Pileggi. 450-457 [doi]
- Sensitivity analysis for oscillatorsIgor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram. 458-463 [doi]
- Yield-aware analog integrated circuit optimization using geostatistics motivated performance modelingGuo Yu, Peng Li. 464-469 [doi]
- Device-circuit co-optimization for mixed-mode circuit design via geometric programmingJintae Kim, Ritesh Jhaveri, Jason Woo, Chih-Kong Ken Yang. 470-475 [doi]
- Modeling, optimization and control of rotary traveling-wave oscillatorCheng Zhuo, Huafeng Zhang, Rupak Samanta, Jiang Hu, Kangsheng Chen. 476-480 [doi]
- A methodology for fast and accurate yield factor estimation during global routingSubarna Sinha, Charles Chiang. 481-487 [doi]
- Archer: a history-driven global routing algorithmMuhammet Mustafa Ozdal, Martin D. F. Wong. 488-495 [doi]
- High-performance routing at the nanometer scaleJarrod A. Roy, Igor L. Markov. 496-502 [doi]
- BoxRouter 2.0: architecture and implementation of a hybrid and robust global routerMinsik Cho, Katrina Lu, Kun Yuan, David Z. Pan. 503-508 [doi]
- CacheCompress: a novel approach for test data compression with cache for IP embedded coresHao Fang, Chenguang Tong, Bo Yao, Xiaodi Song, Xu Cheng. 509-512 [doi]
- A hybrid scheme for compacting test responses with unknown valuesMango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei. 513-519 [doi]
- A selective pattern-compression scheme for power and test-data reductionChia-Yi Lin, Hung-Ming Chen. 520-525 [doi]
- Methodology for low power test pattern generation using activity threshold control logicSrivaths Ravi, V. R. Devanathan, Rubin A. Parekhji. 526-529 [doi]
- ECO timing optimization using spare cellsYen-Pin Chen, Jia-Wei Fang, Yao-Wen Chang. 530-535 [doi]
- Timing optimization by restructuring long combinatorial pathsJürgen Werber, Dieter Rautenbach, Christian Szegedy. 536-543 [doi]
- Engineering change using spare cells with constant insertionYu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska. 544-547 [doi]
- Simultaneous input vector selection and dual threshold voltage assignment for static leakage minimizationLin Yuan, Gang Qu. 548-551 [doi]
- Equalized interconnects for on-chip networks: modeling and optimization frameworkByungsub Kim, Vladimir Stojanovic. 552-559 [doi]
- IntSim: A CAD tool for optimization of multilevel interconnect networksDeepak C. Sekar, Azad Naeemi, Reza Sarvari, Jeffrey A. Davis, James D. Meindl. 560-567 [doi]
- A fast band-matching technique for interconnect inductance modelingHong Li, Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan. 568-571 [doi]
- Formal verification at higher levels of abstractionDaniel Kroening, Sanjit A. Seshia. 572-578 [doi]
- Analog placement with common centroid constraintsQiang Ma, Evangeline F. Y. Young, K. P. Pun. 579-585 [doi]
- Temperature aware microprocessor floorplanning considering application dependent power loadChunta Chu, Xinyi Zhang, Lei He, Tong Jing. 586-589 [doi]
- 3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuitsPingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou. 590-597 [doi]
- Variation-aware task allocation and scheduling for MPSoCFeng Wang 0004, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan. 598-603 [doi]
- A design flow dedicated to multi-mode architectures for DSP applicationsCyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin. 604-611 [doi]
- The design and synthesis of a synchronous and distributed MAC protocol for wireless network-on-chipYi Wang, Dan Zhao. 612-617 [doi]
- Selective shielding: a crosstalk-free bus encoding techniqueMadhu Mutyam. 618-621 [doi]
- Sparse and passive reduction of massively coupled large multiport interconnectsNatalie Nakhla, Michel S. Nakhla, Ramachandra Achar. 622-626 [doi]
- Analysis of large clock meshes via harmonic-weighted model order reduction and port slidingXiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu. 627-631 [doi]
- Principle Hessian direction based parameter reduction with process variationAlexander V. Mitev, Michael Marefat, Dongsheng Ma, Janet Meiling Wang. 632-637 [doi]
- MOSFET modeling for 45nm and beyondYu Cao, Colin C. McAndrew. 638-643 [doi]
- Voltage island-driven floorplanningQiang Ma, Evangeline F. Y. Young. 644-649 [doi]
- An ILP algorithm for post-floorplanning voltage-island generation considering power-network planningWan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang. 650-655 [doi]
- Module assignment for pin-limited designs under the stacked-Vdd paradigmYong Zhan, Tianpei Zhang, Sachin S. Sapatnekar. 656-659 [doi]
- Yield-driven near-threshold SRAM designGregory K. Chen, David Blaauw, Trevor N. Mudge, Dennis Sylvester, Nam Sung Kim. 660-666 [doi]
- Soft-edge flip-flops for improved timing yield: design and optimizationVivek Joshi, David Blaauw, Dennis Sylvester. 667-673 [doi]
- Remote activation of ICs for piracy prevention and digital right managementYousra Alkabani, Farinaz Koushanfar, Miodrag Potkonjak. 674-677 [doi]
- A nonlinear cell macromodel for digital applicationsChandramouli V. Kashyap, Chirayu S. Amin, Noel Menezes, Eli Chiprout. 678-685 [doi]
- Including inductance in static timing analysisAhmed Shebaita, Dusan Petranovic, Yehea I. Ismail. 686-691 [doi]
- A robust finite-point based gate model considering process variationsAlexander V. Mitev, Dinesh Ganesan, Dheepan Shanmugasundaram, Yu Cao, Janet Meiling Wang. 692-697 [doi]
- Victim alignment in crosstalk aware timing analysisRavikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer, Joao Geada. 698-704 [doi]
- Compact modeling of variational waveformsVladimir Zolotov, Jinjun Xiong, S. Abbaspour, David J. Hathaway, Chandu Visweswariah. 705-712 [doi]
- Multi-layer interconnect performance corners for variation-aware timing analysisFrank Huebbers, Ali Dasdan, Yehea I. Ismail. 713-718 [doi]
- An efficient method for statistical circuit simulationFrank Liu. 719-724 [doi]
- A methodology for timing model characterization for statistical static timing analysisZhuo Feng, Peng Li. 725-729 [doi]
- Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performanceKunhyuk Kang, Sang Phill Park, Kaushik Roy, Muhammad Ashraful Alam. 730-734 [doi]
- An efficient method to identify critical gates under circuit agingWenping Wang, Zile Wei, Shengqi Yang, Yu Cao. 735-740 [doi]
- Efficient computation of current flow in signal wires for reliability analysisKanak Agarwal, Frank Liu. 741-746 [doi]
- The effect of process variation on device temperature in FinFET circuitsJung Hwan Choi, Jayathi Murthy, Kaushik Roy. 747-751 [doi]
- BioRoute: a network-flow based routing algorithm for digital microfluidic biochipsPing-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang. 752-757 [doi]
- Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architectureChen Dong, Deming Chen, Sansiri Tanachutiwat, Wei Wang. 758-764 [doi]
- Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arraysM. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli. 765-772 [doi]
- Combining static and dynamic defect-tolerance techniques for nanoscale memory systemsSusmit Biswas, Gang Wang, Tzvetan S. Metodi, Ryan Kastner, Frederic T. Chong. 773-778 [doi]
- An efficient wake-up schedule during power mode transition considering spurious glitches phenomenonYu-Ting Chen, Da-Cheng Juan, Ming-Chao Lee, Shih-Chieh Chang. 779-782 [doi]
- Analysis and optimization of power-gated ICs with multiple power gating configurationsAida Todri, Malgorzata Marek-Sadowska, Shih-Chieh Chang. 783-790 [doi]
- Sizing and placement of charge recycling transistors in MTCMOS circuitsEhsan Pakbaznia, Farzan Fallah, Massoud Pedram. 791-796 [doi]
- Minimizing leakage power in sequential circuits by using mixed ::::V::t:::::: flip-flopsJaehyun Kim, Youngsoo Shin. 797-802 [doi]
- Efficient decoupling capacitance budgeting considering operation and process variationsYiyu Shi, Jinjun Xiong, Chunchen Liu, Lei He. 803-810 [doi]
- Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICsMikhail Popovich, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin. 811-816 [doi]
- A novel technique for incremental analysis of on-chip power distribution networksYuhong Fu, Rajendran Panda, Ben Reschke, Savithri Sundareswaran, Min Zhao. 817-823 [doi]
- Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniquesXiaoyao Liang, Kerem Turgay, David Brooks. 824-830 [doi]
- Novel wire density driven full-chip routing for CMP variation controlHuang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-Wen Chang. 831-838 [doi]
- Accurate detection for process-hotspots with vias and incomplete specificationJingyu Xu, Subarna Sinha, Charles Chiang. 839-846 [doi]
- TIP-OPC: a new topological invariant paradigm for pixel based optical proximity correctionPeng Yu, David Z. Pan. 847-853 [doi]
- A novel intensity based optical proximity correction algorithm with speedup in lithography simulationPeng Yu, David Z. Pan. 854-859 [doi]
- Stabilizing schemes for piecewise-linear reduced order models via projection and weighting functionsBradley N. Bond, Luca Daniel. 860-866 [doi]
- Parameterized model order reduction via a two-directional Arnoldi processYung-Ta Li, Zhaojun Bai, Yangfeng Su, Xuan Zeng. 868-873 [doi]
- Efficient VCO phase macromodel generation considering statistical parametric variationsWei Dong, Zhuo Feng, Peng Li. 874-878 [doi]
- Bounding L2 gain system error generated by approximations of the nonlinear vector fieldKin Cheong Sou, Alexandre Megretski, Luca Daniel. 879-886 [doi]
- Variable domain transformation for linear PAC analysis of mixed-signal systemsJaeha Kim, Kevin D. Jones, Mark A. Horowitz. 887-894 [doi]