Table of Contents

• CD-ECC: content-dependent error correction codes for combating asymmetric nonvolatile memory operation errorsWujie Wen, Mengjie Mao, Xiaochun Zhu, Seung H. Kang, Danghui Wang, Yiran Chen. 1-8 [doi]
• ADAMS: asymmetric differential STT-RAM cell structure for reliable and high-performance applicationsYaojun Zhang, Ismail Bayram, Yu Wang 0002, Hai Li, Yiran Chen. 9-16 [doi]
• Design of cross-point metal-oxide ReRAM emphasizing reliability and costDimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie. 17-23 [doi]
• Efficient aerial image simulation on multi-core SIMD CPUPei-Ci Wu, Tan Yan, Hongbo Zhang, Martin D. F. Wong. 24-31 [doi]
• Optimally minimizing overlay violation in self-aligned double patterning decomposition for row-based standard cell layout in polynomial timeZigang Xiao, Yuelin Du, Haitong Tian, Martin D. F. Wong. 32-39 [doi]
• Efficient analog layout prototyping by layout reuse with routing preservationChing-Yu Chin, Po-Cheng Pan, Hung-Ming Chen, Tung-Chieh Chen, Jou-Chun Lin. 40-47 [doi]
• On reconfiguration-oriented approximate adder design and its applicationRong Ye, Ting Wang, Feng Yuan, Rakesh Kumar, Qiang Xu. 48-54 [doi]
• ForTER: a forward error correction scheme for timing error resilienceJie Zhang, Feng Yuan, Rong Ye, Qiang Xu. 55-60 [doi]
• Aging-aware logic synthesisMojtaba Ebrahimi, Fabian Oboril, Saman Kiamehr, Mehdi Baradaran Tahoori. 61-68 [doi]
• Model-based hardware designGirish Venkataramani, Kiran Kintali, Sudeepa Prakash, Stephan van Beek. 69-73 [doi]
• BAG: a designer-oriented integrated framework for the development of AMS circuit generatorsJohn Crossley, Alberto Puggelli, H.-P. Le, B. Yang, R. Nancollas, K. Jung, L. Kong, Nathan Narevsky, Y. Lu, N. Sutardja, E. J. An, Alberto L. Sangiovanni-Vincentelli, Elad Alon. 74-81 [doi]
• Performance evaluation of multicore systems: from traffic analysis to latency predictions (embedded tutorial)Zhiliang Qian, Paul Bogdan, Chi-Ying Tsui, Radu Marculescu. 82-84 [doi]
• Improved SAT-based ATPG: more constraints, better compactionStephan Eggersglüß, Robert Wille, Rolf Drechsler. 85-90 [doi]
• Automatic test pattern generation for delay defects using timed characteristic functionsShin-Yann Ho, Shuo-Ren Lin, Ko-Lung Yuan, Chien-Yen Kuo, Kuan-Yu Liao, Jie-Hong R. Jiang, Chien-Mo James Li. 91-98 [doi]
• DREAMS: DFM rule EvAluation using manufactured siliconRonald D. Blanton, F. Wang, C. Xue, Pk Nag, Y. Xue, Xin Li. 99-106 [doi]
• Stochastic error rate estimation for adaptive speed control with field delay testingShoichi Iizuka, Masafumi Mizuno, Dan Kuroda, Masanori Hashimoto, Takao Onoye. 107-114 [doi]
• Security-aware mapping for CAN-based real-time distributed automotive systemsChung-Wei Lin, Qi Zhu, Calvin Phung, Alberto L. Sangiovanni-Vincentelli. 115-121 [doi]
• Dynamic server power capping for enabling data center participation in power marketsHao Chen, Can Hankendi, Michael C. Caramanis, Ayse Kivilcim Coskun. 122-129 [doi]
• An energy efficient approximate adder with carry skip for error resilient neuromorphic VLSI systemsYongtae Kim, Yong Zhang, Peng Li. 130-137 [doi]
• PROTON: an automatic place-and-route tool for optical networks-on-chipAnja Boos, Luca Ramini, Ulf Schlichtmann, Davide Bertozzi. 138-145 [doi]
• Analog behavior in custom IC variation-aware designTrent McConaghy. 146-148 [doi]
• A new methodology to address the growing productivity gap in analog designDavid White. 149-152 [doi]
• Agent-based distributed power management for kilo-core processorsMuhammad Shafique, Jörg Henkel. 153-160 [doi]
• Managing mobile platform powerÜmit Y. Ogras, Raid Zuhair Ayoub, Michael Kishinevsky, David Kadjo. 161-162 [doi]
• A high-performance triple patterning layout decomposer with balanced densityBei Yu, Yen-Hung Lin, Gerard Luk-Pat, Duo Ding, Kevin Lucas, David Z. Pan. 163-169 [doi]
• Layout decomposition with pairwise coloring for multiple patterning lithographyYe Zhang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng. 170-177 [doi]
• Constrained pattern assignment for standard cell based triple patterning lithographyHaitong Tian, Yuelin Du, Hongbo Zhang, Zigang Xiao, Martin D. F. Wong. 178-185 [doi]
• Block copolymer directed self-assembly (DSA) aware contact layer optimization for 10 nm 1D standard cell libraryYuelin Du, Daifeng Guo, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang, Qiang Ma 0002. 186-193 [doi]
• Computer-aided design of electrical energy systemsYounghyun Kim, Donghwa Shin, Massimo Petricca, Sangyoung Park, Massimo Poncino, Naehyuck Chang. 194-201 [doi]
• A neuromorphic architecture for anomaly detection in autonomous large-area traffic monitoringQiuwen Chen, Qinru Qiu, Hai Li, Qing Wu. 202-205 [doi]
• Considering fabrication in sustainable computingAlex K. Jones, Yiran Chen, William O. Collinge, Haifeng Xu, Laura A. Schaefer, Amy E. Landis, Melissa M. Bilec. 206-210 [doi]
• SDC-based modulo scheduling for pipeline synthesisZhiru Zhang, Bin Liu 0006. 211-218 [doi]
• Slack matching mode-based asynchronous circuits for average-case performanceMehrdad Najibi, Peter A. Beerel. 219-225 [doi]
• Sensitization criterion for threshold logic circuits and its applicationChen-Kuan Tsai, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen. 226-233 [doi]
• FPGA acceleration of enhanced boolean constraint propagation for SAT solversJason Thong, Nicola Nicolici. 234-241 [doi]
• Dynamic thermal management in mobile devices considering the thermal coupling between battery and application processorQing Xie, Jaemin Kim, Yanzhi Wang, Donghwa Shin, Naehyuck Chang, Massoud Pedram. 242-247 [doi]
• Formal verification of distributed dynamic thermal managementMuhammad Ismail, Osman Hasan, Thomas Ebi, Muhammad Shafique, Jörg Henkel. 248-255 [doi]
• STEAM: a fast compact thermal model for two-phase cooling of integrated circuitsArvind Sridhar, Yassir Madhour, David Atienza, Thomas Brunschwiler, John Richard Thome. 256-263 [doi]
• The overview of 2013 CAD contest at ICCADIris Hui-Ru Jiang, Zhuo Li, Hwei-Tseng Wang, Natarajan Viswanathan. 264 [doi]
• ICCAD-2013 CAD contest in technology mapping for macro blocks and benchmark suiteChih-Jen Hsu, Wei-Hsun Lin, Hwei-Tseng Wang, Feng Lu, Kei-Yong Khoo. 265-267 [doi]
• ICCAD-2013 CAD contest in placement finishing and benchmark suiteMyung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert. 268-270 [doi]
• ICCAD-2013 CAD contest in mask optimization and benchmark suiteShayak Banerjee, Zhuo Li, Sani R. Nassif. 271-274 [doi]
• Compact lateral thermal resistance modeling and characterization for TSV and TSV arrayZao Liu, Sahana Swarup, Sheldon X.-D. Tan. 275-280 [doi]
• On accurate full-chip extraction and optimization of TSV-to-TSV coupling elements in 3D ICsYarui Peng, Taigon Song, Dusan Petranovic, Sung Kyu Lim. 281-288 [doi]
• The impact of shallow trench isolation effects on circuit performanceSravan K. Marella, Sachin S. Sapatnekar. 289-294 [doi]
• Diagnosing root causes of system level performance violationsLingyi Liu, Xuanyu Zhong, Xiaotao Chen, Shobha Vasudevan. 295-302 [doi]
• Automatic concolic test generation with virtual prototypes for post-silicon validationKai Cong, Fei Xie, Li Lei. 303-310 [doi]
• Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platformsDebapriya Chatterjee, Biruk Mammo, Doowon Lee, Raviv Gal, Ronny Morad, Amir Nahir, Avi Ziv, Valeria Bertacco. 311-317 [doi]
• Improving platform energy: chip area trade-off in near-threshold computing environmentHao Wang, Abhishek A. Sinkar, Nam Sung Kim. 318-325 [doi]
• Leveraging rule-based designs for automatic power domain partitioningAbhinav Agarwal, Arvind. 326-333 [doi]
• Performance boosting under reliability and power constraintsYoungtaek Kim, Lizy Kurian John, Indrani Paul, Srilatha Manne, Michael J. Schulte. 334-341 [doi]
• LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designsMinsik Cho, Hua Xiang, Haoxing Ren, Matthew M. Ziegler, Ruchir Puri. 342-348 [doi]
• Methodology for standard cell compliance and detailed placement for triple patterning lithographyBei Yu, Xiaoqing Xu, Jhih-Rong Gao, David Z. Pan. 349-356 [doi]
• POLAR: placement based on novel rough legalization and refinementTao Lin, Chris Chu, Joseph R. Shinnerl, Ismail Bustany, Ivailo Nedelchev. 357-362 [doi]
• Transient modeling of TSV-wire electromigration and lifetime analysis of power distribution network for 3D ICsXin Zhao, Yang Wan, Michael Scheuermann, Sung Kyu Lim. 363-370 [doi]
• Novel crack sensor for TSV-based 3D integrated circuits: design and deployment perspectivesChun Zhang, Moongon Jung, Sung Kyu Lim, Yiyu Shi. 371-378 [doi]
• Electromigration study for multi-scale power/ground vias in TSV-based 3D ICsJiwoo Pak, Sung Kyu Lim, David Z. Pan. 379-386 [doi]
• Scalable and efficient analog parametric fault identificationMustafa Berke Yelten, Suriyaprakash Natarajan, Bin Xue, Prashant Goteti. 387-392 [doi]
• An IDDQ-based source driver IC design-for-test techniqueS.-S. Lin, C.-L. Kao, J.-L. Huang, C. C. Lee, X.-L. Huang. 393-398 [doi]
• Hardware Trojans in wireless cryptographic ICs: silicon demonstration & detection method evaluationYu Liu, Yier Jin, Yiorgos Makris. 399-404 [doi]
• AMBER: adaptive energy management for on-chip hybrid video memoriesMuhammad Usman Karim Khan, Muhammad Shafique, Jörg Henkel. 405-412 [doi]
• Thread-criticality aware dynamic cache reconfiguration in multi-core systemPo-Yang Hsu, TingTing Hwang. 413-420 [doi]
• A disturb-alleviation scheme for 3D flash memoryYu-Ming Chang, Yuan-Hao Chang, Tei-Wei Kuo, Hsiang-Pang Li, Yung-Chun Li. 421-428 [doi]
• Unleashing the potential of MLC STT-RAM cachesXiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Li. 429-436 [doi]
• Eagle-eye: a near-optimal statistical framework for noise sensor placementTao Wang, Chun Zhang, Jinjun Xiong, Yiyu Shi. 437-443 [doi]
• Joint sizing and adaptive independent gate control for FinFET circuits operating in multiple voltage regimes using the logical effort methodXue Lin, Yanzhi Wang, Massoud Pedram. 444-449 [doi]
• High-performance gate sizing with a signoff timerAndrew B. Kahng, Seokhyeong Kang, Hyein Lee, Igor L. Markov, Pankit Thapar. 450-457 [doi]
• Efficient PVT independent abstraction of large IP blocks for hierarchical power analysisNagu R. Dhanwada, David J. Hathaway, Victor V. Zyuban, Peng Peng, Karl Moody, William W. Dungan, Arun Joseph, Rahul Rao, Christopher Gonzalez. 458-465 [doi]
• Place and route for massively parallel hardware-accelerated functional verificationMichael D. Moffitt, Gernot E. Günther, Kevin A. Pasnik. 466-472 [doi]
• Techniques and challenges of implementing large scale logic design models in massively parallel fine-grained multiprocessor systemsPlaton Beletsky, Michael Bershteyn, Alexandre Birguer, Chunkuen Ho, Viktor Salitrennik. 473-477 [doi]
• Fast statistical analysis of rare circuit failure events via scaled-sigma sampling for high-dimensional variation spaceShupeng Sun, Xin Li, Hongzhou Liu, Kangsheng Luo, Ben Gu. 478-485 [doi]
• Verifying start-up failures in coupled ring oscillators in presence of variability using predictive global optimizationTaehwan Kim, Do-Gyoon Song, Sangho Youn, Jaejin Park, Hojin Park, Jaeha Kim. 486-493 [doi]
• An efficient graph sparsification approach to scalable harmonic balance (HB) analysis of strongly nonlinear RF circuitsLengfei Han, Xueqian Zhao, Zhuo Feng. 494-499 [doi]
• Modeling and analysis of (nonstationary) low frequency noise in nano devices: a synergistic approach based on stochastic chemical kineticsA. Gokcen Mahmutoglu, Alper Demir, Jaijeet S. Roychowdhury. 500-507 [doi]
• MOMA: mapping of memory-intensive software-pipelined applications for systems with multiple memory controllersJanmartin Jahn, Santiago Pagani, Jian-Jia Chen, Jörg Henkel. 508-515 [doi]
• An efficient compiler framework for cache bypassing on GPUsXiaolong Xie, Yun Liang, Guangyu Sun, Deming Chen. 516-523 [doi]
• A just-in-time customizable processorLiang Chen, Joseph Tarango, Tulika Mitra, Philip Brisk. 524-531 [doi]
• Temperature tracking: an innovative run-time approach for hardware Trojan detectionDomenic Forte, Chongxi Bao, Ankur Srivastava. 532-539 [doi]
• Redundancy-aware electromigration checking for mesh power gridsSandeep Chatterjee, Mohammad Fawaz, Farid N. Najm. 540-547 [doi]
• Scalable power grid transient analysis via MOR-assisted time-domain simulationsJia Wang, Xuanxing Xiong. 548-552 [doi]
• A vectorless framework for power grid electromigration checkingMohammad Fawaz, Sandeep Chatterjee, Farid N. Najm. 553-560 [doi]
• Parallel power grid analysis using preconditioned GMRES solver on CPU-GPU platformsXuexin Liu, Hai Wang, Sheldon X.-D. Tan. 561-568 [doi]
• Design with FinFETs: design rules, patterns, and variabilityRasit Onur Topaloglu. 569-571 [doi]
• Spin torque devices in embedded memory: model studies and design space explorationArijit Raychowdhury. 572-575 [doi]
• Exploring Boolean and non-Boolean computing with spin torque devicesKaushik Roy, Mrigank Sharad, Deliang Fan, Karthik Yogendra. 576-580 [doi]
• Why the design productivity gap never happenedHarry D. Foster. 581-584 [doi]
• Depth controlled symmetric function fanin tree restructureHua Xiang, Lakshmi N. Reddy, Louise Trevillyan, Ruchir Puri. 585-591 [doi]
• In-placement clock-tree aware multi-bit flip-flop generation for power optimizationChih-Cheng Hsu, Yu-chuan Chen, Mark Po-Hung Lin. 592-598 [doi]
• Clock power minimization using structured latch templates and decision tree inductionSamuel I. Ward, Natarajan Viswanathan, Nancy Y. Zhou, Cliff C. N. Sze, Zhuo Li, Charles J. Alpert, David Z. Pan. 599-606 [doi]
• FPGA simulation engine for customized construction of neural microcircuitsHugh T. Blair, Jason Cong, Di Wu. 607-614 [doi]
• Sample preparation for many-reactant bioassay on DMFBs using common dilution operation sharingChia-Hung Liu, Hao Han Chang, Tung-Che Liang, Juinn-Dar Huang. 615-621 [doi]
• Optimization of polymerase chain reaction on a cyberphysical digital microfluidic biochipYan Luo, Bhargab B. Bhattacharya, Tsung-Yi Ho, Krishnendu Chakrabarty. 622-629 [doi]
• Optimization of interconnects between accelerators and shared memories in dark siliconJason Cong, Bingjun Xiao. 630-637 [doi]
• A polynomial time algorithm for solving the word-length optimization problemKarthick Parashar, Daniel Menard, Olivier Sentieys. 638-645 [doi]
• DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systemsTuo Li 0001, Muhammad Shafique, Semeen Rehman, Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran. 646-653 [doi]
• Trace alignment algorithms for offline workload analysis of heterogeneous architecturesMuhammet Mustafa Ozdal, Aamer Jaleel, Paolo Narváez, Steven M. Burns, Ganapati Srinivasa. 654-661 [doi]
• From statistical model checking to statistical model inference: characterizing the effect of process variations in analog circuitsYan Zhang, Sriram Sankaranarayanan, Fabio Somenzi, Xin Chen 0002, Erika Ábrahám. 662-669 [doi]
• Hardware implementation of BLTL property checkers for acceleration of statistical model checkingKosuke Oshima, Takeshi Matsumoto, Masahiro Fujita. 670-676 [doi]
• Proof logging for computer algebra based SMT solvingOliver Marx, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Alexander Dreyer. 677-684 [doi]
• Conquering the scheduling alternative explosion problem of SystemC symbolic simulationChun-Nan Chou, Chen-Kai Chu, Chung-Yang (Ric) Huang. 685-690 [doi]
• Comprehensive technique for designing and synthesizing TSV fault-tolerant 3D clock treesHeechun Park, Taewhan Kim. 691-696 [doi]
• Low-power timing closure methodology for ultra-low voltage designsWen-Pin Tu, Chung-Han Chou, Shih-Hsu Huang, Shih-Chieh Chang, Yow-Tyng Nieh, Chien-Yung Chou. 697-704 [doi]
• Incremental multiple-scan chain ordering for ECO flip-flop insertionAndrew B. Kahng, Ilgweon Kang, Siddhartha Nath. 705-712 [doi]
• Post-route alleviation of dense meander segments in high-performance printed circuit boardsTsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann. 713-720 [doi]
• Digital logic with molecular reactionsHua Jiang, Marc D. Riedel, Keshab K. Parhi. 721-727 [doi]
• Noise in genetic circuits: hindrance or chance?Cheng-Ju Pan, Hsiao-Chun Huang. 728-731 [doi]
• Sequential logic to transform probabilitiesNaman Saraf, Kia Bazargan. 732-738 [doi]
• Automated generation of efficient instruction decoders for instruction set simulatorsNicolas Fournel, Luc Michel, Frédéric Pétrot. 739-746 [doi]
• Dynamic bandwidth scaling for embedded DSPs with 3D-stacked DRAM and wide I/OsDaniel W. Chang, Young Hoon Son, Jung Ho Ahn, Hoyoung Kim, Minwook Ahn, Michael J. Schulte, Nam Sung Kim. 747-754 [doi]
• ISOMER: integrated selection, partitioning, and placement methodology for reconfigurable architecturesRana Muhammad Bilal, Rehan Hafiz, Muhammad Shafique, Saad Shoaib, Asim Munawar, Jörg Henkel. 755-762 [doi]
• Generalized Boolean symmetries through nested partition refinementHadi Katebi, Karem A. Sakallah, Igor L. Markov. 763-770 [doi]
• Encoding multi-valued functions for symmetryKo-Lung Yuan, Chien-Yen Kuo, Jie-Hong R. Jiang, Meng-Yen Li. 771-778 [doi]
• Approximate logic synthesis under general error magnitude and frequency constraintsJin Miao, Andreas Gerstlauer, Michael Orshansky. 779-786 [doi]
• Partial synthesis through sampling with and without specificationMasahiro Fujita, Satoshi Jo, Shohei Ono, Takeshi Matsumoto. 787-794 [doi]
• Bayesian model fusion: a statistical framework for efficient pre-silicon validation and post-silicon tuning of complex analog and mixed-signal circuitsXin Li, Fa Wang, Shupeng Sun, Chenjie Gu. 795-802 [doi]
• Uncertainty quantification for integrated circuits: stochastic spectral methodsZheng Zhang, Ibrahim M. Elfadel, Luca Daniel. 803-810 [doi]
• Simulation of temporal stochastic phenomena in electronic and biological systems: a comparative review, examples and synergiesAlper Demir, Burak Erman. 811-818 [doi]
• Hardware security: threat models and metricsMasoud Rostami, Farinaz Koushanfar, Jeyavijayan Rajendran, Ramesh Karri. 819-823 [doi]
• A proof-carrying based framework for trusted microprocessor IPYier Jin, Yiorgos Makris. 824-829 [doi]
• A write-time based memristive PUF for hardware security applicationsGarrett S. Rose, Nathan R. McDonald, Lok-Kwong Yan, Bryant T. Wysocki. 830-833 [doi]