Table of Contents

• Automated detection and verification of parity-protected memory elementsEli Arbel, Shlomit Koyfman, Prabhakar Kudva, Shiri Moran. 1-8 [doi]
• Validating direct memory access interfaces with conformance checkingLi Lei, Kai Cong, Zhenkun Yang, Fei Xie. 9-16 [doi]
• Data-parallel simulation for fast and accurate timing validation of CMOS circuitsEric Schneider, Stefan Holst, Xiaoqing Wen, Hans-Joachim Wunderlich. 17-23 [doi]
• Security-aware mapping for TDMA-based real-time distributed systemsChung-Wei Lin, Qi Zhu, Alberto L. Sangiovanni-Vincentelli. 24-31 [doi]
• Reinforcement learning based power management for hybrid electric vehiclesXue Lin, Yanzhi Wang, Paul Bogdan, Naehyuck Chang, Massoud Pedram. 32-38 [doi]
• Functional modeling compiler for system-level design of automotive cyber-physical systemsArquimedes Canedo, Jiang Wan, Mohammad Abdullah Al Faruque. 39-46 [doi]
• BDD-based synthesis of reconfigurable single-electron transistor arraysZheng Zhao, Chian-Wei Liu, Chun-Yao Wang, Weikang Qian. 47-54 [doi]
• Architecting 3D vertical resistive memory for next-generation storage systemsCong Xu, Pai-Yu Chen, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie 0001. 55-62 [doi]
• Reduction and IR-drop compensations techniques for reliable neuromorphic computing systemsBeiye Liu, Hai Li, Yiran Chen, Xin Li, Tingwen Huang, Qing Wu, Mark Barnell. 63-70 [doi]
• Application driven high level design in the era of heterogeneous computingRuchir Puri. 71 [doi]
• High level design for wearables and IoTYatin Hoskote, Ilya Klotchkov. 72 [doi]
• Towards a standard flow for system level power modelingNagu R. Dhanwada, William Rhett Davis, Jerry Frenkil. 73 [doi]
• The role of adaptation and resiliency in computation and power managementArijit Raychowdhury, Saad Bin Nasir, Samantak Gangopadhyay. 74-79 [doi]
• Channel-adaptive zero-margin & process-adaptive self-healing communication circuits/systemsShreyas Sen. 80-85 [doi]
• Modeling oscillator arrays for video analytic applicationsYan Fang, Victor V. Yashin, Andrew J. Seel, Brandon Jennings, Reggie Barnett, Donald M. Chiarulli, Steven P. Levitan. 86-91 [doi]
• Cellular neural networks for image analysis using steep slope devicesIndranil Palit, Qiuwen Lou, Michael T. Niemier, Behnam Sedighi, Joseph Nahas, Xiaobo Sharon Hu. 92-95 [doi]
• A hardware accelerated multilevel visual classifier for embedded visual-assist systemsMatthew Cotter, Siddharth Advani, Jack Sampson, Kevin M. Irick, Vijaykrishnan Narayanan. 96-100 [doi]
• DRC-based hotspot detection considering edge tolerance and incomplete specificationYen-Ting Yu, Iris Hui-Ru Jiang, Yumin Zhang, Charles Chiang. 101-107 [doi]
• Triple patterning lithography aware optimization for standard cell based designJian Kuang 0001, Wing-Kai Chow, Evangeline F. Y. Young. 108-115 [doi]
• Triple patterning aware detailed placement with constrained pattern assignmentHaitong Tian, Yuelin Du, Hongbo Zhang, Zigang Xiao, Martin D. F. Wong. 116-123 [doi]
• Sub-20 nm design technology co-optimization for standard cell logicKaushik Vaidyanathan, Lars Liebmann, Andrzej J. Strojwas, Larry Pileggi. 124-131 [doi]
• Energy-efficient architecture for advanced video memoryFelipe Sampaio, Muhammad Shafique, Bruno Zatt, Sergio Bampi, Jörg Henkel. 132-139 [doi]
• Compaction-free compressed cache for high performance multi-core systemPo-Yang Hsu, Pei-Lan Lin, TingTing Hwang. 140-147 [doi]
• A non-volatile memory based physically unclonable function without helper dataWenjie Che, Jim Plusquellic, Swarup Bhunia. 148-153 [doi]
• Cryptoraptor: high throughput reconfigurable cryptographic processorGokhan Sayilar, Derek Chiou. 154-161 [doi]
• BIST-PUF: online, hardware-based evaluation of physically unclonable circuit identifiersSiam U. Hussain, Sudha Yellapantula, Mehrdad Majzoobi, Farinaz Koushanfar. 162-169 [doi]
• Shielding and securing integrated circuits with sensorsDavood Shahrjerdi, Jeyavijayan Rajendran, Siddharth Garg, Farinaz Koushanfar, Ramesh Karri. 170-174 [doi]
• Power consumption characterization, modeling and estimation of electric vehiclesNaehyuck Chang, Donkyu Baek, Jeongmin Hong. 175-182 [doi]
• Vulnerability assessment and defense technology for smart home cybersecurity considering pricing cyberattacksYang Liu, Shiyan Hu, Tsung-Yi Ho. 183-190 [doi]
• Co-scheduling of HVAC control, EV charging and battery usage for building energy efficiencyTianshu Wei, Qi Zhu, Mehdi Maasoumy. 191-196 [doi]
• Real time anomaly detection in wide area monitoring of smart gridsJie Wu, Jinjun Xiong, Prasenjit Shil, Yiyu Shi. 197-204 [doi]
• Variation aware optimal threshold voltage computation for on-chip noise sensorsTao Wang, Chun Zhang, Jinjun Xiong, Pei-Wen Luo, Liang-Chia Cheng, Yiyu Shi. 205-212 [doi]
• More effective power-gated circuit optimization with multi-bit retention registersShu-Hung Lin, Mark Po-Hung Lin. 213-217 [doi]
• An efficient spectral graph sparsification approach to scalable reduction of large flip-chip power gridsXueqian Zhao, Zhuo Feng, Cheng Zhuo. 218-223 [doi]
• Reinforcement learning based self-adaptive voltage-swing adjustment of 2.5D I/Os for many-core microprocessor and memory communicationHantao Huang, Sai Manoj Pudukotai Dinakarrao, Dongjun Xu, Hao Yu, Zhigang Hao. 224-229 [doi]
• Fast lithographic mask optimization considering process variationYu-Hsuan Su, Yu-Chen Huang, Liang-Chun Tsai, Yao-Wen Chang, Shayak Banerjee. 230-237 [doi]
• A fast process variation and pattern fidelity aware mask optimization algorithmAhmed Awad, Atsushi Takahashi, Satoshi Tanaka, Chikaaki Kodama. 238-245 [doi]
• Benchmarking of mask fracturing heuristicsTuck Boon Chan, Puneet Gupta, Kwangsoo Han, Abde Ali Kagalwalla, Andrew B. Kahng, Emile Sahouria. 246-253 [doi]
• Overlapping-aware throughput-driven stencil planning for E-beam lithographyJian Kuang 0001, Evangeline F. Y. Young. 254-261 [doi]
• Protecting integrated circuits from piracy with test-aware logic lockingStephen M. Plaza, Igor L. Markov. 262-269 [doi]
• Hardware obfuscation using PUF-based logicJames Bradley Wendt, Miodrag Potkonjak. 270-277 [doi]
• On trojan side channel design and identificationJie Zhang, Guantong Su, Yannan Liu, Lingxiao Wei, Feng Yuan, Guoqiang Bai, Qiang Xu. 278-285 [doi]
• Design automation for biochemistry synthesis on a digital microfluidic lab-on-a-chipKrishnendu Chakrabarty, Bhargab B. Bhattacharya, Ansuman Banerjee. 286-288 [doi]
• High-radix on-chip networks with low-radix routersAnimesh Jain, Ritesh Parikh, Valeria Bertacco. 289-294 [doi]
• Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cubeYinhe Han, Ying Wang, Huawei Li, Xiaowei Li 0001. 295-300 [doi]
• Using multi-level cell STT-RAM for fast and energy-efficient local checkpointingPing Chi, Cong Xu, Tao Zhang, Xiangyu Dong, Yuan Xie 0001. 301-308 [doi]
• Modeling and analysis of nonstationary low-frequency noise in circuit simulators: enabling non monte carlo techniquesA. Gokcen Mahmutoglu, Alper Demir. 309-315 [doi]
• MPME-DP: multi-population moment estimation via dirichlet process for efficient validation of analog/mixed-signal circuitsManzil Zaheer, Xin Li, Chenjie Gu. 316-323 [doi]
• Fast statistical analysis of rare circuit failure events via subset simulation in high-dimensional variation spaceShupeng Sun, Xin Li. 324-331 [doi]
• Removing concurrency for rapid functional verificationStephen Longfield Jr., Rajit Manohar. 332-339 [doi]
• Towards formal evaluation and verification of probabilistic designNian-Ze Lee, Jie-Hong R. Jiang. 340-347 [doi]
• Silicon fault diagnosis using sequence interpolation with backbonesCharlie Shucheng Zhu, Georg Weissenbacher, Sharad Malik. 348-355 [doi]
• The overview of 2014 CAD contest at ICCADIris Hui-Ru Jiang, Natarajan Viswanathan, Tai-Chen Chen, Jin-Fu Li. 356 [doi]
• ICCAD-2014 CAD contest in simultaneous CNF encoder optimization with SAT solver setting selection and benchmark suiteChih-Jen Hsu, Wei-Hsun Lin, Chi-An Wu, Kei-Yong Khoo. 357-360 [doi]
• ICCAD-2014 CAD contest in incremental timing-driven placement and benchmark suiteMyung-Chul Kim, Jin Hu, Natarajan Viswanathan. 361-366 [doi]
• ICCAD-2014 CAD contest in design for manufacturability flow for advanced semiconductor nodes and benchmark suiteRasit Onur Topaloglu. 367-368 [doi]
• Optimal offloading control for a mobile device based on a realistic battery model and semi-markov decision processShuang Chen, Yanzhi Wang, Massoud Pedram. 369-375 [doi]
• A learning-on-cloud power management policy for smart devicesGung-Yu Pan, Bo-Cheng Charles Lai, Sheng-Yen Chen, Jing-Yang Jou. 376-381 [doi]
• Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurationsIris Hui-Ru Jiang, Gi-Joon Nam, Hua-Yu Chang, Sani R. Nassif, Jerry Hayes. 382-388 [doi]
• A resource-level parallel approach for global-routing-based routing congestion estimation and a method to quantify estimation accuracyWen-Hao Liu, Zhen-Yu Peng, Ting-Chi Wang. 389-396 [doi]
• MCFRoute: a detailed router based on multi-commodity flow methodXiaotao Jia, Yici Cai, Qiang Zhou, Gang Chen, Zhuoyuan Li, Zuowei Li. 397-404 [doi]
• Exact routing for digital microfluidic biochips with temporary blockagesOliver Keszocze, Robert Wille, Rolf Drechsler. 405-410 [doi]
• Design things for the internet of things: an EDA perspectiveGang Qu, Lin Yuan. 411-416 [doi]
• Security of IoT systems: design challenges and opportunitiesTeng Xu, James Bradley Wendt, Miodrag Potkonjak. 417-423 [doi]
• Towards a rich sensing stack for IoT devicesChenguang Shen, Haksoo Choi, Supriyo Chakraborty, Mani B. Srivastava. 424-427 [doi]
• IR-drop based electromigration assessment: parametric failure chip-scale analysisValeriy Sukharev, Xin Huang, Hai-Bao Chen, Sheldon X.-D. Tan. 428-433 [doi]
• Lifetime optimization for real-time embedded systems considering electromigration effectsTaeyoung Kim, Bowen Zheng, Hai-Bao Chen, Qi Zhu, Valeriy Sukharev, Sheldon X.-D. Tan. 434-439 [doi]
• Accurate full-chip estimation of power map, current densities and temperature for EM assessmentMarko Chew, Ara Aslyan, Jun-Ho Choy, Xin Huang. 440-445 [doi]
• TonyChopper: a desynchronization packageZhao Wang, Xiao He, Carl M. Sechen. 446-453 [doi]
• SuperPUF: integrating heterogeneous physically unclonable functionsMichael Wang, Andrew Yates, Igor L. Markov. 454-461 [doi]
• Constrained interpolation for guided logic synthesisAna Petkovska, David Novo, Alan Mishchenko, Paolo Ienne. 462-469 [doi]
• Logic synthesis and a generalized notation for memristor-realized material implication gatesAnika Raghuvanshi, Marek A. Perkowski. 470-477 [doi]
• Towards interdependencies of aging mechanismsHussam Amrouch, Victor M. van Santen, Thomas Ebi, Volker Wenzel, Jörg Henkel. 478-485 [doi]
• A systematic approach for analyzing and optimizing cell-internal signal electromigrationGracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar. 486-491 [doi]
• ReSCALE: recalibrating sensor circuits for aging and lifetime estimation under BTIDeepashree Sengupta, Sachin S. Sapatnekar. 492-497 [doi]
• max testingMichihiro Shintani, Takashi Sato. 498-503 [doi]
• Multi-level approximate logic synthesis under general error constraintsJin Miao, Andreas Gerstlauer, Michael Orshansky. 504-510 [doi]
• On error modeling and analysis of approximate addersLi Li 0021, Hai Zhou. 511-518 [doi]
• Generating multiple correlated probabilities for MUX-based stochastic computing architectureYili Ding, Yi Wu, Weikang Qian. 519-526 [doi]
• PowerCool: simulation of integrated microfluidic power generation in bright silicon MPSoCsArvind Sridhar, Mohamed M. Sabry, Patrick Ruch, David Atienza, Bruno Michel. 527-534 [doi]
• Workload dependent evaluation of thin-film thermoelectric devices for on-chip cooling and energy harvestingSri Harsha Choday, Kon-Woo Kwon, Kaushik Roy. 535-541 [doi]
• Fast and accurate emissivity and absolute temperature maps measurement for integrated circuitsHsueh-Ling Yu, Yih-Lang Li, Tzu-Yi Liao, Tianchen Wang, Yiyu Shi, Shu-Fei Tsai. 542-549 [doi]
• Efficient layout generation and evaluation of vertical channel devicesWei-Che Wang, Puneet Gupta. 550-556 [doi]
• Thermal-aware synthesis of integrated photonic ring resonatorsChristopher Condrat, Priyank Kalla, Steve Blair. 557-564 [doi]
• Full chip impact study of power delivery network designs in monolithic 3D ICsSandeep Kumar Samal, Kambiz Samadi, Pratyush Kamal, Yang Du, Sung Kyu Lim. 565-572 [doi]
• Evolving physical design paradigms in the transition from 20/14 to 10nm process technology nodesLuigi Capodieci. 573 [doi]
• Design and manufacturing process co-optimization in nano-technologyMeng-Kai Hsu, Nitesh Katta, Homer Yen-Hung Lin, Keny Tzu-Hen Lin, King Ho Tam, Ken Chung-Hsing Wang. 574-581 [doi]
• Design and technology co-optimization near single-digit nodesLars W. Liebmann, Rasit Onur Topaloglu. 582-585 [doi]
• Automated and quality-driven requirements engineeringRolf Drechsler, Mathias Soeken, Robert Wille. 586-590 [doi]
• TAU 2014 contest on removing common path pessimism during timing analysisJin Hu, Debjit Sinha, Igor Keller. 591 [doi]
• Common path pessimism removal: an industry perspectiveVibhor Garg. 592-595 [doi]
• Fast path-based timing analysis for CPPRTsung-Wei Huang, Pei-Ci Wu, Martin D. F. Wong. 596-599 [doi]
• iTimerC: common path pessimism removal using effective reduction methodsYu-Ming Yang, Yu-wei Chang, Iris Hui-Ru Jiang. 600-605 [doi]
• TKtimer: fast & accurate clock network pessimism removalChristos Kalonakis, Charalampos Antoniadis, Panagiotis Giannakou, Dimos Dioudis, Georgios Pinitas, Georgios I. Stamoulis. 606-610 [doi]
• A novel linear algebra method for the determination of periodic steady states of nonlinear oscillatorsHaotian Liu, Kim Batselier, Ngai Wong. 611-617 [doi]
• A unifying and robust method for efficient envelope-following simulation of PWM/PFM DC-DC convertersYa Wang, Peng Li, Suming Lai. 618-625 [doi]
• Large-signal MOSFET modeling using frequency-domain nonlinear system identificationMoning Zhang, Yang Tang, Zuochang Ye. 626-632 [doi]
• Pragma-based floating-to-fixed point conversion for the emulation of analog behavioral modelsFrank Austin Nothaft, Luis Fernandez, Stephen Cefali, Nishant Shah, Jacob Rael, Luke Darnell. 633-640 [doi]
• Asynchronous circuit placement by lagrangian relaxationGang Wu, Tao Lin, Hsin-Ho Huang, Chris Chu, Peter A. Beerel. 641-646 [doi]
• Efficient and effective packing and analytical placement for large-scale heterogeneous FPGAsYu-Chen Chen, Sheng-Yen Chen, Yao-Wen Chang. 647-654 [doi]
• A hierarchical approach for generating regular floorplansJavier de San Pedro, Jordi Cortadella, Antoni Roca. 655-662 [doi]
• Planning and placing power clamps for effective CDM protectionHsin-Chun Lin, Sean S.-Y. Liu, Hung-Ming Chen. 663-669 [doi]
• On application of data mining in functional debugKuo-Kai Hsieh, Wen Chen, Li-C. Wang, Jayanta Bhadra. 670-675 [doi]
• Improving the efficiency of automated debugging of pipelined microprocessors by symmetry breaking in modular schemes for boolean encoding of cardinalityMiroslav N. Velev, Ping Gao 0002. 676-683 [doi]
• Multiple clock domain synchronization in a QBF-based verification environmentDjordje Maksimovic, Bao Le, Andreas G. Veneris. 684-689 [doi]
• Probabilistic model checking for comparative analysis of automated air traffic control systemsYang Zhao, Kristin Y. Rozier. 690-695 [doi]
• A zonotoped macromodeling for reachability verification of eye-diagram in high-speed I/O links with jitterSai Manoj Pudukotai Dinakarrao, Hao Yu, Chenji Gu, Cheng Zhuo. 696-701 [doi]
• Random walk based capacitance extraction for 3D ICs with cylindrical inter-tier-viasWenjian Yu, Chao Zhang, Qing Wang, Yiyu Shi. 702-709 [doi]
• Self-learning MIMO-RF receiver systems: process resilient real-time adaptation to channel conditions for low power operationDebashis Banerjee, Barry John Muldrey, Shreyas Sen, Xian Wang, Abhijit Chatterjee. 710-717 [doi]
• Multithreaded pipeline synthesis for data-parallel kernelsMingxing Tan, Bin Liu 0006, Steve Dai, Zhiru Zhang. 718-725 [doi]
• Toward scalable source level accuracy analysis for floating-point to fixed-point conversionGaël Deest, Tomofumi Yuki, Olivier Sentieys, Steven Derrien. 726-733 [doi]
• Warranty-aware page management for PCM-based embedded systemsSheng-Wei Cheng, Yu-Fen Chang, Yuan-Hao Chang, Hsin-Wen Wei, Wei Kuan Shih. 734-741 [doi]
• Frequency-centric resonant rotary clock distribution network designYing Teng, Baris Taskin. 742-749 [doi]
• Opportunistic through-silicon-via inductor utilization in LC resonant clocks: concept and algorithmsUmamaheswara Rao Tida, Varun Mittapalli, Cheng Zhuo, Yiyu Shi. 750-757 [doi]
• UI-timer: an ultra-fast clock network pessimism removal algorithmTsung-Wei Huang, Pei-Ci Wu, Martin D. F. Wong. 758-765 [doi]