Abstract is missing.
- Scope - quality retaining display rendering workload scaling based on user-smartphone distanceKent W. Nixon, Xiang Chen, Yiran Chen. 1 [doi]
- NVSim-CAM: a circuit-level simulator for emerging nonvolatile memory based content-addressable memoryShuangchen Li, Liu Liu, Peng Gu, Cong Xu, Yuan Xie. 2 [doi]
- Design technology for fault-free and maximally-parallel wavelength-routed optical networks-on-chipAndrea Peano, Luca Ramini, Marco Gavanelli, Maddalena Nonato, Davide Bertozzi. 3 [doi]
- FAst generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applicationsAna Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert K. Brayton, Paolo Ienne. 4 [doi]
- Analytic approaches to the collapse operation and equivalence verification of threshold logic circuitsNian-Ze Lee, Hao-Yuan Kuo, Yi-Hsiang Lai, Jie-Hong R. Jiang. 5 [doi]
- A flash-based digital circuit design flowMonther Abusultan, Sunil P. Khatri. 6 [doi]
- MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodesYibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li 0001, Charles J. Alpert, David Z. Pan. 7 [doi]
- OWARU: free space-aware timing-driven incremental placementJinwook Jung, Gi-Joon Nam, Lakshmi Reddy, Iris Hui-Ru Jiang, Youngsoo Shin. 8 [doi]
- Detailed placement for modern FPGAs using 2D dynamic programmingShounak Dhar, Saurabh N. Adya, Love Singhal, Mahesh A. Iyer, David Z. Pan. 9 [doi]
- Security and privacy threats to on-chip non-volatile memories and countermeasuresSwaroop Ghosh, Mohammad Nasim Imtiaz Khan, Asmit De, Jae-Won Jang. 10 [doi]
- Security engineering of nanostructures and nanomaterialsDavood Shahrjerdi, B. Nasri, D. Armstrong, A. Alharbi, Ramesh Karri. 11 [doi]
- Caffeine: towards uniformed representation and acceleration for deep convolutional neural networksChen Zhang, Zhenman Fang, Peipei Zhou, Peichen Pan, Jason Cong. 12 [doi]
- Re-architecting the on-chip memory sub-system of machine-learning accelerator for embedded devicesYing Wang, Huawei Li, Xiaowei Li. 13 [doi]
- A data locality-aware design framework for reconfigurable sparse matrix-vector multiplication kernelSicheng Li, Yandan Wang, Wujie Wen, Yu Wang, Yiran Chen, Hai Li. 14 [doi]
- Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computingPai-Yu Chen, Jae-sun Seo, Yu Cao, Shimeng Yu. 15 [doi]
- A new tightly-coupled transient electro-thermal simulation method for power electronicsQuan Chen, Wim Schoenmaker. 16 [doi]
- A tensor-based volterra series black-box nonlinear system identification and simulation frameworkKim Batselier, Zhongming Chen, Haotian Liu, Ngai Wong. 17 [doi]
- Efficient statistical analysis for correlated rare failure events via asymptotic probability approximationHandi Yu, Jun Tao, Changhai Liao, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li 0001. 18 [doi]
- Duplex: simultaneous parameter-performance exploration for optimizing analog circuitsSeyed Nematollah Ahmadyan, Shobha Vasudevan. 19 [doi]
- Improved flop tray-based design implementation for power reductionAndrew B. Kahng, Jiajia Li, Lutong Wang. 20 [doi]
- RC-aware global routingRudolf Scheifele. 21 [doi]
- Scalable, high-quality, SAT-based multi-layer escape routingSam Bayless, Holger H. Hoos, Alan J. Hu. 22 [doi]
- Redistribution layer routing for integrated fan-out wafer-level chip-scale packagesBo-Qiao Lin, Ting-Chou Lin, Yao-Wen Chang. 23 [doi]
- The architecture value engine: measuring and delivering sustainable SoC improvementJuan Antonio Carballo, Bangqi Xu. 24 [doi]
- Circuit valorization in the IC design ecosystemJosé Pineda de Gyvez, Hamed Fatemi, Maarten Vertregt. 25 [doi]
- Interconnect-aware device targeting from PPA perspectiveMustafa Badaroglu, Jeff Xu. 26 [doi]
- Measuring progress and value of IC implementation technologyAndrew B. Kahng, Hyein Lee, Jiajia Li. 27 [doi]
- Provably secure camouflaging strategy for IC protectionMeng Li, Kaveh Shamsi, Travis Meade, Zheng Zhao, Bei Yu, Yier Jin, David Z. Pan. 28 [doi]
- CamoPerturb: secure IC camouflaging for minterm protectionMuhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran. 29 [doi]
- Chip editor: leveraging circuit edit for logic obfuscation and trusted fabricationBicky Shakya, Navid Asadizanjani, Domenic Forte, Mark Mohammad Tehranipoor. 30 [doi]
- Arbitrary streaming permutations with minimum memory and latencyThaddeus Koehn, Peter M. Athanas. 31 [doi]
- Multibank memory optimization for parallel data access in multiple data arraysShouyi Yin, Zhicong Xie, Chenyue Meng, Leibo Liu, Shaojun Wei. 32 [doi]
- Allocation of multi-bit flip-flops in logic synthesis for power optimizationDongyoun Yi, Taewhan Kim. 33 [doi]
- Model-based design of resource-efficient automotive control softwareWanli Chang, Debayan Roy, Licong Zhang, Samarjit Chakraborty. 34 [doi]
- Testing automotive embedded systems under X-in-the-loop setupsGhizlane Tibba, Christoph Malz, Christoph Stoermer, Natarajan Nagarajan, Licong Zhang, Samarjit Chakraborty. 35 [doi]
- Efficient statistical validation of machine learning systems for autonomous drivingWeijing Shi, Mohamed Baker Alawieh, Xin Li, Huafeng Yu, Nikos Arechiga, Nobuyuki Tomatsu. 36 [doi]
- CONVINCE: a cross-layer modeling, exploration and validation framework for next-generation connected vehiclesBowen Zheng, Chung-Wei Lin, Huafeng Yu, Hengyi Liang, Qi Zhu. 37 [doi]
- Overview of the 2016 CAD contest at ICCADShih-Hsu Huang, Rung-Bin Lin, Myung-Chul Kim, Shigetoshi Nakatake. 38 [doi]
- ICCAD-2016 CAD contest in large-scale identical fault searchTangent Wei, Luke Lin. 39 [doi]
- ICCAD-2016 CAD contest in non-exact projective NPNP boolean matching and benchmark suiteChi-An (Rocky) Wu, Chih-Jen (Jacky) Hsu, Kei-Yong Khoo. 40 [doi]
- ICCAD-2016 CAD contest in pattern classification for integrated circuit design space analysis and benchmark suiteRasit Onur Topaloglu. 41 [doi]
- OpenDesign flow database: the infrastructure for VLSI design and design automation researchJinwook Jung, Iris Hui-Ru Jiang, Gi-Joon Nam, Victor N. Kravets, Laleh Behjat, Yih-Lang Li. 42 [doi]
- Malicious LUT: a stealthy FPGA trojan injected and triggered by the design flowChristian Krieg, Clifford Wolf, Axel Jantsch. 43 [doi]
- On detecting delay anomalies introduced by hardware trojansDylan Ismari, Jim Plusquellic, Charles Lamech, Swarup Bhunia, Fareena Saqib. 44 [doi]
- An optimization-theoretic approach for attacking physical unclonable functionsYuntao Liu, Yang Xie, Chongxi Bao, Ankur Srivastava. 45 [doi]
- LRR-DPUF: learning resilient and reliable digital physical unclonable functionJin Miao, Meng Li, Subhendu Roy, Bei Yu. 46 [doi]
- Enabling online learning in lithography hotspot detection with information-theoretic feature optimizationHang Zhang, Bei Yu, Evangeline F. Y. Young. 47 [doi]
- Incorporating cut redistribution with mask assignment to enable 1D gridded designJian Kuang 0001, Evangeline F. Y. Young, Bei Yu. 48 [doi]
- VCR: simultaneous via-template and cut-template-aware routing for directed self-assembly technologyYu-Hsuan Su, Yao-Wen Chang. 49 [doi]
- DSA-compliant routing for two-dimensional patterns using block copolymer lithographyYu-Hsuan Su, Yao-Wen Chang. 50 [doi]
- The art of semi-formal bug huntingPradeep Kumar Nalla, Raj Kumar Gajavelly, Jason Baumgartner, Hari Mony, Robert Kanzelman, Alexander Ivrii. 51 [doi]
- Compiled symbolic simulation for systemCVladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler. 52 [doi]
- Exact diagnosis using boolean satisfiabilityHeinz Riener, Görschwin Fey. 53 [doi]
- Efficient and accurate analysis of single event transients propagation using SMT-based techniquesGhaith Bany Hamad, Ghaith Kazma, Otmane Aït Mohamed, Yvon Savaria. 54 [doi]
- Power delivery in 3D packages: current crowding effects, dynamic IR drop and compensation network using sensors (invited paper)Sukeshwar Kannan, Mehdi Sadi, Luke England. 55 [doi]
- Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integrationDylan Stow, Itir Akgun, Russell Barnes, Peng Gu, Yuan Xie 0001. 56 [doi]
- Energy-efficient and reliable 3D network-on-chip (NoC): architectures and optimization algorithmsSourav Das, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty. 57 [doi]
- The hype, myths, and realities of testing 3D integrated circuitsRan Wang, Sergej Deutsch, Mukesh Agrawal, Krishnendu Chakrabarty. 58 [doi]
- TASA: toolchain-agnostic static software randomisation for critical real-time systemsLeonidas Kosmidis, Roberto Vargas, David Morales, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla. 59 [doi]
- Splitting functions in code management on scratchpad memoriesYoungbin Kim, Jian Cai, Yooseong Kim, Kyoungwoo Lee, Aviral Shrivastava. 60 [doi]
- Adaptive performance prediction for integrated GPUsUjjwal Gupta, Joseph Campbell, Ümit Y. Ogras, Raid Ayoub, Michael Kishinevsky, Francesco Paterna, Suat Gumussoy. 61 [doi]
- Energy-efficient fault tolerance approach for internet of things applicationsTeng Xu 0001, Miodrag Potkonjak. 62 [doi]
- Critical path isolation for time-to-failure extension and lower voltage operationYutaka Masuda, Masanori Hashimoto, Takao Onoye. 63 [doi]
- Control synthesis and delay sensor deployment for efficient ASV designsChaofan Li, Sachin S. Sapatnekar, Jiang Hu. 64 [doi]
- Performance driven routing for modern FPGAsPariVallal Kannan, Satish Sivaswamy. 65 [doi]
- UTPlaceF: a routability-driven FPGA placer with physical and congestion aware packingWuxi Li, Shounak Dhar, David Z. Pan. 66 [doi]
- RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAsChak-Wa Pui, Gengjie Chen, Wing-Kai Chow, Ka Chun Lam, Jian Kuang 0001, Peishan Tu, Hang Zhang, Evangeline F. Y. Young, Bei Yu. 67 [doi]
- GPlace: a congestion-aware placement tool for ultrascale FPGAsRyan Pattison, Ziad Abuowaimer, Shawki Areibi, Gary Gréwal, Anthony Vannelli. 68 [doi]
- Resiliency in dynamically power managed designsLiangzhen Lai, Vikas Chandra, Rob Aitken. 69 [doi]
- Dynamic reliability management for near-threshold dark silicon processorsTaeyoung Kim, Zeyu Sun, Chase Cook, Jagadeesh Gaddipati, Hai Wang, Hai-Bao Chen, Sheldon X.-D. Tan. 70 [doi]
- A cross-layer approach for resiliency and energy efficiency in near threshold computingMohammad Saber Golanbari, Anteneh Gebregiorgis, Fabian Oboril, Saman Kiamehr, Mehdi Baradaran Tahoori. 71 [doi]
- Design space exploration of drone infrastructure for large-scale delivery servicesSangyoung Park, Licong Zhang, Samarjit Chakraborty. 72 [doi]
- Multi-objective design optimization for flexible hybrid electronicsGanapati Bhat, Ujjwal Gupta, Nicholas Tran, Jaehyun Park, Sule Ozev, Ümit Y. Ogras. 73 [doi]
- KCAD: kinetic cyber-attack detection method for cyber-physical additive manufacturing systemsSujit Rokka Chhetri, Arquimedes Canedo, Mohammad Abdullah Al Faruque. 74 [doi]
- Autonomous sensor-context learning in dynamic human-centered internet-of-things environmentsSeyed Ali Rokni, Hassan Ghasemzadeh. 75 [doi]
- Formulating customized specifications for resource allocation problem of distributed embedded systemsXinhai Zhang, Lei Feng, Martin Törngren, De-Jiu Chen. 76 [doi]
- A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loopsGiuseppe Natale, Giulio Stramondo, Pietro Bressana, Riccardo Cattaneo, Donatella Sciuto, Marco D. Santambrogio. 77 [doi]
- Efficient memory compression in deep neural networks using coarse-grain sparsification for speech applicationsDeepak Kadetotad, Sairam Arunachalam, Chaitali Chakrabarti, Jae-sun Seo. 78 [doi]
- Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-designWarren Kemmerer, Wei Zuo, Deming Chen. 79 [doi]
- Architectural-space exploration of approximate multipliersSemeen Rehman, Walaa El-Harouni, Muhammad Shafique, Akash Kumar 0001, Jörg Henkel. 80 [doi]
- Design of power-efficient approximate multipliers for approximate artificial neural networksVojtech Mrazek, Syed Shakib Sarwar, Lukás Sekanina, Zdenek Vasícek, Kaushik Roy 0001. 81 [doi]
- Automated error prediction for approximate sequential circuitsAmrut Kapare, Hari Cherupalli, John Sartori. 82 [doi]
- Approximation-aware rewriting of AIGs for error tolerant applicationsArun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler. 83 [doi]
- Properties first? a new design methodology for hardware, and its perspectives in safety analysisJoakim Urdahl, Shrinidhi Udupi, Tobias Ludwig, Dominik Stoffel, Wolfgang Kunz. 84 [doi]
- Where formal verification can help in functional safety analysisAlessandro Bernardini, Wolfgang Ecker, Ulf Schlichtmann. 85 [doi]
- Formal approaches to design of active cell balancing architectures in battery management systemsSebastian Steinhorst, Martin Lukasiewycz. 86 [doi]
- How much cost reduction justifies the adoption of monolithic 3D ICs at 7nm node?Bon Woong Ku, Peter Debacker, Dragomir Milojevic, Praveen Raghavan, Sung Kyu Lim. 87 [doi]
- A novel unified dummy fill insertion framework with SQP-based optimization methodYudong Tao, Changhao Yan, Yibo Lin, Sheng-Guo Wang, David Z. Pan, Xuan Zeng. 88 [doi]
- Efficient yield estimation through generalized importance sampling with application to NBL-assisted SRAM bitcellsLorenzo Ciampolini, Jean-Christophe Lafont, Faress Tissafi-Drissi, Jean-Paul Morin, David Turgis, Xavier Jonsson, Cyril Desclèves, Joseph Nguyen. 89 [doi]
- Are proximity attacks a threat to the security of split manufacturing of integrated circuits?Jonathon Magaña, Daohang Shi, Azadeh Davoodi. 90 [doi]
- Making split-fabrication more securePing-Lin Yang, Malgorzata Marek-Sadowska. 91 [doi]
- A machine learning approach to fab-of-origin attestationAli Ahmadi, Mohammad-Mahdi Bidmeshki, Amit Nahar, Bob Orr, Michael Pas, Yiorgos Makris. 92 [doi]
- OpenRAM: an open-source memory compilerMatthew R. Guthaus, James E. Stine, Samira Ataei, Brian Chen, Bin Wu, Mehedi Sarwar. 93 [doi]
- A hardware-based technique for efficient implicit information flow trackingJangseop Shin, Hongce Zhang, JinYong Lee, Ingoo Heo, Yu-Yuan Chen, Ruby B. Lee, Yunheung Paek. 94 [doi]
- Imprecise security: quality and complexity tradeoffs for hardware information flow trackingWei Hu, Andrew Becker, Armita Ardeshiricham, Yu Tai, Paolo Ienne, Dejun Mu, Ryan Kastner. 95 [doi]
- Encasing block ciphers to foil key recovery attempts via side channelGiovanni Agosta, Alessandro Barenghi, Gerardo Pelosi, Michele Scandale. 96 [doi]
- Security of neuromorphic computing: thwarting learning attacks using memristor's obsolescence effectChaofei Yang, Beiye Liu, Hai Li, Yiran Chen, Wujie Wen, Mark Barnell, Qing Wu, Jeyavijayan Rajendran. 97 [doi]
- Generation and use of statistical timing macro-models considering slew and load variabilityDebjit Sinha, Vladimir Zolotov, Jin Hu, Sheshashayee K. Raghunathan, Adil Bhanji, Christine M. Casey. 98 [doi]
- TinySPICE plus: scaling up statistical SPICE simulations on GPU leveraging shared-memory based sparse matrix solution techniquesLengfei Han, Zhuo Feng. 99 [doi]
- PieceTimer: a holistic timing analysis framework considering setup/hold time interdependency using a piecewise modelGrace Li Zhang, Bing Li, Ulf Schlichtmann. 100 [doi]
- A fast layer elimination approach for power grid reductionAbdul-Amir Yassine, Farid N. Najm. 101 [doi]
- A deterministic approach to stochastic computationDevon Jenson, Marc Riedel. 102 [doi]
- Control-fluidic CoDesign for paper-based digital microfluidic biochipsQin Wang, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li, Ulf Schlichtmann, Yici Cai. 103 [doi]
- Neural networks designing neural networks: multi-objective hyper-parameter optimizationSean C. Smithson, Guang Yang, Warren J. Gross, Brett H. Meyer. 104 [doi]
- Error recovery in a micro-electrode-dot-array digital microfluidic biochip?Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, Krishnendu Chakrabarty, Miroslav Pajic, Tsung-Yi Ho, Chen-Yi Lee. 105 [doi]
- Privacy protection via appliance scheduling in smart homesJie Wu, Jinglan Liu, Xiaobo Sharon Hu, Yiyu Shi. 106 [doi]
- Framework designs to enhance reliable and timely services of disaster management systemsChi-Sheng Shih, Pi-Cheng Hsiu, Yuan-Hao Chang, Tei-Wei Kuo. 107 [doi]
- Analysis of production data manipulation attacks in petroleum cyber-physical systemsXiaodao Chen, Yuchen Zhou, Hong Zhou, Chaowei Wan, Qi Zhu, Wenchao Li, Shiyan Hu. 108 [doi]
- Security challenges in smart surveillance systems and the solutions based on emerging nano-devicesChaofei Yang, Chunpeng Wu, Hai Li, Yiran Chen, Mark Barnell, Qing Wu. 109 [doi]
- Fast physics-based electromigration checking for on-die power gridsSandeep Chatterjee, Valeriy Sukharev, Farid N. Najm. 110 [doi]
- Exploring aging deceleration in FinFET-based multi-core systemsErmao Cai, Dimitrios Stamoulis, Diana Marculescu. 111 [doi]
- An efficient and accurate algorithm for computing RC current response with applications to EM reliability evaluationZhong Guan, Malgorzata Marek-Sadowska. 112 [doi]
- Voltage-based electromigration immortality check for general multi-branch interconnectsZeyu Sun, Ertugrul Demircan, Mehul D. Shrof, Taeyoung Kim, Xin Huang, Sheldon X.-D. Tan. 113 [doi]
- Exploiting randomness in sketching for efficient hardware implementation of machine learning applicationsYe Wang, Constantine Caramanis, Michael Orshansky. 114 [doi]
- Making neural encoding robust and energy efficient: an advanced analog temporal encoder for brain-inspired computing systemsChenyuan Zhao, Jialing Li, Yang Yi. 115 [doi]
- Statistical methodology to identify optimal placement of on-chip process monitors for predicting fmaxSzu-Pang Mu, Wen-Hsiang Chang, Mango C.-T. Chao, Yi-Ming Wang, Ming-Tung Chang, Min-Hsiu Tsai. 116 [doi]
- BugMD: automatic mismatch diagnosis for bug triagingBiruk Mammo, Milind Furia, Valeria Bertacco, Scott A. Mahlke, Daya Shanker Khudia. 117 [doi]
- ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencYLinuo Xue, Yuanqing Cheng, Jianlei Yang, Peiyuan Wang, Yuan Xie 0001. 118 [doi]
- Delay-optimal technology mapping for in-memory computing using ReRAM devicesDebjyoti Bhattacharjee, Anupam Chattopadhyay. 119 [doi]
- Reconfigurable in-memory computing with resistive memory crossbarYue Zha, Jing Li. 120 [doi]
- Exploiting ferroelectric FETs for low-power non-volatile logic-in-memory circuitsXunzhao Yin, Ahmedullah Aziz, Joseph Nahas, Suman Datta, Sumeet Kumar Gupta, Michael T. Niemier, Xiaobo Sharon Hu. 121 [doi]
- Approximation knob: power capping meets energy efficiencyAnil Kanduri, Mohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Pasi Liljeberg, Axel Jantsch, Nikil D. Dutt, Hannu Tenhunen. 122 [doi]
- IC thermal analyzer for versatile 3-D structures using multigrid preconditioned krylov methodsScott Ladenheim, Yi-Chung Chen, Milan Mihajlovic, Vasilis F. Pavlidis. 123 [doi]
- BoostNoC: power efficient network-on-chip architecture for near threshold computingChidhambaranathan Rajamanikkam, Rajesh J. S., Koushik Chakraborty, Sanghamitra Roy. 124 [doi]
- QScale: thermally-efficient QoS management on heterogeneous mobile platformsOnur Sahin, Ayse Kivilcim Coskun. 125 [doi]
- Synthesis of statically analyzable accelerator networks from sequential programsShaoyi Cheng, John Wawrzynek. 126 [doi]
- Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memoryShouyi Yin, Xianqing Yao, Tianyi Lu, Leibo Liu, Shaojun Wei. 127 [doi]
- Efficient synthesis of graph methods: a dynamically scheduled architectureMarco Minutoli, Vito Giovanni Castellana, Antonino Tumeo, Marco Lattuada, Fabrizio Ferrandi. 128 [doi]
- Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICsSandeep Kumar Samal, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, Sung Kyu Lim. 129 [doi]
- Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial toolsKyungwook Chang, Saurabh Sinha, Brian Cline, Raney Southerland, Michael Doherty, Greg Yeric, Sung Kyu Lim. 130 [doi]
- SAINT: handling module folding and alignment in fixed-outline floorplans for 3D ICsJai-Ming Lin, Po-Yang Chiu, Yen-Fu Chang. 131 [doi]
- From biochips to quantum circuits: computer-aided design for emerging technologiesRobert Wille, Bing Li, Ulf Schlichtmann, Rolf Drechsler. 132 [doi]
- Multilevel design understanding: from specification to logic invited paperSandip Ray, Ian G. Harris, Görschwin Fey, Mathias Soeken. 133 [doi]