Table of Contents

• CFIRSTNET: Comprehensive Features for Static IR Drop Estimation with Neural NetworkYu-Tung Liu, Yu-Hao Cheng, Shao-Yu Wu, Hung-Ming Chen. [doi]
• Neural Architecture Search for Highly Bespoke Robust Printed Neuromorphic CircuitsPriyanjana Pal, Haibin Zhao, Tara Gheshlaghi, Michael Hefenbrock, Michael Beigl, Mehdi B. Tahoori. [doi]
• Efficient Ultra-Dense 3D IC Power Delivery and Cooling Using 3D Thermal ScaffoldingDennis Rich, Tathagata Srimani, Mohamadali Malakoutian, Srabanti Chowdhury, Subhasish Mitra. [doi]
• NORNS: Three Guides for Efficient Automatic Post-Fabrication Optimization of Modern NAND Flash MemoryEarl Kim, Hyunuk Cho, Sungjun Cho, Myungsuk Kim, Jisung Park 0001, JaeYong Jeong, Eunkyoung Kim, Sunghoi Hur. [doi]
• Joint Placement Optimization for Hierarchical Analog/Mixed-Signal CircuitsXiaohan Gao, Haoyi Zhang, Bingyang Liu, Yibo Lin, Runsheng Wang, Ru Huang 0001. [doi]
• An Effective ECO Methodology for Reducing Back-side Design Rule Violations in Double-sided Signal RoutingChe-Ping Tsai, Fang-Yu Hsu, Wai-Kei Mak, Ting-Chi Wang. [doi]
• RABER: Reliability-Aware Bayesian-Optimization-based Control Layer Escape Routing for Flow-based MicrofluidicsSiyuan Liang, Rongliang Fu, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann, Tsung-Yi Ho. [doi]
• Strengthening the Foundations for IC Physical Design and ML EDA ResearchVidya A. Chhabria, Vikram Gopalakrishnan, Andrew B. Kahng, Sayak Kundu, Zhiang Wang, Bing-Yue Wu, Dooseok Yoon. [doi]
• One-for-All: An Unified Learning-based Framework for Efficient Cross-Corner Timing SignoffLinyu Zhu, Yichen Cai, Xinfei Guo. [doi]
• MARCA: Mamba Accelerator with Reconfigurable ArchitectureJinhao Li 0006, Shan Huang, Jiaming Xu, Jun Liu 0071, Li Ding 0012, Ningyi Xu, Guohao Dai. [doi]
• Overview of 2024 CAD contest at ICCADShao-Yun Fang, Yi-Yu Liu, Chung-Kuan Cheng, Tsun-Ming Tseng. [doi]
• Hardware-Aware Quantization for Accurate Memristor-Based Neural NetworksSumit Diware, Mohammad Amin Yaldagard, Rajendra Bishnoi. [doi]
• 2024 ICCAD CAD Contest Problem C: Scalable Logic Gate Sizing Using ML Techniques and GPU AccelerationBing-Yue Wu, Rongjian Liang, Geraldo Pradipta, Anthony Agnesina, Haoxing Ren, Vidya A. Chhabria. [doi]
• On the Security Vulnerabilities of MRAM-based In-Memory Computing Architectures against Model Extraction AttacksSaion K. Roy, Naresh R. Shanbhag. [doi]
• Fusion of Global Placement and Gate Sizing with Differentiable OptimizationYufan Du, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang 0001. [doi]
• Layout-level Hardware Trojan Prevention in the Context of Physical DesignXingyu Tong, Guohao Chen, Min Wei, Zhijie Cai, Peng Zou, Zhifeng Lin, Jianli Chen. [doi]
• Detecting Hardware Trojans in Manufactured Chips without Reference: A GMM-Based ApproachMahsa Tahghigh, Hassan Salmani. [doi]
• GL0AM: GPU Logic Simulation Using 0-Delay and Re-simulation Acceleration MethodYanqing Zhang 0002, Haoxing Ren, Brucek Khailany. [doi]
• Extending High-Level Synthesis with AI/ML MethodsNicolas Bohm Agostini, Giovanni Gozzi, Michele Fiorito, Claudio Barone, Serena Curzel, Ankur Limaye, Marco Minutoli, Vito Giovanni Castellana, Joseph B. Manzano, Fabrizio Ferrandi, Antonino Tumeo. [doi]
• Large Scale Delocalized Federated Learning Over a Huge Diversity of Devices in Emerging Next-Generation Edge Intelligence EnvironmentsMahdi Morafah, Hojin Chang, Bill Lin 0001. [doi]
• ALISE: Accelerating Large Language Model Serving with Speculative SchedulingYoupeng Zhao, Jun Wang. [doi]
• REMNA: Variation-Resilient and Energy-Efficient MLC FeFET Computing-in-Memory Using NAND Flash-Like Read and Adaptive ControlTaixin Li, Hongtao Zhong, Yixin Xu, Vijaykrishnan Narayanan, Kai Ni 0004, Huazhong Yang, Thomas Kämpfe, Xueqing Li. [doi]
• PACiM: A Sparsity-Centric Hybrid Compute-in-Memory Architecture via Probabilistic ApproximationWenlun Zhang, Shimpei Ando, Yung-Chin Chen, Satomi Miyagi, Shinya Takamaeda-Yamazaki, Kentaro Yoshioka. [doi]
• SEM-CLIP: Precise Few-Shot Learning for Nanoscale Defect Detection in Scanning Electron Microscope ImageQian Jin, Yuqi Jiang, Xudong Lu, Yumeng Liu, Yining Chen, Dawei Gao, Qi Sun 0002, Cheng Zhuo. [doi]
• RankTuner: When Design Tool Parameter Tuning Meets Preference Bayesian OptimizationPeng Xu, Su Zheng, Yuyang Ye 0001, Chen Bai, Siyuan Xu, Hao Geng, Tsung-Yi Ho, Bei Yu 0001. [doi]
• OSCA: End-to-end Serial Stochastic Computing Neural Acceleration with Fine-grained Scaling and Piecewise ActivationYixuan Hu, Yikang Jia, Meng Li 0004, Yuan Wang 0001, Runsheng Wang, Ru Huang 0001. [doi]
• Towards Energy-Aware Federated Learning via MARL: A Dual-Selection Approach for Model and ClientJun Xia 0003, Yi Zhang, Yiyu Shi 0001. [doi]
• Potter: A Parallel Overlap-Tolerant Router for UltraScale FPGAsXinshi Zang, Wenhao Lin, Jinwei Liu, Evangeline F. Y. Young. [doi]
• Non-volatile Memory Technologies for Edge AI ApplicationsXiaoyu Sun 0001, Win-San Khwa, Xiaochen Peng, Meng-Fan Chang, Kerem Akarvardar. [doi]
• Foveated HDR: Efficient HDR Content Generation on Edge Devices Leveraging User's Visual AttentionZiyu Ying 0001, Sandeepa Bhuyan, Yingtian Zhang, Yan Kang, Mahmut T. Kandemir, Chita R. Das. [doi]
• GNN-Based Performance Prediction of Quantum Optimization of Maximum Independent SetAtefeh Sohrabizadeh, Wan-Hsuan Lin, Daniel Bochen Tan, Madelyn Cain, Sheng-Tao Wang, Mikhail D. Lukin, Jason Cong. [doi]
• TReCiM: Lower Power and Temperature-Resilient Multibit 2FeFET-1T Compute-in-Memory DesignYifei Zhou, Thomas Kämpfe, Kai Ni 0004, Hussam Amrouch, Cheng Zhuo, Xunzhao Yin. [doi]
• Package Modeling and Analysis for Heterogeneous IntegrationChristopher Bailey, Leslie Hwang, Fnu Pallavi Praful. [doi]
• Leda: Leveraging Tiling Dataflow to Accelerate SpMM on HBM-Equipped FPGAs for GNNsEnxin Yi, Jiarui Bai, Yijie Nie, Dan Niu, Zhou Jin 0001, Weifeng Liu 0002. [doi]
• ATPlace2.5D: Analytical Thermal-Aware Chiplet Placement Framework for Large-Scale 2.5D-ICQipan Wang, Xueqing Li, Tianyu Jia, Yibo Lin, Runsheng Wang, Ru Huang 0001. [doi]
• Differentiable Edge-based OPCGuojin Chen, Haoyu Yang, Haoxing Mark Ren, Bei Yu 0001, David Z. Pan. [doi]
• A Framework for Explainable, Comprehensive, and Customizable Memory-Centric WorkloadsMohamed Abuelala, Mohamed Hassan 0002. [doi]
• EasyPart: An Effective and Comprehensive Hypergraph Partitioner for FPGA-based EmulationShengbo Tong, Haoyuan Li, Jiahao Xu, Chunyan Pei, Wenjian Yu, Shengjun Liu, Jian Shen. [doi]
• Dataflow Accelerator Architecture for Autonomous Machine ComputingShaoshan Liu, Yuhao Zhu 0001, Bo Yu 0014, Jean-Luc Gaudiot, Guangrong Gao. [doi]
• AdaPI: Facilitating DNN Model Adaptivity for Efficient Private Inference in Edge ComputingTong Zhou 0002, Jiahui Zhao, Yukui Luo, Xi Xie, Wujie Wen, Caiwen Ding, Xiaolin Xu 0001. [doi]
• Generative Methods in EDA: Innovations in Dataset Generation and EDA Tool AssistantsVidya A. Chhabria, Bing-Yue Wu, Utsav Sharma, Kishor Kunal, Austin Rovinski, Sachin S. Sapatnekar. [doi]
• A Hardware-Aware Gate Cutting Framework for Practical Quantum Circuit KnittingXiangyu Ren, Mengyu Zhang, Antonio Barbalace. [doi]
• FlexHE: A flexible Kernel Generation Framework for Homomorphic Encryption-Based Private InferenceJiangrui Yu, Wenxuan Zeng, Tianshi Xu, Renze Chen, Yun Liang 0001, Runsheng Wang, Ru Huang 0001, Meng Li 0004. [doi]
• A Co-optimization Framework with Multi-layer Constraints for ManufacturabilityGuohao Chen, Chang Liu, Xingyu Tong, Peng Zou, Jianli Chen. [doi]
• CircuitSeer: RTL Post-PnR Delay Prediction via Coupling Functional and Structural RepresentationSanjay Gandham, Joe Walston, Sourav Samanta, Lingxiang Yin, Hao Zheng 0005, Mingjie Lin, Stelios Diamantidis. [doi]
• PrivQuant: Communication-Efficient Private Inference with Quantized Network/Protocol Co-OptimizationTianshi Xu, Shuzhang Zhong, Wenxuan Zeng, Runsheng Wang, Meng Li. [doi]
• OpenSource Heterogeneous Chiplet-based Computing ArchitecturesAdrian Evans, César Fuguet, Davy Million. [doi]
• Modern Fixed-Outline Floorplanning with Rectilinear Soft ModulesYu-Yang Chen, Yi-Chen Lin, Tzu-Han Hsu, Iris Hui-Ru Jiang, Tung-Chieh Chen, Tai-Chen Chen, Hua-Yu Chang. [doi]
• CellRejuvo: Rescuing the Aging of 3D NAND Flash Cells with Dense-Sparse Cell ReprogrammingHan-Yu Liao, Yi-Shen Chen, Jen-Wei Hsieh, Hung-Pin Chen, Yuan-Hao Chang 0001. [doi]
• MCUBERT: Memory-Efficient BERT Inference on Commodity MicrocontrollersZebin Yang, Renze Chen, Taiqiang Wu, Ngai Wong, Yun Liang 0001, Runsheng Wang, Ru Huang 0001, Meng Li 0004. [doi]
• EPipe: Pipeline Inference Framework with High-quality Offline Parallelism Planning for Heterogeneous Edge DevicesYi Xiong 0003, Weihong Liu, Rui Zhang, Yulong Zu, Zongwei Zhu, Xuehai Zhou. [doi]
• Hierarchical Power Co-Optimization and Management for LLM Chiplet DesignsYanchi Dong, Xueping Liu, Xiaochen Hao, Yun Liang 0001, Ru Huang 0001, Le Ye, Tianyu Jia. [doi]
• Equivalence Checking for Flow-Based Computing using Iterative SAT SolvingSven Thijssen, Muhammad Rashedul Haq Rashed, Md Rubel Ahmed, Suraj Singireddy, Sumit Kumar Jha 0001, Rickard Ewetz. [doi]
• OpenNTT - An Automated Toolchain for Compiling High-Performance NTT Accelerators in FHEFlorian Krieger, Florian Hirner, Ahmet Can Mert, Sujoy Sinha Roy. [doi]
• GAT-Steiner: Rectilinear Steiner Minimal Tree Prediction Using GNNsBugra Onal, Eren Dogan, Muhammad Hadir Khan, Matthew R. Guthaus. [doi]
• Accurate, Yet Scalable: A SPICE-based Design and Optimization Framework for eNVM based Analog In-memory ComputingS. M. Mojahidul Ahsan, Muhammad Sakib Shahriar, Mrittika Chowdhury, Tanvir Hossain, Md Sakib Hasan, Tamzidul Hoque. [doi]
• Single Instruction Isolation for RISC-V Vector Test FailuresManfred Schlägl, Daniel Große. [doi]
• Optimizing Supply Chain Management using Permissioned BlockchainsAritri Saha, Ujjwal Guin. [doi]
• Are LLMs Any Good for High-Level Synthesis?Yuchao Liao, Tosiron Adegbija, Roman Lysecky. [doi]
• Enhancing DNN Accelerator Integrity via Selective and Permuted RecomputationJhon Ordoñez, Chengmo Yang. [doi]
• A Physical and Timing Aware Placement Optimization Framework Based on Graph Neural NetworkWenjie Ding, Zhanhua Zhang, Guoqing He, Peng Cao 0002. [doi]
• AnalogGym: An Open and Practical Testing Suite for Analog Circuit SynthesisJintao Li, Haochang Zhi, Ruiyu Lyu, Wangzhen Li, Zhaori Bi, Keren Zhu 0001, Yanhan Zeng, Weiwei Shan, Changhao Yan, Fan Yang 0001, Yun Li, Xuan Zeng 0001. [doi]
• ALISA: An Adaptive Learned Index Structure for Spatial Data on Solid-State DrivesChe-Wei Lin, Chun-Feng Wu. [doi]
• Quantum State Preparation Circuit Optimization Exploiting Don't CaresHanyu Wang, Daniel Bochen Tan, Jason Cong. [doi]
• Voxel-CIM: An Efficient Compute-in-Memory Accelerator for Voxel-based Point Cloud Neural NetworksXipeng Lin, Shanshi Huang, Hongwu Jiang. [doi]
• Bayesian-Informed Hyperdimensional Learning for Intelligent and Efficient Data ProcessingHamza Errahmouni Barkam, Tamoghno Das, Prathyush Poduval, Sungjeon Jeong, Calvin Yeung 0002, Mostafa A. Solitan, Mohsen Imani. [doi]
• ConSmax: Hardware-Friendly Alternative Softmax with Learnable ParametersShiwei Liu, Guanchen Tao, Yifei Zou, Derek Chow, Zichen Fan, Kauna Lei, Bangfei Pan, Dennis Sylvester, Gregory Kielian, Mehdi Saligane. [doi]
• HLSPilot: LLM-based High-Level SynthesisChenwei Xiong, Cheng Liu, Huawei Li, Xiaowei Li. [doi]
• EI-PIT: A Parallel-in-Time Exponential Integrator Method for Transient Linear Circuit SimulationHang Zhou, Quan Chen. [doi]
• SeGen: Automatic Topology Generator for Sequencing ElementsKyounghun Kang, Wanyeong Jung. [doi]
• FAS-Trans: Fully Exploiting FFN and Attention Sparsity for Transformer on FPGAHongji Wang, Kun Wang, Yifan Zhang, Jun Yu. [doi]
• Invited Paper: Enhancing Privacy-Preserving Computing with Optimized CKKS Encryption: A Hardware Acceleration ApproachTianyou Bao, Pengzhou He, Jiafeng Xie. [doi]
• AI-Driven Evaluation and Optimization of Bump Pitch Effects on Chiplet and Interposer Design QualitySeungmin Woo, Pruek Vanna-Iampikul, Sung Kyu Lim. [doi]
• Invited Paper: Efficient Design of FHEW/TFHE Bootstrapping Implementation with Scalable ParametersMing-Chien Ho, Yu-Te Ku, Yu Xiao, Feng-Hao Liu, Chih-Fan Hsu, Ming-Ching Chang, Shih-Hao Hung, Wei-Chao Chen. [doi]
• TP-DCIM: Transposable Digital SRAM CIM Architecture for Energy-Efficient and High Throughput Transformer AccelerationJunwoo Park, Kyeongho Lee, Jongsun Park 0001. [doi]
• Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QAYuan Pu 0001, Zhuolun He, Tairu Qiu, Haoyuan Wu, Bei Yu 0001. [doi]
• TSB: Tiny Shared Block for Efficient DNN Deployment on NVCIM AcceleratorsYifan Qin, Zheyu Yan, Zixuan Pan, Wujie Wen, Xiaobo Sharon Hu, Yiyu Shi 0001. [doi]
• RL-Fill: Timing-Aware Fill Insertion using Reinforcement LearningJinoh Cho, SeongHyeon Park, Jakang Lee, Sung Yun Lee, Jinmo Ahn, Seokhyeong Kang. [doi]
• TransLib: An Extensible Graph-Aware Library Framework for Automated Generation of Transformer Operators on FPGAYang Liu, Tianchen Wang, Yuxuan Dong, Zexu Zhang, Shun Li, Jun Yu 0010, Kun Wang 0005. [doi]
• ISLU: Indexing-Efficient Sparse LU Factorization for Circuit Simulation on GPUsDan Niu, Yiyang Tao, Zhou Jin 0001, Yichao Dong, Chao Wang, Changyin Sun. [doi]
• Fault Tolerant In-Memory Computing based on Emerging Technologies for Ultra-Low Precision Edge AI AcceleratorsAkul Malhotra, Sumeet Kumar Gupta. [doi]
• 2024 ICCAD CAD Contest Problem B: Power and Timing Optimization Using Multibit Flip-FlopSheng-Wei Yang, Jhih-Wei Hsu, Ting-Wei Lee, Tzu-Hsuan Chen, Cindy Chin-Fang Shen. [doi]
• HERMES: Homomorphic Encryption over Residual Number System for Multi-level EvaluationSAntian Wang, Kaiyuan Zhang, Keshab K. Parhi, Yingjie Lao. [doi]
• AdapMoE: Adaptive Sensitivity-based Expert Gating and Management for Efficient MoE InferenceShuzhang Zhong, Ling Liang, Yuan Wang 0001, Runsheng Wang, Ru Huang 0001, Meng Li 0004. [doi]
• SCATTER: Algorithm-Circuit Co-Sparse Photonic Accelerator with Thermal-Tolerant, Power-Efficient In-situ Light RedistributionZiang Yin, Nicholas Gangi, Meng Zhang, Jeff Zhang 0001, Z. Rena Huang, Jiaqi Gu 0002. [doi]
• Improving Timing & Power Trade-off in Post-place Optimization Using Multi-agent Reinforcement LearningJaemin Seo, Sejin Park 0001, Seokhyeong Kang. [doi]
• MatFactory: A Framework for High-Performance Matrix Factorization on FPGAsMingzhe Zhang, Xiaochen Hao, Hongbo Rong, Wenguang Chen. [doi]
• HybriDIFT: Scalable Memory-Aware Dynamic Information Flow Tracking for HardwareFlavien Solt, Kaveh Razavi. [doi]
• Edge-BiT: Software-Hardware Co-design for Optimizing Binarized Transformer Networks Inference on Edge FPGAShuai Zhou, Sisi Meng, Huinan Tian, Jun Yu, Kun Wang. [doi]
• RTLRewriter: Methodologies for Large Models aided RTL Code OptimizationXufeng Yao, Yiwen Wang, Xing Li, Yingzhao Lian, Ran Chen, Lei Chen 0002, Mingxuan Yuan, Hong Xu 0001, Bei Yu 0001. [doi]
• TAP-CAM: A Tunable Approximate Matching Engine based on Ferroelectric Content Addressable MemoryChenyu Ni, Sijie Chen, Che-Kai Liu, Liu Liu, Mohsen Imani, Thomas Kämpfe, Kai Ni 0004, Michael T. Niemier, Xiaobo Sharon Hu, Cheng Zhuo, Xunzhao Yin. [doi]
• PulseRF: Physics Augmented ML Modeling and Synthesis for High-Frequency RFIC DesignHyunsu Chae, Hao Yu, Sensen Li, David Z. Pan. [doi]
• Reinforcement Learning-Enhanced Cloud-Based Open Source Analog Circuit Generator for Standard and Cryogenic Temperatures in 130-nm and 180-nm OpenPDKsAli Hammoud, Anhang Li, Wen Tian, Ayushman Tripathi, Harsh Khandeparkar, Ryan Wans, Gregory Kielian, Boris Murmann, Dennis Sylvester, Mehdi Saligane. [doi]
• FloorSet - a VLSI Floorplanning Dataset with Design Constraints of Real-World SOCsUday Mallappa, Hesham Mostafa, Mikhail Galkin 0001, Mariano Phielipp, Somdeb Majumdar. [doi]
• Minimizing Worst-Case Data Transmission Cycles in Wavelength-Routed Optical NoC through Bandwidth AllocationLiaoyuan Cheng, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann. [doi]
• HeLEM-GR: Heterogeneous Global Routing with Linearized Exponential Multiplier MethodChunyuan Zhao, Zizheng Guo, Rui Wang, Zaiwen Wen, Yun Liang 0001, Yibo Lin. [doi]
• JigsawPlanner: Jigsaw-like Floorplanner for Eliminating Whitespace and Overlap among Complex Rectilinear ModulesXingbo Du, Ruizhe Zhong, Shixiong Kai, Zhentao Tang, Siyuan Xu, Jianye Hao, Mingxuan Yuan, Junchi Yan. [doi]
• A Built-In Integrated Rowhammer, Rowpress, and Leakage Detection Sensor for DRAMNezam Rohbani, Rouzbeh Pirayadi, Mohammad Arman Soleimani, Adrián Cristal Kestelman, Osman S. Unsal, Hamid Sarbazi-Azad. [doi]
• KirchhoffNet: A Scalable Ultra Fast Analog Neural NetworkZhengqi Gao, Fan-Keng Sun, Ron Rohrer, Duane S. Boning. [doi]
• Optimal Layout Synthesis of Multi-Row Standard Cells for Advanced Technology NodesSehyeon Chung, Hyunbae Seo, Handong Cho, Kyumyung Choi, Taewhan Kim 0001. [doi]
• AMAZE: Accelerated MiMC Hardware Architecture for Zero-Knowledge Applications on the EdgeAnees Ahmed, Nojan Sheybani, Davi Moreno, Nges Brian Njungle, Tengkai Gong, Michel A. Kinsy, Farinaz Koushanfar. [doi]
• Multi-Objective Software-Hardware Co-Optimization for HD-PIM via Noise-Aware Bayesian OptimizationChien-Yi Yang, Minxuan Zhou, Flavio Ponzina, Suraj Sathya Prakash, Raid Ayoub, Pietro Mercati, Mahesh Subedar, Tajana Rosing. [doi]
• DiffSAT: Differential MaxSAT Layer for SAT SolvingYu Zhang 0189, Hui-Ling Zhen, Mingxuan Yuan, Bei Yu 0001. [doi]
• An O(m+n)-Space Spatiotemporal Denoising Filter with Cache-Like Memories for Dynamic Vision SensorsQinghang Zhao, Jiaqi Wang, Yixi Ji, Jinjian Wu, Guangming Shi. [doi]
• Exploration of Timing and Higher-Energy Attacks on Quantum Random Access MemoryYizhuo Tan, Chuanqi Xu, Jakub Szefer. [doi]
• ChatOPU: An FPGA-based Overlay Processor for Large Language Models with Unstructured SparsityTiandong Zhao, Shaoqiang Lu, Chen Wu, Lei He. [doi]
• LAG-Sizer: A Novel Gate Sizer Based on Leak Generative Adversarial Network with Feature FusionZhanhua Zhang, Wenjie Ding, Guoqing He, Peng Cao 0002. [doi]
• MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library TuningMingju Liu, Daniel Robinson, Yingjie Li, Cunxi Yu. [doi]
• Efficient High-Fidelity Two-Dimensional Warpage Modeling for Advanced Packaging AnalysisShao-Yu Lo, MaoZe Liu, Yao-Wen Chang. [doi]
• Enforcing hard constraints in physics-informed learning for transient TSV electromigration analysisXiaoman Yang, Hai-Bao Chen, Wenjie Zhu, Yuhan Zhang, Yongkang Xue, Pengpeng Ren, Runsheng Wang, Zhigang Ji, Ru Huang 0001. [doi]
• The Power of Graph Signal Processing for Chip Placement AccelerationYiting Liu, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang. [doi]
• Tiny Deep Ensemble: Uncertainty Estimation in Edge AI Accelerators via Ensembling Normalization Layers with Shared WeightsSoyed Tuhin Ahmed, Michael Hefenbrock, Mehdi B. Tahoori. [doi]
• Fortifying the NAND Flash Supply Chain with Innovative Security PrimitivesMatchima Buddhanoy, Biswajit Ray. [doi]
• Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generationKaiyan Chang, Zhirong Chen, Yunhao Zhou, Wenlong Zhu, Kun Wang, Haobo Xu, Cangyuan Li, Mengdi Wang, Shengwen Liang, Huawei Li 0001, Yinhe Han 0001, Ying Wang 0001. [doi]
• RandOhm: Mitigating Impedance Side-channel Attacks using Randomized Circuit ConfigurationsSaleh Khalaj Monfared, Domenic Forte, Shahin Tajik. [doi]
• RareLS: Rarity-Reducing Logic Synthesis for Mitigating Hardware Trojan ThreatsChang Meng, Mingfei Yu, Hanyu Wang, Wayne P. Burleson, Giovanni De Micheli. [doi]
• On Reducing the Execution Latency of Superconducting Quantum Processors via Quantum Job SchedulingWenjie Wu, Yiquan Wang, Ge Yan 0001, Yuming Zhao, Bo Zhang, Junchi Yan. [doi]
• ARO: Autoregressive Operator Learning for Transferable and Multi-fidelity 3D-IC Thermal Analysis With Active LearningMingyue Wang, Yuanqing Cheng, Weiheng Zeng, Zhenjie Lu, Vasilis F. Pavlidis, Wei Xing. [doi]
• DISC: Exploiting Data Parallelism of Non-Stencil Computations on CGRAs via Dynamic Iteration SchedulingYue Liang, Di Mou, Dajiang Liu. [doi]
• VeriCHERI: Exhaustive Formal Security Verification of CHERI at the RTLAnna Lena Duque Antón, Johannes Müller 0006, Philipp Schmitz, Tobias Jauch, Alex Wezel, Lucas Deutschmann, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz. [doi]
• Thinking and Moving: An Efficient Computing Approach for Integrated Task and Motion Planning in Cooperative Embodied AI SystemsZishen Wan, Yuhang Du, Mohamed Ibrahim, Yang (Katie) Zhao, Tushar Krishna, Arijit Raychowdhury. [doi]
• Generative AI Agents in Autonomous Machines: A Safety PerspectiveJason Jabbour, Vijay Janapa Reddi. [doi]
• DeepGate3: Towards Scalable Circuit Representation LearningZhengyuan Shi, Ziyang Zheng, Sadaf Khan, Jianyuan Zhong, Min Li 0019, Qiang Xu 0001. [doi]
• TSO-Flow: A Topology Synthesis and Optimization Workflow for Operational Amplifiers with Invertible Graph Generative ModelJinglin Han, Yuhao Leng, Xiuli Zhang, Peng Wang. [doi]
• DoS-FPGA: Denial of Service on Cloud FPGAs via Coordinated Power HammeringHassan Nassar, Philipp Machauer, Lars Bauer, Dennis Gnad, Mehdi Baradaran Tahoori, Jörg Henkel. [doi]
• Enabling Robust Inverse Lithography with Rigorous Multi-Objective OptimizationYang Luo, Xiaoxiao Liang, Yuzhe Ma. [doi]
• Automatic Verification and Identification of Partial Retention Register Sets for Low-Power DesignsYu-An Shih, Sharad Malik. [doi]
• ZnH2: Augmenting ZNS-based Storage System with Host-Managed Heterogeneous ZonesYingjia Wang, Lok Yin Chow, Xirui Nie, Yuhong Liang, Ming-Chang Yang. [doi]
• SMT-based Layout Synthesis for Silicon-based Quantum Computing with Crossbar ArchitectureSheng-Tan Huang, Ying-Jie Jiang, Shao-Yun Fang, Chung-Kuan Cheng. [doi]
• FabGPT: An Efficient Large Multimodal Model for Complex Wafer Defect Knowledge QueriesYuqi Jiang, Xudong Lu, Qian Jin, Qi Sun 0002, HanMing Wu, Cheng Zhuo. [doi]
• FlexInt: A New Number Format for Robust Sub-8-Bit Neural Network InferenceMinuk Hong, Hyeonuk Sim, Sugil Lee, Jongeun Lee. [doi]
• Spiking Transformer Hardware Accelerators in 3D IntegrationBoxun Xu, Junyoung Hwang, Pruek Vanna-Iampikul, Sung Kyu Lim, Peng Li 0001. [doi]
• Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate PlacementHongyang Pan, Cunqing Lan, Yiting Liu, Zhiang Wang, Li Shang, Xuan Zeng 0001, Fan Yang 0001, Keren Zhu 0001. [doi]
• A Neural-Ordinary-Differential-Equations Based Generic Approach for Process Modeling in DTCO: A Case Study in Chemical-Mechanical Planarization and Copper PlatingYue Qian, Lan Chen. [doi]
• A comparison on constrain encoding methods for quantum approximate optimization algorithmYiwen Liu, Qingyue Jiao, Yiyu Shi, Ke Wan, Shangjie Guo. [doi]
• Parameter Setting Heuristics Make the Quantum Approximate Optimization Algorithm Suitable for the Early Fault-Tolerant EraZichang He, Ruslan Shaydulin, Dylan Herman, Changhao Li, Rudy Raymond, Shree Hari Sureshbabu, Marco Pistoia. [doi]
• AESHA: Accelerating Eigen-decomposition-based Sparse Transformer with Hybrid RRAM-SRAM ArchitectureXuliang Yu, Tianwei Ni, Xinsong Sheng, Yun Pan, Lei He, Liang Zhao. [doi]
• LiTformer: Efficient Modeling and Analysis of High-Speed Link Transmitters Using Non-Autoregressive TransformerSongyu Sun, Xiao Dong, Yanliang Sha, Quan Chen 0007, Cheng Zhuo. [doi]
• Towards Floating Point-Based Attention-Free LLM: Hybrid PIM with Non-Uniform Data Format and Reduced MultiplicationsLidong Guo, Zhenhua Zhu, Tengxuan Liu, Xuefei Ning, Shiyao Li, Guohao Dai, Huazhong Yang, Wangyang Fu, Yu Wang 0002. [doi]
• Co-designing 2.5D Silicon Photonic Accelerators for Distributed Transformer at the EdgeDharanidhar Dang, Priyabrata Dash, Luqi Zheng, Haitong Li. [doi]
• Hyena: Optimizing Homomorphically Encrypted Convolution for Private CNN InferenceHyeri Roh, Woo-seok Choi. [doi]
• Robust Implementation of Retrieval-Augmented Generation on Edge-based Computing-in-Memory ArchitecturesRuiyang Qin, Zheyu Yan, Dewen Zeng, Zhenge Jia, Dancheng Liu, Jianbo Liu, Ahmed Abbasi, Zhi Zheng, Ningyuan Cao, Kai Ni 0004, Jinjun Xiong, Yiyu Shi 0001. [doi]
• Multi-Tier 3D SRAM Module Design: Targeting Bit-Line and Word-Line FoldingAditya Sridharan Iyer, Daehyun Kim 0002, Saibal Mukhopadhyay, Sung Kyu Lim. [doi]
• ReSCIM: Variation-Resilient High Weight-Loading Bandwidth In-Memory Computation Based on Fine-Grained Hybrid Integration of Multi-Level ReRAM and SRAM CellsXiaomeng Wang, Jingyu He, Kunming Shao, Jiakun Zheng, Fengshi Tian, Kwang-Ting (Tim) Cheng, Chi-Ying Tsui. [doi]
• Towards Uncertainty-Quantifiable Biomedical Intelligence: Mixed-signal Compute-in-Entropy for Bayesian Neural NetworksLikai Pei, Yifan Qin, Zephan M. Enciso, Boyang Cheng, Jianbo Liu, Steven Davis, Zhenge Jia, Michael T. Niemier, Yiyu Shi 0001, Xiaobo Sharon Hu, Ningyuan Cao. [doi]
• Balor: HLS Source Code Evaluator Based on Custom Graphs and Hierarchical GNNsEmmet Murphy, Lana Josipovic. [doi]
• Invited Paper: LLM4HWDesign Contest: Constructing a Comprehensive Dataset for LLM-Assisted Hardware Code Generation with Community EffortsZhongzhi Yu, Chaojian Li, Yongan Zhang, Mingjie Liu, Nathaniel Ross Pinckney, Wenfei Zhou, Haoyu Yang, Rongjian Liang, Haoxing Ren, Yingyan Celine Lin. [doi]
• EDALearn: A Comprehensive RTL-to-Signoff EDA Benchmark for Democratized and Reproducible ML for EDA ResearchJingyu Pan, Chen-Chia Chang, Zhiyao Xie, Yiran Chen 0001, Hai Helen Li. [doi]
• SysMix: Mixed-Size Placement for Systolic-Array-Based Hierarchical DesignsDonghao Fang, Hailiang Hu, Wuxi Li, Bo Yuan 0001, Jiang Hu. [doi]
• Co-Designing NVM-based Systems for Machine Learning and In-memory Search ApplicationsJörg Henkel, Lokesh Siddhu, Hassan Nassar, Lars Bauer, Jian-Jia Chen, Christian Hakert, Tristan Taylan Seidl, Kuan-Hsun Chen, Xiaobo Sharon Hu, Mengyuan Li, Chia-Lin Yang, Ming-Liang Wei. [doi]
• OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-ReflectionFan Cui, Chenyang Yin, Kexing Zhou, Youwei Xiao, Guangyu Sun 0003, Qiang Xu 0001, Qipeng Guo, Yun Liang 0001, Xingcheng Zhang, Demin Song, Dahua Lin. [doi]
• Imaging, Computing, and Human Perception: Three Agents to Usher in the Autonomous Machine Computing EraYuhao Zhu 0001. [doi]
• ReCon: Reconfiguring Analog Rydberg Atom Quantum Computers for Quantum Generative Adversarial NetworksNicholas S. DiBrita, Daniel Leeds, Yuqian Huo, Jason Ludmir, Tirthak Patel. [doi]
• Mixed-precision Neural Networks on RISC-V Cores: ISA extensions for Multi-Pumped Soft SIMD OperationsGiorgos Armeniakos, Alexis Maras, Sotirios Xydis, Dimitrios Soudris. [doi]
• Automatic Generation of Cycle-Accurate Timing Models from RTL for Hardware AcceleratorsYu Zeng, Aarti Gupta, Sharad Malik. [doi]
• R-HLS: An IR for Dynamic High-Level Synthesis and Memory Disambiguation based on Regions and State EdgesDavid Metz 0001, Nico Reissmann, Magnus Själander. [doi]
• APINT: A Full-Stack Framework for Acceleration of Privacy-Preserving Inference of Transformers based on Garbled CircuitsHyunjun Cho, JaeHo Jeon, Jaehoon Heo, Joo-Young Kim 0001. [doi]
• Hybrid Modeling and Weighting for Timing-driven Placement with Efficient CalibrationBangqi Fu, Lixin Liu, Martin D. F. Wong, Evangeline F. Y. Young. [doi]
• Word-Level Augmentation of Formal Proof by Learning from Simulation TracesZhiyuan Yan 0003, Hongce Zhang. [doi]
• FLOP: A Flexible Memory-Optimized Processor for Parallel Graph Mining on FPGAGuoyu Li, Runzhou Zhang, Jun Yu, Kun Wang. [doi]
• AceRoute: Adaptive Compute-Efficient FPGA Routing with Pluggable Intra-Connection Bidirectional ExplorationXinming Wei, Ziyun Zhang, Sunan Zou, Kaiwen Sun, Jiahao Zhang, Jiaxi Zhang 0001, Ping Fan, Guojie Luo. [doi]
• Detecting Fraudulent Services on Quantum Cloud Platforms via Dynamic FingerprintingJindi Wu, Tianjie Hu, Qun Li 0001. [doi]
• Placement Tomography-Based Routing Blockage Generation for DRV Hotspot MitigationAndrew B. Kahng, Sayak Kundu, Dooseok Yoon. [doi]
• InstantGR: Scalable GPU Parallelization for Global RoutingShiju Lin, Liang Xiao, Jinwei Liu, Evangeline F. Y. Young. [doi]
• Efficient Task Transfer for HLS DSEZijian Ding, Atefeh Sohrabizadeh, Weikai Li 0002, Zongyue Qin, Yizhou Sun, Jason Cong. [doi]
• Barber: Balancing Thermal Relaxation Deviations of NISQ Programs by Exploiting Bit-Inverted CircuitsEnhyeok Jang, Seungwoo Choi, Youngmin Kim, Jeewoo Seo, Won Woo Ro. [doi]
• HeteroExcept: A CPU-GPU Heterogeneous Algorithm to Accelerate Exception-aware Static Timing AnalysisZizheng Guo, Zuodong Zhang, Wuxi Li, Tsung-Wei Huang, Xizhe Shi, Yufan Du, Yibo Lin, Runsheng Wang, Ru Huang 0001. [doi]
• AyE-Edge: Automated Deployment Space Search Empowering Accuracy yet Efficient Real-Time Object Detection on the EdgeChao Wu 0006, Yifan Gong 0004, Liangkai Liu, Mengquan Li, Yushu Wu, Xuan Shen, Zhimin Li, Geng Yuan, Weisong Shi, Yanzhi Wang. [doi]
• ProPD: Dynamic Token Tree Pruning and Generation for LLM Parallel DecodingShuzhang Zhong, Zebin Yang, Ruihao Gong, Runsheng Wang, Ru Huang 0001, Meng Li 0004. [doi]
• Systematic Use of Random Self-Reducibility in Cryptographic Code against Physical AttacksFerhat Erata, Tinghung Chiu, Anthony Etim, Srilalith Nampally, Tejas Raju, Rajashree Ramu, Ruzica Piskac, Timos Antonopoulos, Wenjie Xiong 0001, Jakub Szefer. [doi]
• Co-Designing Binarized Transformer and Hardware Accelerator for Efficient End-to-End Edge DeploymentYuhao Ji, Chao Fang, Shaobo Ma, Haikuo Shao, Zhongfeng Wang. [doi]
• BasisN: Reprogramming-Free RRAM-Based In-Memory-Computing by Basis Combination for Deep Neural NetworksAmro Eldebiky, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ing-Chao Lin, Ulf Schlichtmann, Bing Li 0005. [doi]
• An Access Pattern-aware Hybrid Learning-based and Conventional Mapping for Solid-State DrivesQian Wei, Xiaosu Guo, Jie Wang, Zhaoyan Shen, Dongxiao Yu, Zhiping Jia, Bingzhe Li. [doi]
• HDXpose: Harnessing Hyperdimensional Computing's Explainability for Adversarial AttacksFatemeh Asgarinejad, Flavio Ponzina, Onat Güngör, Tajana Rosing, Baris Aksanli. [doi]
• 2024 ICCAD CAD Contest Problem A: Reinforcement Logic Optimization for a General Cost FunctionChung-Han Chou, Chih-Jen Hsu, Chi-An Wu, Kuan-Hua Tu, Kwangsoo Han, Zhou Li. [doi]
• MORPH: More Robust ASIC Placement for Hybrid Region Constraint ManagementJing Mai, Zuodong Zhang, Yibo Lin, Runsheng Wang, Ru Huang 0001. [doi]
• CoCoA: Algorithm-Hardware Co-Design for Large-Scale GNN Training using Compressed GraphYunki Han, Jaekang Shin, GunHee Park, Lee-Sup Kim. [doi]
• MapFormer: Attention-based multi-DNN manager for throughout & power co-optimization on embedded devicesAndreas Karatzas, Iraklis Anagnostopoulos. [doi]
• µLAM: A LLM-Powered Assistant for Real-Time Micro-architectural Attack Detection and MitigationUpasana Mandal, Shubhi Shukla 0001, Ayushi Rastogi, Sarani Bhattacharya, Debdeep Mukhopadhyay. [doi]
• ADO-LLM: Analog Design Bayesian Optimization with In-Context Learning of Large Language ModelsYuxuan Yin, Yu Wang 0167, Boxun Xu, Peng Li 0001. [doi]
• Compiler Optimizations for QAOAYuchen Zhu, Yidong Zhou, Jinglei Cheng, Yuwei Jin, Boxi Li, Siyuan Niu, Zhiding Liang. [doi]
• RapidStream IR: Infrastructure for FPGA High-Level Physical SynthesisJason Lau, Yuanlong Xiao, Yutong Xie 0011, Yuze Chi, Linghao Song, Shaojie Xiang, Michael Lo, Zhiru Zhang, Jason Cong, Licheng Guo. [doi]
• Evolutionary Approximation of Ternary Neurons for On-sensor Printed Neural NetworksVojtech Mrazek, Argyris Kokkinis, Panagiotis Papanikolaou, Zdenek Vasícek, Kostas Siozios, Georgios Tzimpragos, Mehdi B. Tahoori, Georgios Zervakis 0001. [doi]
• An Effective Analytical Placement Approach to Handle Fence Region ConstraintJai-Ming Lin, Wei-Yuan Lin, Yung-Chen Chen, Pin-Yu Chen, Chen-Fa Tsai, De-Shiun Fu, Che-Li Lin. [doi]
• Neuromorphic Computing for Graph AnalyticsAnup Das. [doi]
• An FPGA-based Key-Switching Accelerator with Ultra-High Throughput for FHEZhaojun Lu, Peng Xu 0003, Yijie Wang, Yifan Yang, Qidong Chen, Weizong Yu, Gang Qu 0001. [doi]
• Multi-phase Coupled CMOS Ring Oscillator based Potts MachineYilmaz Ege Gonul, Baris Taskin. [doi]
• MEIC: Re-thinking RTL Debug Automation using LLMsKe Xu, Jialin Sun, Yuchen Hu, Xinwei Fang, Weiwei Shan, Xi Wang, Zhe Jiang. [doi]
• Fast and Efficient 2-bit LLM Inference on GPU: 2/4/16-bit in a Weight Matrix with Asynchronous DequantizationJinhao Li 0006, Jiaming Xu, Shiyao Li, Shan Huang, Jun Liu 0071, Yaoxiu Lian, Guohao Dai. [doi]
• CSP: Comprehensively-Sparsified Preconditioner for Efficient Nonlinear Circuit SimulationYuxuan Zhao, Xiaoyu Yang, Yinuo Bai, Lijie Zeng, Dan Niu, Weifeng Liu 0002, Zhou Jin 0001. [doi]
• MAXCell: PPA-Directed Multi-Height Cell Layout Routing Optimization using Anytime MaXSAT with Constraint LearningJiun-Cheng Tsai, Wei-Min Hsu, Yun-Ting Hsieh, Yu-Ju Li, Wei Huang, C. N. Ho, Hsuan-Ming Huang, Jen-Hang Yang, Heng-Liang Huang, Aaron C.-W. Liang, Charles H.-P. Wen. [doi]
• AGC: A Unified Architecture for Accelerating K-Nearest Neighbor Graph Construction in Vector SearchLei Dai, Ziming Yuan, Wen Li, Shengwen Liang, Kaiwei Zou, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li. [doi]
• Sustainable High-Performance Instruction Selection for Superscalar ProcessorsSaeideh Sheikhpour, David Metz 0001, Erling Jellum, Magnus Själander, Lieven Eeckhout. [doi]
• BPINN-EM: Fast Stochastic Analysis of Electromigration Damage using Bayesian Physics-Informed Neural NetworksSubed Lamichhane, Mohammadamir Kavousi, Sheldon X.-D. Tan. [doi]
• RISCSparse: Point Cloud Inference Engine on RISC-V ProcessorShangran Lin, Xinrui Zhu, Baohui Xie, Tinghuan Chen, Cheng Zhuo, Qi Sun 0002, Bei Yu 0001. [doi]
• Revisiting sensitivity-based analog sizing with derivative-aware Bayesian optimization and error-suppressed adjoint analysisRuiyu Lyu, Aidong Zhao, Yuan Meng, Keren Zhu 0001, Zhaori Bi, Changhao Yan, Fan Yang 0001, Dian Zhou, Xuan Zeng 0001. [doi]
• RACI: A Resource-Aware Cooperative Inference Framework on Heterogeneous Edge DevicesZhenyu Wang, Ao Ren, Duo Liu, Haining Fang, Jiaxing Shi, Yujuan Tan, Xianzhang Chen. [doi]
• LSMR: Synergy Randomness in Liquid State Machine and RRAM-based Analog-digital AcceleratorNing Lin, Songqi Wang, Xinyuan Zhang, Shaocong Wang, Yangu He, Woyu Zhang, Bo Wang, Jiankun Li, Mingzi Li, Binbin Cui, Yi Li, Jia Chen, Chunwei Xia, Wei Xuan, Xiaoming Chen, Dashan Shang, Zhongrui Wang. [doi]
• Explainable and Layout-Aware Timing PredictionZhengyang Lyu, Xiaqing Li, Zidong Du, Qi Guo 0001. [doi]
• A Hypergraph Partitioner Utilizing a Novel Graph Generative ModelMagi Chen, Ting-Chi Wang. [doi]
• Heterogeneous Manycore In-Memory Computing ArchitecturesChukwufumnanya Ogbogu, Gaurav Narang, Biresh Kumar Joardar, Janardhan Rao Doppa, Partha Pratim Pande. [doi]
• Analyzing the Impact of FinFET Self-Heating on the Performance of RF Power AmplifiersNibedita Karmokar, Sai-Wang Tam, Thanh Viet Dinh, Vidya A. Chhabria, Ramesh Harjani, Sachin S. Sapatnekar. [doi]
• FSMM: An Efficient Matrix Multiplication Accelerator Supporting Flexible SparsityYuxuan Qiao, Fan Yang, YeCheng Zhang, Xiankui Xiong, Xiao Yao, Haidong Yao. [doi]
• A Sparsity-Aware Autonomous Path Planning Accelerator with Algorithm-Architecture Co-DesignYanjun Zhang, Xiaoyu Niu, Yifan Zhang, Hongzheng Tian, Bo Yu 0014, Shaoshan Liu, Sitao Huang. [doi]
• Shedding Light on LLMs: Harnessing Photonic Neural Networks for Accelerating LLMsMahdi Nikdast, Salma Afifi, Sudeep Pasricha. [doi]
• UFO-MAC: A Unified Framework for Optimization of High-Performance Multipliers and Multiply-AccumulatorsDongsheng Zuo, Jiadong Zhu, Chenglin Li, Yuzhe Ma. [doi]
• SNNGX: Securing Spiking Neural Networks with Genetic XOR Encryption on RRAM-based Neuromorphic AcceleratorKwunhang Wong, Songqi Wang, Wei Huang, Xinyuan Zhang, Yangu He, Karl Ming Him Lai, Yuzhong Jiao, Ning Lin, Xiaojuan Qi 0001, Xiaoming Chen, Zhongrui Wang. [doi]
• HG-PIPE: Vision Transformer Acceleration with Hybrid-Grained PipelineQingyu Guo, Jiayong Wan, Songqiang Xu, Meng Li, Yuan Wang. [doi]
• OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL GenerationShang Liu, Yao Lu, Wenji Fang, Mengming Li, Zhiyao Xie. [doi]
• NAND-Tree: A 3D NAND Flash Based Processing In Memory Accelerator for Tree-Based Models on Large-Scale Tabular DataHongtao Zhong, Taixin Li, Yiming Chen, Wenjun Tang, Juejian Wu, Huazhong Yang, Xueqing Li. [doi]
• LACO: A Latency-Constraint Offline Neural Network Scheduler towards Reliable Self-Driving PerceptionKaisheng Ma, Zhanhong Tan, Zijian Zhu, Mengdi Wu. [doi]
• LaserEscape: Detecting and Mitigating Optical Probing AttacksSaleh Khalaj Monfared, Kyle Mitard, Andrew Cannon, Domenic Forte, Shahin Tajik. [doi]
• OFT: An accelerator with eager gradient prediction for attention trainingMiao Wang, Shengbing Zhang, Sijia Wang, Zhao Yang, Meng Zhang. [doi]
• An Agile Framework for Efficient LLM Accelerator Development and Model InferenceLvcheng Chen, Ying Wu, Chenyi Wen, Shizhang Wang, Li Zhang 0021, Bei Yu 0001, Qi Sun 0002, Cheng Zhuo. [doi]
• LLM-AID: Leveraging Large Language Models for Rapid Domain-Specific Accelerator DevelopmentFarshad Firouzi, Sri Sai Rakesh Nakkilla, Chenghao Fu, Sanmitra Banerjee, Jonti Talukdar, Krishnendu Chakrabarty. [doi]
• Beyond the Yield Barrier: Variational Importance Sampling Yield AnalysisYanfang Liu, Lei He 0001, Wei W. Xing. [doi]
• Pseudo Adjoint Optimization: Harnessing the Solution Curve for SPICE AccelerationJiatai Sun, Xiaru Zha, Chao Wang, Xiao Wu, Dan Niu, Wei W. Xing, Zhou Jin 0001. [doi]
• TopoOrderPart: a Multi-level Scheduling-Driven Partitioning Framework for Processor-Based EmulationShunyang Bi, Jing Tang, Hailong You, Haonan Wu, Cong Li, Richard Sun. [doi]
• Peak Power and Dynamic IR-drop Assessment via Waveform AugmentingYihan Wen, Juan Li, Bei Yu, Xiaoyi Wang. [doi]
• FaStTherm: Fast and Stable Full-Chip Transient Thermal Predictor Considering Nonlinear EffectsTianxiang Zhu, Qipan Wang, Yibo Lin, Runsheng Wang, Ru Huang 0001. [doi]
• LEAP: Learning guided Quality Cut selection for faster Technology MappingChandrabhusan Reddy Chigarapally, Harshwardhan Nitin Bhakkad, Animesh Basak Chowdhury, Chandan Karfa, Sukanta Bhattacharjee. [doi]
• PolarGate: Breaking the Functionality Representation Bottleneck of And-Inverter Graph Neural NetworkJiawei Liu 0006, Jianwang Zhai, Mingyu Zhao, Zhe Lin, Bei Yu, Chuan Shi 0001. [doi]
• A materials- and devices-centric approach to neuromorphic computingShaloo Rakheja. [doi]
• GACER: Granularity-Aware ConcurrEncy Regulation for Multi-Tenant Deep LearningYongbo Yu, Fuxun Yu, Zhi Tian, Xiang Chen. [doi]
• Accelerating Quantum Circuit Simulation with Symbolic Execution and Loop SummarizationTian-Fu Chen, Yu-Fang Chen 0001, Jie-Hong Roland Jiang, Sára Jobranová, Ondrej Lengál. [doi]
• Sustainable Hardware SpecializationPranav Dangi, Thilini Kaushalya Bandara, Saeideh Sheikhpour, Tulika Mitra, Lieven Eeckhout. [doi]
• eXpect: On the Security Implications of Violations in AXI ImplementationsMelisande Zonta-Roudes, Andres Meza 0001, Nora Hinderling, Lucas Deutschmann, Francesco Restuccia 0002, Ryan Kastner, Shweta Shinde. [doi]
• ShiftCAM: A Time-Domain Content Addressable Memory Utilizing Shifted Hamming Distance for Robust Genome AnalysisPeiyi He, Ruibin Mao, Keyi Shan, Yunwei Tong, Zhicheng Xu, Muyuan Peng, Ruibang Luo, Can Li. [doi]
• Is Vanilla Bayesian Optimization Enough for High-Dimensional Architecture Design Optimization?Yuanhang Gao, Donger Luo, Chen Bai, Bei Yu 0001, Hao Geng, Qi Sun 0002, Cheng Zhuo. [doi]
• A Processing-using-Memory Architecture for Commodity DRAM Devices with Enhanced Compatibility and ReliabilityHoon Shin, Rihae Park, Jae W. Lee. [doi]
• DDP-Fsim: Efficient and Scalable Fault Simulation for Deterministic Patterns with Two-Dimensional ParallelismFeng Gu, Mingjun Wang, Jianan Mu, Zizhen Liu, Jiaping Tang, Hui Wang, Yonghao Wang, Jing Ye 0001, Huawei Li 0001, Xiaowei Li 0001. [doi]
• ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree SearchJitendra Bhandari, Animesh Basak Chowdhury, Ozgur Sinanoglu, Siddharth Garg, Ramesh Karri, Johann Knechtel. [doi]
• Partial Differential Equation Acceleration by Exploiting Value SimilarityZehua Li, Kaisheng Ma. [doi]
• Accelerating Fault Injection for Validating Processor RTL ImplementationsYi Yuan, Derek Chiou. [doi]
• Error Correction and Detection for Analog AI Computing in Edge SystemsAnxiao Jiang. [doi]
• Residual-INR: Communication Efficient On-Device Learning Using Implicit Neural RepresentationHanqiu Chen, Xuebin Yao, Pradeep Subedi, Cong Hao. [doi]
• CAMSHAP: Accelerating Machine Learning Model Explainability with Analog CAMJohn Moon, Giacomo Pedretti, Pedro Bruel, Sergey Serebryakov, Omar Eldash, Luca Buonanno, Catherine E. Graves, Paolo Faraboschi, Jim Ignowski. [doi]
• OCTS: An Optical Clock Tree Synthesis Methodology for 2.5D SystemsAristotelis Tsekouras, Georgios Kyriazidis, Gage Hills, Vasilis Pavlidis. [doi]
• Hybrid Power Failure Recovery for Intermittent ComputingGan Fang, Jongouk Choi, Changhee Jung. 1-9 [doi]