Table of Contents

• DIVE: Dynamic Information-Guided Variable Expansion for Deeper Analog Circuit OptimizationZhuohua Liu, Weilun Xie, Yuxuan Zhang, Chen Wang, Yuanqi Hu, Wei W. Xing. 1-9 [doi]
• PPAAS: PVT and Pareto Aware Analog Sizing via Goal-conditioned Reinforcement LearningSeunggeun Kim, Ziyi Wang 0010, Sungyoung Lee 0004, Youngmin Oh, Hanqing Zhu, Doyun Kim, David Z. Pan. 1-9 [doi]
• Tiny-Align: Bridging Automatic Speech Recognition and Large Language Model on EdgeRuiyang Qin, Dancheng Liu, Gelei Xu, Amir Nassereldine, Zheyu Yan, Chenhui Xu, Yuting Hu, X. Sharon Hu, Jinjun Xiong, Yiyu Shi 0001. 1-9 [doi]
• Capacitance Extraction via Machine Learning with Application to Interconnect Geometry ExplorationCheng-Yu Tsai, Suwan Kim, Sung Kyu Lim. 1-9 [doi]
• Mamba-X: An End-to-End Vision Mamba Accelerator for Edge Computing DevicesDongho Yoon, Gungyu Lee, Jaewon Chang, Yunjae Lee, Dongjae Lee, Minsoo Rhu. 1-9 [doi]
• BAGNet: A Boundary-Aware Graph Neural Network for SRAM Yield Analysis in Post-LayoutSimulationHaoyang Sang, Changhao Yan, Zhaori Bi, Keren Zhu 0001, Xuan Zeng 0001. 1-9 [doi]
• Discriminate Weight Approximation for Efficient DSP Packing in LLM AcceleratorsJun Li, Yangyijian Liu, Chang-Wei Shi, Mingyang Li, Wu-Jun Li. 1-9 [doi]
• CTDM: Resource-Efficient FPGA-Accelerated Simulation of Large-Scale NPU DesignsHyunje Jo, Han-Sok Suh, Hyun-Seok Heo, Jinseok Kim, Hyunsung Kim, Boeui Hong, Jungju Oh, Sunghyun Park 0006, Jinwook Oh, Sunghwan Jo, Kangwook Lee 0008, Jae-sun Seo. 1-9 [doi]
• Neuromorphic Architectures for Scientific Computing: a Structural Characterization Case StudyM. Lakshmi Varshika, Jonathan Hollenbach, Nicolas Bohm Agostini, Ankur Limaye, Marco Minutoli, Vito Giovanni Castellana, Joseph B. Manzano, Anup Das 0001, Mitra Taheri, Antonino Tumeo. 1-9 [doi]
• Constraints-aware Adaptive Routing with Hybrid Waveguides for Photonic Integrated CircuitsYuchao Wu, Xiaofei Yu, Xianyi Feng, Yeyu Tong, Yuzhe Ma. 1-8 [doi]
• Non-Negative AdderNet: Algorithm-Hardware Co-design for Lightweight Defense of Adversarial Bit-Flip AttacksYunxiang Zhang, Sabbir Ahmed, Abeer Matar A Almalky, Adnan Siraj Rakin, Wenfeng Zhao. 1-8 [doi]
• dyGRASS: Dynamic Spectral Graph Sparsification via Localized Random Walks on GPUsYihang Yuan, Ali Aghdaei, Zhuo Feng. 1-9 [doi]
• (Invited Paper) Overview of 2025 CAD Contest at ICCADChung-Kuan Cheng, Shao-Yun Fang, Yi-Yu Liu, Tsun-Ming Tseng. 1-4 [doi]
• LEAP: LLM Inference on Scalable PIM-NoC Architecture with Balanced Dataflow and Fine-Grained ParallelismYimin Wang 0001, Yue Jiet Chong, Xuanyao Fong. 1-9 [doi]
• FlexTEE: Dynamically Enhancing Metadata Locality Through Affine Address Transformation for Heterogeneous & Secure AI PlatformsRakin Muhammad Shadab, Sanjay Gandham, Mingjie Lin. 1-9 [doi]
• J2Place: A Multiphase Clocking-Oriented Length-Matching Placement for Rapid Single-Flux-Quantum CircuitsRongliang Fu, Minglei Zhou, Huilong Jiang, Junying Huang, Xiaochun Ye, Tsung-Yi Ho. 1-8 [doi]
• 2EAL: Hybrid-Bonding Architecture with Hybrid Sparse Attention for Efficient Long-Context LLM InferenceZizhuo Fu, Xiaotian Guo, Wenxuan Zeng, Shuzhang Zhong, Yadong Zhang, Peiyu Chen, Runsheng Wang, Le Ye, Meng Li. 1-9 [doi]
• M3: Mamba-assisted Multi-Circuit Optimization via Model-based RL with Effective SchedulingYoungmin Oh, Jinje Park, Taejin Paik, Seunggeun Kim, Suwan Kim, Yoon Hyeok Lee, David Z. Pan. 1-8 [doi]
• Enabling Decoder-only Language Model Inference on a CNN AcceleratorSeongwoo Choi, Hyunsu Moh, Changjae Yi, Joon Choi, Soonhoi Ha. 1-9 [doi]
• 3D CoSim: Coupled Operator Learning-Based Co-Simulator for Transferable 3D-IC AnalysisYouran Wu, Shunjie Chang, Jianli Chen, Jun Yu, Kun Wang. 1-9 [doi]
• G-Contour: GPU Accelerated Contour Tracing For Large-Scale LayoutsShuo Yin, Jiahao Xu, Jiaxi Jiang, Mingjun Li, Yuzhe Ma, Tsung-Yi Ho, Bei Yu 0001. 1-9 [doi]
• (Invited Paper) AnaFlow: Agentic LLM-based Workflow for Reasoning-Driven Explainable and Sample-Efficient Analog Circuit SizingMohsen Ahmadzadeh, Kaichang Chen, Georges G. E. Gielen. 1-7 [doi]
• Apollo: Automated Routing-Informed Placement for Large-Scale Photonic Integrated CircuitsHongjian Zhou, Haoyu Yang, Nicholas Gangi, Zhaoran Rena Huang, Haoxing Ren, Jiaqi Gu 0002. 1-9 [doi]
• Addressing Thermal Throttling in HBMGaurav Kothari, Kanad Ghose. 1-9 [doi]
• Tenpura: A General Transient Fault Evaluation and Scope Narrowing Platform for Ultra-fast Reliability AnalysisQuan Cheng, Huizi Zhang, Chien-Hsing Liang, Mingtao Zhang, Jing-Jia Liou, Jinjun Xiong, Longyang Lin, Masanori Hashimoto. 1-9 [doi]
• COPA: A Congestion-Oriented Pin Assignment Framework for Intra-Block Physical Design OptimizationShu-Yi Tsai, Yu-Guang Chen, Kun-Min Chen, Sheng-Bing Ke, Chung-Hui Hsieh, Chih-Wei Lin, Mango Chia-Tso Chao. 1-9 [doi]
• H3D-LLM: Heterogeneous 3D Chiplet Design for LLM Inference with Dynamic Task Scheduling and Memory-Aware OrchestrationHui Kou, Chenjie Xia, Jialin Yang, Liyi Li 0004, Hao Cai 0001, Xin Si, Bo Liu 0019. 1-9 [doi]
• TETRIS: On-Device Trainable Energy-Efficient FPGA Accelerator for Trustworthy and Real-Time Instance SegmentationSeungIl Lee, Juntae Park, Kwanghyun Koo, Gilha Lee, Sangbeom Jeong, JunOh Park, Hyun Kim 0001. 1-9 [doi]
• Enhancing Timing Closure via Spatially Embedded Graph Transformer with Low Power/Area OverheadJoonyoung Seo, Jonghyeon Nam, Howoo Jang, Yoonseok Jung, Seokhyeong Kang. 1-9 [doi]
• Simulation Framework and Optimization of Superconducting Transmon-Tunable Coupler-Transmon System for Qudit GatesFerris Prima Nugraha, Yuhan Huang, Jiacheng Liu, Qiming Shao. 1-8 [doi]
• CNOT Oriented Synthesis for Small-Scale Boolean Functions Using Spatial Structures of ParallelotopesQiang Zheng, Yongzhen Xu, Jiaxi Zhang 0001, Zhaofeng Su 0001, Shenggen Zheng. 1-9 [doi]
• LEAF: Lightweight and Efficient Hardware Accelerator for Signature Verification of FALCONSamuel Coulon, Jinjun Xiong, Jiafeng Xie. 1-9 [doi]
• GradMap: A Gradient-Descent Approach to Simultaneous Technology Mapping, Buffer Insertion, and Gate SizingHsin-Ying Tsai, Chung-Kai Wu, Chih-Cheng Hsu, Jie-Hong R. Jiang. 1-9 [doi]
• FACAM: Design and Optimization of A Compact Energy Efficient FeFET-Based Analog Content Addressable MemoryJiahao Cai, Ann Franchesca Laguna, Zeyu Yang, Yuxiao Yang, Thomas Kämpfe, Zheyu Yan, Cheng Zhuo, Xunzhao Yin. 1-9 [doi]
• Energy-Efficient Accelerator for Scalable Point Transformer Networks with Reduced Data AccessHyunsung Yoon, Jehun Lee, Jae-Joon Kim. 1-9 [doi]
• Designing with Deception: ML- and Covert Gate-Enhanced Camouflaging to Thwart IC Reverse EngineeringJunling Fan, David Selasi Koblah, Domenic Forte. 1-9 [doi]
• Tasa: Thermal-aware 3D-Stacked Architecture Design with Bandwidth Sharing for LLM InferenceSiyuan He, Peiran Yan, YanDong He, Youwei Zhuo, Tianyu Jia. 1-9 [doi]
• JitFilt: Mitigate Jitter-based Side Channel Analysis AttacksDarshana Jayasinghe, Yuanhua Zhong, Sri Parameswaran. 1-9 [doi]
• NeuroPDE: A Neuromorphic PDE Solver Based on Spintronic and Ferroelectric DevicesSiqing Fu, Lizhou Wu, Tiejun Li, Chunyuan Zhang, Sheng Ma, Jianmin Zhang, Yuhan Tang, Jixuan Tang. 1-9 [doi]
• RTPU: Unifying Non-Private and Private Inference with Reconfigurable ArchitectureFuping Li, Ying Wang 0001, Yinghao Yang 0001, Jingxuan Li, Yibo Du, Huawei Li 0001, Yinhe Han 0001, Hang Lu, Xiaowei Li 0001. 1-9 [doi]
• 2T-Tiny: Runtime-Reconfigurable Throughput-Optimized TinyML for Hybrid Inference Acceleration on FPGA SoCsGeorgios Mentzos, Valentin Alexander Frey, Konstantinos Balaskas, Georgios Zervakis 0001, Jörg Henkel. 1-9 [doi]
• Adaptive Graph Learning for Efficient Thermal Analysis of Multi-Stacking Chiplet Systems under Interface VariationsZiyao Yang, Jingbo Sun, Vidya A. Chhabria, Yu Cao 0001. 1-9 [doi]
• Invited Paper: APS: Open-Source Hardware-Software Co-Design Framework for Agile Processor SpecializationYouwei Xiao, Yuyang Zou, Yansong Xu, Yuhao Luo, Yitian Sun, Chenyun Yin, Ruifan Xu, Renze Chen, Yun Liang 0001. 1-9 [doi]
• Revolution or Hype? Seeking the Limits of Large Models in Hardware DesignQiang Xu, Leon Stok, Rolf Drechsler, Xi Wang, Grace Li Zhang, Igor L. Markov. 1-9 [doi]
• ZeroSim: Zero-Shot Analog Circuit Evaluation with Unified Transformer EmbeddingsXiaomeng Yang, Jian Gao, Yanzhi Wang, Xuan Zhang. 1-9 [doi]
• Invited Paper: Mindful AI for Pervasive Health and Wellbeing (PHW)Hamidreza Alikhani, Anil Kanduri, Pasi Liljeberg, Amir M. Rahmani, Nikil D. Dutt. 1-8 [doi]
• EI-TR: A Versatile Exponential Integrator Framework for Transient Analysis of Generic Nonlinear CircuitsHang Zhou, Zhenjie Lu, Quan Chen. 1-9 [doi]
• Accelerating Genome Alignment Pipeline with In-NAND Search Technology and Group Testing TechniquesMing-Hsiang Tsai, Ming-Liang Wei, Chia-Chun Chien, Po-Hao Tseng, Yung-Chun Lee, Hsiang-Pang Li, Chia-Lin Yang. 1-10 [doi]
• Invited Paper: 2025 ICCAD CAD Contest Problem A: Hardware Trojan Detection on Gate-Level NetlistChung-Han Chou, Chih-Jen (Jacky) Hsu, Hung-Chun Chiu, Kai-Chiang Wu, Yu-Guang Chen, Zhuo Li. 1-5 [doi]
• LaZagna: An Open-Source Framework for Flexible 3D FPGA Architectural ExplorationIsmael Youssef, Hang Yang, Cong Hao. 1-9 [doi]
• HD-MoE: Hybrid and Dynamic Parallelism for Mixture-of-Expert LLMs with 3D Near-Memory ProcessingHaochen Huang, Shuzhang Zhong, Zhe Zhang 0006, Shuangchen Li, Dimin Niu, Hongzhong Zheng, Runsheng Wang, Meng Li 0004. 1-9 [doi]
• Differentiable Timing-Driven FPGA Placement with Smooth Optimization and ML-Based Delay CalibrationYu-Kang Lin, Zhili Xiong, David Z. Pan. 1-9 [doi]
• Hercules: Hardware accElerator foR stoChastic schedULing in hEterogeneous SystemsVairavan Palaniappan, Adam H. Ross, Amit Ranjan Trivedi, Debjit Pal. 1-9 [doi]
• Achieving Simultaneous Buffering and Steiner Tree Synthesis via Harmonic Based Reinforcement LearningLin Chen, Yuxuan Li, Hu Ding. 1-9 [doi]
• The Munich Microfluidics Toolkit: Design Automation and Simulation Tools for Microfluidic DevicesRobert Wille, Philipp Ebner, Maria Emmerich, Michel Takken. 1-8 [doi]
• MiCo: End-to-End Mixed Precision Neural Network Co-Exploration Framework for Edge AIZijun Jiang, Yangdi Lyu. 1-9 [doi]
• LLM4Verilog: Building Large-Scale, High-Quality Data Infrastructure for Verilog Code Generation via Community EffortsZhongzhi Yu, Chaojian Li, Yongan Zhang, Mingjie Liu, Nathaniel Ross Pinckney, Wenfei Zhou, Rongjian Liang, Haoyu Yang, Haoxing Ren, Yingyan Celine Lin. 1-9 [doi]
• Hyle: An HLS Framework for Hyperdimensional Computing Accelerators on FPGAsCaio Vieira, Antonio Carlos Schneider Beck. 1-9 [doi]
• Half-Height Double-Row CFET Standard Cells for Area Optimized Placement in A7 CMOS NodeHalil Kükner, Ji-Yung Lin, Sheng Yang, Lynn Verschueren, Jürgen Bömmels, Anita Farokhnejad, Maarten Van De Put, Odysseas Zografos, Naoto Horiguchi, Geert Hellings, Marie Garcia Bardon, Julien Ryckaert. 1-8 [doi]
• Clay: High-level ASIP Framework for Flexible Microarchitecture-Aware Instruction CustomizationWeijie Peng, Youwei Xiao, Yuyang Zou, Zizhang Luo, Yun (Eric) Liang. 1-9 [doi]
• OA-LAMA: An Outlier-Adaptive LLM Inference Accelerator with Memory-Aligned Mixed-Precision Group QuantizationHuangxu Chen, Yingbo Hao, Yi Zou, Xinyu Chen. 1-9 [doi]
• LUT-HD: Accelerating Hyperdimensional Computing Inference via Efficient Table LookupHaodong Lu, Da Tang, Xiqiong Bai, Zexu Zhang, Tianyi Zhou, Xinran Li, Kun Wang. 1-9 [doi]
• Self-Error Detection and Correction Techniques for Reliable and Efficient Selector-Only MemoryHyunJun Lee, Joon-Sung Yang. 1-9 [doi]
• Invited Paper: Circuit and Architecture Design with Emerging Computing ParadigmsSalim Ullah, Siva Satyendra Sahoo, Can Li 0024, Chao Li 0065, Liu Liu 0023, Tomas Sousa Pereira, Bo Wen, Xunzhao Yin, Armin Darjani, Nima Kavand, Chakravarthy Bodla, Rupa Yashaswi Panduga, Aniruddh Holemadlu, Johannes Maly, Jonathan Förste, Samarth Vadia, Xiaobo Sharon Hu, Akash Kumar 0001. 1-9 [doi]
• SpikeSynth: Energy-Efficient Adaptive Analog Printed Spiking Neural NetworksPriyanjana Pal, Alexander Studt, Tara Gheshlaghi, Michael Hefenbrock, Michael Beigl, Mehdi Baradaran Tahoori. 1-9 [doi]
• Invited Paper: BitMedViT: Ternary-Quantized Vision Transformer for Medical AI Assistants on the EdgeMikolaj Walczak, Uttej Kallakuri, Edward Humes, Xiaomin Lin 0002, Tinoosh Mohsenin. 1-7 [doi]
• HyDra: SOT-CAM Based Vector Symbolic Macro for Hyperdimensional ComputingMd Mizanur Rahaman Nayan, Che-Kai Liu, Zishen Wan, Arijit Raychowdhury, Azad J. Naeemi. 1-9 [doi]
• 3D-MoE: Accelerating Multi-Expert Activated LLMs on 3D In/Near-Memory Computing Architecture via Hybrid ParallelismXinyu Qu, Zehua Zhang, Runnan Xu, Yufei Ma 0002. 1-9 [doi]
• Uncertainty-Guided Live Measurement Sequencing for Fast SAR ADC Linearity TestingThorben Schey, Khaled Karoonlatifi, Michael Weyrich, Andrey Morozov 0001. 1-9 [doi]
• Making the Best Switch: Encoding Strategy Management for Efficient TFHE Circuit EvaluationMingfei Yu, Gabrielle De Micheli, Giovanni De Micheli. 1-9 [doi]
• LCTMwalk: GPU-Accelerated Transient Thermal Simulation for Liquid-Cooled 2.5D/3D ICs via Random Walks on Circuit Networks of Modified Compact Thermal ModelsZhixuan Dong, Yonghan Luo, Yuan Meng, Changhao Yan, Zhaori Bi, Keren Zhu 0001, Sheng-Guo Wang, Dian Zhou, Xuan Zeng 0001. 1-9 [doi]
• SOME: Symmetric One-Hot Matching Elector - A Lightweight Microsecond Decoder for Quantum Error CorrectionXinyi Guo, Geguang Miao, Shinichi Nishizawa, Hiromitsu Awano, Shinji Kimura, Takashi Sato 0001. 1-9 [doi]
• PAR-CIM: A Precise/Approximate Reconfigurable Digital CIM Macro with 0.35-4b Fractional Mixed-Bitwidth QuantizationHan Zhang, Zhenyu Xue, Wente Yi, Tianshuo Bai, Lehao Tan, Jingcheng Gu, Weijie Ding, Wang Kang 0001, Biao Pan. 1-9 [doi]
• Coflex: Enhancing HW-NAS with Sparse Gaussian Processes for Efficient and Scalable DNN Accelerator DesignYinhui Ma, Tomomasa Yamasaki, Zhehui Wang, Tao Luo, Bo Wang. 1-9 [doi]
• VeriRL: Boosting the LLM-based Verilog Code Generation via Reinforcement LearningFu Teng, Miao Pan, Xuhong Zhang 0002, Zhezhi He, Yiyao Yang, Xinyi Chai, MengNan Qi, Liqiang Lu, Jianwei Yin. 1-9 [doi]
• GAIA: Glass-Aware I/O MiddlewareHung-Yuna Chen, Chun-Feng Wu, Yuna-Hao Chang, David Hung-Chang Du. 1-9 [doi]
• Gotta Hash 'Em All! Accelerating Hash Functions for Zero-Knowledge Proof ApplicationsNojan Sheybani, Tengkai Gong, Anees Ahmed, Nges Brian Njungle, Michel A. Kinsy, Farinaz Koushanfar. 1-9 [doi]
• Twill: Scheduling Compound AI Systems on Heterogeneous Mobile Edge PlatformsZain Taufique, Aman Vyas, Antonio Miele, Pasi Liljeberg, Anil Kanduri. 1-9 [doi]
• QuickFlow: An Efficient Local Search Method to Map Convolutions on Spatial ArchitecturesMarco Ronzani, Cristina Silvano. 1-9 [doi]
• Building Reasoning LLMs for Hardware Design Generation via Function-Aligned Differentiated RevisionWeimin Fu, Shijie Li 0009, Kaichen Yang, Xuan Silvia Zhang, Yier Jin, Xiaolong Guo 0001. 1-8 [doi]
• ProtoCellLayout: Prototype-Guided Graph Learning for Accurate and Generalizable Standard Cell Layout PPA EstimationZhiyuan Luo, Le Zhou, Zenghui Zhang, Jie Zhou, Zhien Li, Huiqing You, Feng Yao, Zhenyu Zhao. 1-9 [doi]
• Augmented Co-Simulation for Fast Functional and System-Level Verification of HLS AcceleratorsMichele Fiorito, Serena Curzel, Fabrizio Ferrandi. 1-9 [doi]
• Scalable and Asynchronous Differential Checkpointing for Intermittently Powered DevicesYoungbin Kim, Yoojin Lim. 1-9 [doi]
• Semidefinite Programming-Based Decoupling Capacitor Placement for Power Distribution Network OptimizationZong-Ying Cai, Wei-Han Mao, Yao-Wen Chang, Yang Lu, Jerry Bai, Bin-Chyi Tseng. 1-9 [doi]
• Perturbation-efficient Zeroth-order Optimization for Hardware-friendly On-device TrainingQitao Tan, Sung-En Chang, Rui Xia, Huidong Ji, Chence Yang, Ci Zhang, Jun Liu 0075, Zheng Zhan 0001, Zhenman Fang, Zhuo Zou, Yanzhi Wang 0001, Jin Lu 0001, Geng Yuan. 1-9 [doi]
• Closing the Gap: Advantages of Block-Level over Gate-Level in 3D IC Design for Advanced NodesMin-Gyu Park, Pruek Vanna-Iampikul, Sung Kyu Lim. 1-9 [doi]
• Optimal Selection and Placement of Voltage Regulators in 2.5D Heterogeneously Integrated SystemsHangyu Zhang, Divya Yogi, Ramesh Harjani, Sachin S. Sapatnekar. 1-9 [doi]
• HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM SolutionsJing Wang 0171, Shang Liu 0006, Yao Lu 0031, Zhiyao Xie. 1-9 [doi]
• (Invited) FENIX: Flexible and Efficient Hybrid HE/MPC Acceleration with Near-Memory ProcessingTengyu Zhang, Chenqi Lin, Jiangrui Yu, Yi Chen, Shuwen Deng, Meng Li 0004. 1-9 [doi]
• Versatile Rewiring and Concurrent Resynthesis for High-Quality Customized OptimizationJiun-Hao Chen, Jie-Hong R. Jiang, Alan Mishchenko. 1-9 [doi]
• COTIA: Concolic Testing with Intelligent AgentYan Tan, Xiangchen Meng, Yangdi Lyu. 1-9 [doi]
• Ultrafast Density Gradient Accumulation in 3D Analytical Placement with Divergence TheoremPeiyu Liao, Yuxuan Zhao 0001, Siting Liu 0002, Bei Yu 0001. 1-9 [doi]
• ApproxGNN: A Pretrained GNN for Parameter Prediction in Design Space Exploration for Approximate ComputingOndrej Vlcek, Vojtech Mrazek. 1-8 [doi]
• TOGGLE: Temporal Logic-Guided Large Language Model Compression for EdgeKhurram Khalil, Khaza Anuarul Hoque. 1-9 [doi]
• EPiCarbon: A Carbon Modeling Tool for Electro-Photonic AcceleratorsFarbin Fayza, Cansu Demirkiran, Satyavolu Papa Rao, Darius Bunandar, Udit Gupta, Ajay Joshi. 1-9 [doi]
• A Parallel Analytical Legalization Algorithm via Alternating Direction Method of MultipliersJaekyung Im, Seokhyeong Kang. 1-8 [doi]
• Circuit Folding: Scalable and Graph-Based Circuit Cutting via Modular Structure ExploitationShuwen Kan, Yanni Li, Hao Wang, Sara Mouradian, Ying Mao. 1-9 [doi]
• Invited Paper: Towards Generative AI for Analog and RF IC Design: From Spec to LayoutHyunsu Chae, Seunggeun Kim, Souradip Poddar, Xiaohan Gao, Sensen Li, David Z. Pan. 1-9 [doi]
• Robin: RWKV Accelerator using Block Circulant Matrices based on FPGAZeYu Li, Shangkun Li, Chuyi Dai, Chaofang Ma, Jiawei Liang, Xin Li, Wei Zhanh. 1-9 [doi]
• SNO: Securing Network Function Offloading on FPGA-based SmartNICs in Untrusted CloudsYunkun Liao, Jingya Wu, Wenyan Lu, Hang Lu, Xiaowei Li 0001, Guihai Yan. 1-9 [doi]
• Synthesis of Standard Cells of Minimum DelaySehyeon Chung, Hyunbae Seo, Taewhan Kim 0001. 1-8 [doi]
• VeriSAT: the Hardware Design of Modern SAT SolverYue Tao, Shaowei Cai 0001. 1-9 [doi]
• Invited Paper: Rowhammer Mitigation by Approximate Computing: A Compressed Sensing Case StudyYuhang Hao, Yun Wu 0003, Minmin Jiang, Máire O'Neill, Chongyan Gu. 1-8 [doi]
• SPARTA: Spike-Aware Token Skipping Co-Optimization with Heterogeneous ReRAM-CIM Architecture for Spiking Transformer AccelerationPinfeng Jiang, Letian Wang, Yilong Fang, Yi Wang, Mingde Zhu, Xiangshui Miao, Xingsheng Wang. 1-9 [doi]
• QUARK: Quantization-Enabled Circuit Sharing for Transformer Acceleration by Exploiting Common Patterns in Nonlinear OperationsZhixiong Zhao, Haomin Li 0002, Fangxin Liu, Yuncheng Lu, Zongwu Wang, Tao Yang 0031, Li Jiang 0002, Haibing Guan. 1-9 [doi]
• Seeing Through Designs: Attention-Based Knowledge Transfer for Preference-Guided Microarchitecture SearchYiyang Zhao, Xuyang Zhao, Zhaori Bi, Ming Zhu 0016, Qiwei Zhan, Keren Zhu 0001, Fan Yang 0001, Changhao Yan, Dian Zhou, Xuan Zeng 0001. 1-9 [doi]
• e-boost: Boosted E-Graph Extraction with Adaptive Heuristics and Exact SolvingJiaqi Yin, Zhan Song, Chen Chen, Yaohui Cai, Zhiru Zhang, Cunxi Yu. 1-9 [doi]
• The Fellowship of the Leak: Power Analysis of a Masked FrodoKEM Hardware AcceleratorMartin Schmid, Giuseppe Manzoni, Aydin Aysu, Elif Bilge Kavun. 1-8 [doi]
• LsCMM-H: A TCO-Optimized Hybrid CXL Memory Expansion Architecture with Log StructureXingyu Chen, Xiangrui Zhang, Sirui Peng, Zhiwang Guo, Haidong Tian, Xiankui Xiong, Xiaoyong Xue, Xiaoyang Zeng. 1-7 [doi]
• ScanNow: A Scan Window-Based Sparse Matrix Multiplication Accelerator DesignChaofang Ma, Lin Jiang, ZeYu Li, Hanwei Fan, Maolin Wang, Jiang Xu, Wei Zhang. 1-9 [doi]
• Invited Paper: Pushing SIMD Efficiency in Homomorphic Encryption for Machine Learning via Pattern-Aware Ciphertext EncodingRan Ran, Zhaoting Gong, Zhaowei Li, Wujie Wen. 1-9 [doi]
• Automated Design Space Exploration in High-Level Physical SynthesisLinfeng Du, Jiawei Liang, Jason Lau, Yuze Chi, Yutong Xie 0011, Chunyou Su, Afzal Ahmad, Zifan He, Jake Ke, Jinming Ge, Jason Cong, Wei Zhang 0012, Licheng Guo. 1-9 [doi]
• Mitigating Resource Contention for Responsive On-device Machine Learning InferencesMinSung Kim, Jihoon Lee, Seongjin Chou, Whisoo Chung, Inwoo Kim, Woosung Kang, Hyosu Kim, Sangeun Oh, Hoon Sung Chwa, Kilho Lee. 1-9 [doi]
• Waferscale Silicon Photonics Systems: A Cost-Benefit Analysis and OptimizationRobert Bao, Zongrui Cai, Shuangliang Chen, Ajay Joshi, Darius Bunandar, Rakesh Kumar 0002. 1-9 [doi]
• Software-Style Hardware Debugging: A Hardware Generation, Simulation and Debugging FrameworkWeiran Liu, Shixuan Chen, Chun Yang, Xianhua Liu 0001. 1-9 [doi]
• NSTherm: An Error-Bounded Network-Stochastic Fusion Thermal Simulator for Geometry-Adaptable Chiplets via Diffeomorphic Mapping and Neural-Guided Variance ReductionYuan Meng, Yuyan Wang, Zhixuan Dong, Yonghan Luo, Changhao Yan, Keren Zhu 0001, Zhaori Bi, Sheng-Guo Wang, Dian Zhou, Xuan Zeng 0001. 1-9 [doi]
• MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive DebuggingJinwei Tang, Jiayin Qin, Nuo Xu 0013, Pragnya Sudershan Nalla, Yu Cao, Yang Katie Zhao, Caiwen Ding. 1-9 [doi]
• LLM-on-the-Palm: Mobile LLM Inference with PIM-Enhanced NAND Flash MemoryHyunjin Kim, SangHyeok Han, Jae-Joon Kim. 1-9 [doi]
• 3D Acceleration for Mixture-of-Experts and Multi-Head Attention Spiking Transformers with Dynamic Head PruningBoxun Xu, Junyoung Hwang, Pruek Vanna-Iampikul, Yuxuan Yin, Sung Kyu Lim, Peng Li 0001. 1-9 [doi]
• Invited Paper: LLM-Enhanced GPU-Optimized Physical Design at ScaleYi-Chen Lu, Hao-Hsiang Hsiao, Haoxing Ren. 1-7 [doi]
• Optimizing Neural Networks with Learnable Non-Linear Activation Functions via Lookup-Based FPGA AccelerationMengyuan Yin, Benjamin Chen Ming Choong, Chuping Qu, Rick Siow Mong Goh, Weng-Fai Wong, Tao Luo 0014. 1-9 [doi]
• How Do Errors Impact NN Accuracy on Non-Ideal Analog PIM? Fast Evaluation via an Error-Injected Robustness MetricLidong Guo, Zhenhua Zhu, Qiushi Lin, Yuan Xie 0001, Huazhong Yang, Wangyang Fu, Yu Wang 0002. 1-9 [doi]
• PIGen: Accelerating ReRAM Co-Design via Generative Physics-Informed ModelingZihan Zhang, Marco Donato. 1-9 [doi]
• Orthrus: Dual-Loop Automated Framework for System-Technology Co-OptimizationYi Ren, Baokang Peng, Chenhao Xue, Kairong Guo, Yukun Wang, Guoyao Cheng, Yibo Lin, Lining Zhang, Guangyu Sun 0003. 1-9 [doi]
• Secure Token Pruning Mechanism and Accelerator for Vision TransformerQiuran Li, Jingkui Yang, Fanjin Xu, Fei Zhang, Xingyu Zhang, Zhe Li, Jinjin Shao, Yaohua Wang. 1-9 [doi]
• SubtreeLU: High-Performance Parallel Sparse LU Factorization for Circuit SimulationJiawen Cheng, Yibin Zhang, Wenjian Yu. 1-8 [doi]
• Invited Paper: Rapid Performance Evaluation and Optimized AI Inference for Heterogeneous Automotive ChipletsChristoph Schorn, Axel Sauer, Marius Fischer, Ingo Feldner, Thomas Schamm, Falk Rehm. 1-8 [doi]
• DecoRTL: A Run-Time Decoding Framework for RTL Code Generation with LLMsMohammad Akyash, Kimia Zamiri Azar, Hadi Mardani Kamali. 1-9 [doi]
• No Redundancy, No Stall: Lightweight Streaming 3D Gaussian Splatting for Real-time RenderingLinye Wei, Jiajun Tang 0001, Fan Fei, Boxin Shi, Runsheng Wang, Meng Li. 1-9 [doi]
• Revisiting Noise-adaptive Transpilation in Quantum Computing: How Much Impact Does it Have?Yuqian Huo, Jinbiao Wei, Christopher Kverne, Mayur Akewar, Janki Bhimani, Tirthak Patel. 1-9 [doi]
• Leveraging GPU for Better Detailed Placement QualityChen-Han Lu, Wen-Hao Liu, Haoxing Ren, Ting-Chi Wang. 1-9 [doi]
• CacheGuardian: A Timing Side-Channel Resilient LLC DesignZiang Zhou, Qi Zhu, Hao Lan, Huifeng Zhu, Wei Yan 0005, Chenglu Jin, Xuejun An, Xiaochun Ye. 1-9 [doi]
• Hummingbird: A Smaller and Faster Large Language Model Accelerator on Embedded FPGAJindong Li 0001, Tenglong Li, Ruiqi Chen, Guobin Shen, Dongcheng Zhao, Qian Zhang 0080, Yi Zeng 0001. 1-9 [doi]
• CarbonClarity: Understanding and Addressing Uncertainty in Embodied Carbon for Sustainable ComputingXuesi Chen, Leo Han, Anvita Bhagavathula, Udit Gupta 0001. 1-9 [doi]
• LP-Spec: Leveraging LPDDR PIM for Efficient LLM Mobile Speculative Inference with Architecture-Dataflow Co-OptimizationSiyuan He, Zhantong Zhu, YanDong He, Tianyu Jia. 1-9 [doi]
• Snake-3D: Differentiable Learning for Cross-Tier Logic Path Snaking Optimization in 3D ICsYen-Hsiang Huang, Sung Kyu Lim. 1-9 [doi]
• A Graph-Based Deep Reinforcement Learning Framework for Quantum Circuit Mapping with Look-Ahead Rewards and Biased ExplorationYueran Zhao, Kaiqi Li, Ziying Guo, Jialin Zhang. 1-9 [doi]
• A Geometry-Material Aware Point Cloud Transformer for Large-scale Unstructured Thermal Analysis in 2.5D ICsDekang Zhang, Dan Niu, Yichao Cao, Yichao Dong, Zhenya Zhou, Zhou Jin 0001. 1-9 [doi]
• FabThink: A Wafer Analysis Multimodal LLM via Chain-of-Thought-Driven Retrieval AugmentationYuqi Jiang, Qian Jin, Xudong Lu 0004, Jinyuan Deng, Hao Geng, HanMing Wu, Qi Sun 0002, Cheng Zhuo. 1-9 [doi]
• Adder-DCIM: A Parallel Bit-Flexible Digital CIM Accelerator Joint Model Compression Framework for AdderNet InferenceHaikang Diao, Chuyue Tang, Bocheng Xu, Haoyang Luo, Meng Li 0004, Yuan Wang 0001, Xiyuan Tang. 1-9 [doi]
• P2P-Chiplet: Partition and Placement Co-Optimization for Multi-Chiplet ArchitectureQidie Wu, Jiangyuan Gu, Xuguang Yuan, Shaojun Wei, Shouyi Yin. 1-9 [doi]
• Invited Paper: Resource Management on Heterogeneous Chiplets SystemsWanli Chang 0001, Yili Guo, Weijie Wang, Yaqi Yao, Fuyang Zhao, Yinjie Fang, Kuan Jiang, Liyun Shang. 1-8 [doi]
• PLAIN: Leveraging High Internal Bandwidth in PIM for Accelerating Large Language Model Inference via Mixed-Precision QuantizationYiwei Hu, Fangxin Liu, Zongwu Wang, Yilong Zhao, Tao Yang 0031, Li Jiang 0002, Haibing Guan. 1-9 [doi]
• Uranus: Ultra-efficient Acceleration Architecture for the Privacy Inference of Graph Neural NetworksXicheng Xu, Yinghao Yang 0001, Fuyao Liu, Xiaowei Li 0001, Hang Lu. 1-9 [doi]
• ASTRA: Automatic Sizing of Transistors with Reasoning AgentsWei W. Xing, Baowen Ou, Yuxuan Zhang, Zhuohua Liu, Yuanqi Hu. 1-9 [doi]
• TickTockStack: In-Datapath Current Imbalance Elimination Using Clocked Differential Logic in a Voltage Stacked Vector ProcessorMichal Andrzej Gorywoda, Wanyeong Jung. 1-9 [doi]
• Unveiling the Mask: Trusted Semiconductor Manufacturing through Wafer-Level Mask-Set AttestationSuraag Sunil Tellakula, Ching-Yi Chang, Matthew Nigh, Christos Vasileiou, John M. Carulli, Yiorgos Makris. 1-9 [doi]
• RIROS: A Parallel RTL Fault SImulation FRamework with TwO-Dimensional Parallelism and Unified ScheduleJiaping Tang, Jianan Mu, Zizhen Liu, Ge Yu, Tenghui Hua, Bin Sun, Silin Liu, Jing Ye 0001, Huawei Li 0001. 1-9 [doi]
• 3D DRC: Design Rule Checking for 3D IC with U-Net-based Non-Manhattan OptimizationShunjie Chang, Youran Wu, Jianli Chen, Jun Yu, Kun Wang. 1-9 [doi]
• SpectrePrefetch: Undermining Cache-Centric Secure Speculation with Modern Hardware PrefetchersFang Jiang, Fei Tong 0001, Xiaoyu Cheng, Zhe Zhou, Hongyu Wang, Yuxing Mao. 1-9 [doi]
• HLSTester: Efficient Testing of Behavioral Discrepancies with LLMs for High-Level SynthesisKangwei Xu, Bing Li 0005, Grace Li Zhang, Ulf Schlichtmann. 1-9 [doi]
• Optimizing Memory Latency and Bandwidth of Spiking Neural Network Accelerators on FPGA via Sparse HashingShadi Matinizadeh, M. Lakshmi Varshika, Anup Das 0001. 1-9 [doi]
• Invited Paper: CMOS 2.0 - Redefining the Future of ScalingMoritz Brunion, Navaneeth Kunhi Purayil, Francesco Dell'Atti, Sebastian Lam, Refik Bilgic, Mehdi B. Tahoori, Luca Benini, Julien Ryckaert. 1-8 [doi]
• Invited Paper: System and Technology Co-Optimization Framework for a Disaggregated System with Passive Die 2.5D IntegrationGauthaman Murali, Mudit Bhargava, Shairfe Salahuddin, Zhichao Chen, Archana Pandey, Srivatsa Rangachar Srinivasa, Prerna Budhkar, Ragh Kuttappa, Vinayak Honkote, Prashanth Sakthi, Myung Hee Na, Tanay Karnik. 1-7 [doi]
• H3D: Heterogeneous Resources Aware Global Router for Face-to-Face Bonded 3D ICsYuxuan Zhao 0001, Feng Gu, Siting Liu 0002, Peiyu Liao, Bei Yu 0001. 1-9 [doi]
• AccelStack: A Cost-Driven Analysis of 3D-Stacked LLM AcceleratorsChen Bai, Xin Fan, Zhenhua Zhu, Wei Zhang, Yuan Xie. 1-9 [doi]
• Design of Machine Learning Accelerators as RISC-V Extensions using an Open Source Tool FlowBatuhan Sesli, Muhammad Sabih, Frank Hannig, Jürgen Teich. 1-9 [doi]
• Performance-Driven Pre-Assignment Routing for High-Speed Package DesignsShao-Hsiang Chen, Zeng-Wei Chen, Po-Jen Lin, Hung-Jen Hsu, Hsin-Ying Lin, Yung-Hsiang Chuang, Huang-Yu Chen, Jim Chang, Yao-Wen Chang. 1-9 [doi]
• VIRTUAL: Vector-based Dynamic Power Estimation via Decoupled Multi-Modality LearningYuntao Lu, Mingjun Wang, Yihan Wen, Boyu Han, Jianan Mu, Huawei Li 0001, Bei Yu 0001. 1-9 [doi]
• Invited Paper: CURE-Fuzz: Curiosity-Driven Reinforcement Learning for Agile Hardware TestingHanwei Fan, Ya Wang, Xiaofeng Zhou, Sicheng Li, Binguang Zhao, Yangdi Lyu, Jiang Xu, Wei Zhang. 1-9 [doi]
• Target Circuit Matching in Large-Scale Netlists Using GNN-Based Region PredictionSangwoo Seo, Jimin Seo, Yoonho Lee 0002, Donghyeon Kim, Hyejin Shin, Banghyun Sung, Chanyoung Park 0001. 1-9 [doi]
• CROP: Circuit Retrieval and Optimization with Parameter Guidance using LLMsJingyu Pan, Isaac Jacobson, Zheng Zhao, Tung-Chieh Chen, Guanglei Zhou, Chen-Chia Chang, Vineet Rashingkar, Yiran Chen 0001. 1-9 [doi]
• Prompt, Fab, Flex: Agentic LLMs for Flexible Electronics DesignFarshad Firouzi, Bahareh J. Farahani, Polykarpos Vergos, Deepesh Sahoo, Nathaniel Bleier, Krishnendu Chakrabarty. 1-9 [doi]
• Energy-Efficient Multi-Operand XOR Logic-Based CIM Accelerator using RRAM technologyAbhairaj Singh, Konstantinos Stavrakakis, Rajendra Bishnoi, Rajiv V. Joshi, Said Hamdioui. 1-7 [doi]
• Invited Paper: Side Channel Vulnerability Analysis of Flexible Neuromorphic CircuitsPriyanjana Pal, Brojogopal Sapui, Mehdi B. Tahoori. 1-7 [doi]
• Rhea: a Framework for Fast Design and Validation of RTL Cache-Coherent Memory SubsystemsDavide Zoni, Andrea Galimberti, Adriano Guarisco. 1-9 [doi]
• Continuous On-Chip Learning in Neural Networks using SOT-MRAM based CIM ArchitecturesAnubha Sehgal, Sandeep Soni, Sumit Diware, Alok Kumar Shukla, Sourajeet Roy, Rajendra Bishnoi. 1-8 [doi]
• SpecMamba: Accelerating Mamba Inference on FPGA with Speculative DecodingLinfeng Zhong, Songqiang Xu, Huifeng Wen, Tong Xie, Qingyu Guo, Yuan Wang 0001, Meng Li 0004. 1-9 [doi]
• Building an Open CGRA Ecosystem for Agile InnovationRohan Juneja, Pranav Dangi, Thilini Kaushalya Bandara, Zhaoying Li, Dhananjaya Wijerathne, Li-Shiuan Peh, Tulika Mitra. 1-9 [doi]
• SPIMA: Scalable and Cost-Efficient Sparse Matrix Multiplication via Processing in DRAM ArrayTairali Assylbekov, Minsang Yu, Jaewoo Park 0006, Mingon Kim, Seungsu Kim, Jongeun Lee. 1-8 [doi]
• Invited Paper: Synthesizing Analog & Mixed-Signal Floating-Gate enabled Reconfigurable Fabrics using Analog Standard CellsJennifer Hasler, Afolabi Ige, Linhao Yang, Pranav O. Mathews. 1-7 [doi]
• IncreGPUSTA: GPU-Accelerated Incremental Static Timing Analysis for Iterative Design FlowsHaichuan Liu, Zizheng Guo 0001, Runsheng Wang, Yibo Lin. 1-9 [doi]
• LLM-Barber: Block-Aware Rebuilder for Sparsity Mask in One-Shot for Large Language ModelsYupeng Su, Ziyi Guan, Xiaoqun Liu, Tianlai Jin, Dongkuan Wu, Zhengfei Chen, Graziano Chesi, Ngai Wong 0001, Hao Yu 0001. 1-9 [doi]
• DynVec: An End-to-End Framework for Efficient Vector-Dataflow ExecutionJiangnan Li, Xianfeng Cao, Kaixiang Zhu, Wenbo Yin, Lingli Wang. 1-9 [doi]
• An Adaptive Sparse Matrix Compression CIM Accelerator based on 256Kb SOT-MRAM for Downlink Massive MIMO CommunicationsLiangchen Li, Jianxin Wu, Changyu Li, Liang Zhang, Anyang Yu, Junda Zhao, Zhaohao Wang, Chengyuan Sun, Kaihua Cao, Hongxi Liu, Wang Kang 0001, He Zhang 0011, Weisheng Zhao. 1-9 [doi]
• Optimizing SFQ Circuit Design: A Timing-Driven Framework for Performance-Constrained Area MinimizationRobert S. Aviles, Rassul Bairamkulov, Ziyu Liu, Peter A. Beerel. 1-9 [doi]
• Differentiable Physical OptimizationYufan Du, Zizheng Guo 0001, Runsheng Wang, Yibo Lin. 1-9 [doi]
• "Energon": Unveiling Transformers from GPU Power and Thermal Side-ChannelsArunava Chaudhuri, Shubhi Shukla 0001, Sarani Bhattacharya, Debdeep Mukhopadhyay. 1-9 [doi]
• Invited paper - Connecting the D.O.T.S.: Design of fluidic circuit boards for multi-OoC platforms using CAD Tools for StandardizationLaurens Spoelstra, Marlize Kramer, Jasper Rietveld, Josh T. Loessberg-Zahl, Loes Segerink. 1-7 [doi]
• AI-Driven Multi-Die Architecture ExplorationTim Kogel, Holger Keding. 1-4 [doi]
• A Unified Design Flow for Homogeneous and Heterogeneous 3D Integration with Fine-Pitch Hybrid BondingGyumin Kim, Heechun Park. 1-9 [doi]
• RSizing: Robust Bayesian Optimization for Analog Circuit Sizing Under Process VariationsJindong Tu, Yapeng Li, Peng Xu 0052, Tuo Li, Guoqing Li, Zushuai Xie, Bei Yu 0001, Tinghuan Chen. 1-8 [doi]
• DiffCkt: A Diffusion Model-Based Hybrid Neural Network Framework for Automatic Transistor-Level Generation of Analog CircuitsChengjie Liu, Jiajia Li, Yabing Feng, Wenhao Huang, Weiyu Chen, Yuan Du, Jun Yang, Li Du. 1-9 [doi]
• PROFUZZ: Directed Graybox Fuzzing via Module Selection and ATPG-Guided Seed GenerationRaghul Saravanan, Sudipta Paria, Aritra Dasgupta 0002, Swarup Bhunia, Sai Manoj P. D.. 1-9 [doi]
• CLASS: A Controller-Centric Layout Synthesizer for Dynamic Quantum CircuitsYu Chen, Yilun Zhao 0002, Bing Li 0017, He Li, Mengdi Wang 0004, Yinhe Han 0001, Ying Wang 0001. 1-9 [doi]
• PATHE: A Privacy-Preserving Database Pattern Search Platform with Homomorphic EncryptionXuan Wang, Minxuan Zhou, Gabrielle De Micheli, Yujin Nam, Sumukh Pinge, Augusto Vega, Tajana Rosing. 1-9 [doi]
• Adaptive Pin Pattern Modification on Standard Cells Towards ECO RoutingJaehoon Ahn, Sehyeon Chung, Taewhan Kim 0001. 1-9 [doi]
• (Invited) Generalized GPU-Accelerated Dynamic Programming with Application to Mixed-Cell-Height Detailed PlacementDa Wei Huang, Shao-Yun Fang, Wen-Hao Liu. 1-9 [doi]
• CorDBA: Corners Decoupled Bayesian Approach for yield optimizationYue Zhang, Yunqi Li, Shichang Ye, Bojun Zhang, Jinkai Wang, Zhizhong Zhang, Peng Wang. 1-8 [doi]
• ChronoTE: Crosstalk-Aware Timing Estimation for Routing Optimization via Edge-Enhanced GNNsLeilei Jin, Rongliang Fu, Zhen Zhuang, Liang Xiao 0001, Fangzhou Liu, Bei Yu 0001, Tsung-Yi Ho. 1-9 [doi]
• ILP-Driven FPGA Multiplier Synthesis: A Scalable Framework for Area-Latency Co-OptimizationShangshang Yao, Kunlong Li, Li Shen. 1-9 [doi]
• ToMamba: Towards Token-Efficient Mamba Architecture on FPGAKejia Shi, Yue Cao, Yuhang Du, Jianli Chen, Jun Yu 0010, Kun Wang 0005. 1-9 [doi]
• A Complete Modeling Methodology for Full-chip Parasitic ExtractionYipei Xu, Zhisheng Zeng, Qing He. 1-9 [doi]
• Invited Paper: Analyzing the Robustness of Neuromorphic Computing in the Presence of Variability in Non-Volatile MemoryAndreia Podasca, Anup Das 0001. 1-8 [doi]
• FAB: Fast and Demand-Aware Bandwidth Allocation Method for Wavelength-Routed Optical Networks-on-ChipLiaoyuan Cheng, Mengchu Li, Zhidan Zheng, Tsun-Ming Tseng, Ulf Schlichtmann. 1-9 [doi]
• Everything Depends on Your Hammer: A Systematic Rowhammer Attack Exploration on SPHINCS+S. G. Shoaib Ahamed, Mrityunjay Shukla, Khushang Singla, Sayandeep Saha. 1-9 [doi]
• Tensor Program Optimization for the RISC-V Vector Extension Using Probabilistic ProgramsFederico Nicolás Peccia, Frederik Haxel, Oliver Bringmann 0001. 1-9 [doi]
• BARQ: Boundary-Aware Regularized Training for Accurate Inference on Computing-in-Memory Accelerators with Low-Precision A/D ConversionTingrui Ren, Bi Wang, Liang Wang, Yuanfu Zhao. 1-9 [doi]
• GTA: GPU-Accelerated Track Assignment with Lightweight Lookup Table for Conflict DetectionChunyuan Zhao, Jiarui Wang, Xun Jiang 0002, Jincheng Lou, Yibo Lin. 1-9 [doi]
• Promise: Property Mining for Sequential SynthesisJiahui Xu, Jordi Cortadella, Lana Josipovic. 1-9 [doi]
• Transferable Parasitic Estimation via Graph Contrastive Learning and Label Rebalancing in AMS CircuitsShan Shen, Shenglu Hua, Jiajun Zou, Jiawei Liu 0006, Jianwang Zhai, Chuan Shi 0001, Wenjian Yu. 1-9 [doi]
• Wit-HW: Bug Localization in Hardware Design Code via Witness Test Case GenerationRuiyang Ma, Daikang Kuang, Ziqian Liu, Jiaxi Zhang 0001, Ping Fan, Guojie Luo. 1-9 [doi]
• Invited Paper: End-to-end RFIC Topology Synthesis and Design combining Reinforcement learning and Inverse DesignKaushik Sengupta, Jonathan Zhou, Emir Ali Karahan, Juho Park. 1-8 [doi]
• Invited: IEEE DATC RDF-2025: Enabling an EDA Research EcosystemVidya A. Chhabria, Amur Ghose, Vikram Gopalakrishnan, Andrew B. Kahng, Sayak Kundu, Yiting Liu, Zhiang Wang, Bing-Yue Wu. 1-9 [doi]
• ExactMap: Enhancing Delay Optimization in Parallel ASIC Technology MappingZhenxuan Xie, Lixin Liu, Tianji Liu, Evangeline F. Y. Young. 1-9 [doi]
• When Pipelined In-Memory Accelerators Meet Spiking Direct Feedback Alignment: A Co-Design for Neuromorphic Edge ComputingHaoxiong Ren, Yangu He, Kwunhang Wong, Rui-bao, Ning Lin, Zhongrui Wang, Dashan Shang. 1-9 [doi]
• MMPack: Multi-Mask Co-Design for Ultra-Large Wafer-Scale Package IntegrationShanyi Li, Zhen Zhuang, Siyuan Liang, Bei Yu 0001, Tsung-Yi Ho. 1-9 [doi]
• A Precision-Steerable Electromigration Solver with Physics-Informed Adaptive Graph PartitioningZhaoyuan Liu, Haodong Lu, Jianli Chen, Jun Yu, Kun Wang. 1-9 [doi]
• Equivalent Lumped Element Model for Electromigration Considering Thermal EffectsHengyi Zhu, Wenjie Zhu, Tianshu Hou, Zhigang Ji, Runsheng Wang, Min Tang, Hai-Bao Chen. 1-9 [doi]
• CIMTester: An Agile Golden-Result-Free BIST Compiler for Robust Compute-In-MemoryWenjie Ren, Meng Wu 0005, Mingxuan Li, Peiyu Chen, Tianyu Jia, Le Ye. 1-9 [doi]
• Pathfinder: Constructing Cycle-accurate Taint Graphs for Analyzing Information Flow TracesKatharina Ceesay-Seitz, Flavien Solt, Alexander Klukas, Kaveh Razavi. 1-9 [doi]
• Refinement Strategies for Any-Angle Package Routing with I/O Alignment ConsiderationYu-En Lin, Shao-Yun Fang, Yi-Yu Liu. 1-8 [doi]
• NUA-Timer: Pre-Synthesis Timing Prediction Under Non-Uniform Input Arrival TimesZiyi Wang 0010, Fangzhou Liu, Tsung-Yi Ho, David Z. Pan, Bei Yu 0001. 1-9 [doi]
• DANCE: Dual-Side Agile N:M Sparse Compressed Digital CiM Accelerator for Efficient Compound AIZhonghao Chen, Hongtao Zhong, Jianhe Deng, Mulin Shi, Yongpan Liu, Huazhong Yang, Xueqing Li 0002. 1-9 [doi]
• Squat: Quant Small Language Models on the EdgeXuan Shen, Peiyan Dong, Zhenglun Kong, Yifan Gong 0004, Changdi Yang, Zhaoyang Han, Yanyue Xie, Lei Lu, Cheng Lyu, Chao Wu 0006, Yanzhi Wang 0001, Pu Zhao 0001. 1-9 [doi]
• Quantitative Cost Model and Cost Optimization Methods for Multi-Technology-Node ArchitectureQimin Yuan, Kai Huang 0002, Xiaowen Jiang 0001, Dongliang Xiong. 1-9 [doi]
• High-Resolution Full-Chip Thermal Resistance Extraction of BEOL Interconnects in 3-D ICs Considering Detailed Via ConnectivityTianxiang Zhu, Qipan Wang, Yibo Lin, Runsheng Wang. 1-9 [doi]
• Revisit Choice Network for Synthesis and Technology MappingChen Chen, Jiaqi Yin, Cunxi Yu. 1-9 [doi]
• CoXplorer: Multi-Staged Co-Exploration Framework for AI Model Compression and Accelerator DesignSongchen Ma, Junyi Wu, Yonghao Tan, Pingcheng Dong, Peng Luo, Di Pang, Yu Liu 0007, Xuejiao Liu, Luhong Liang, Kwang-Ting Cheng, Fengbin Tu. 1-9 [doi]
• Invited Paper: Feature-to-Classifier Co-Design for Mixed-Signal Smart Flexible Wearables for Healthcare at the Extreme EdgeMaha Shatta, Konstantinos Balaskas, Paula Carolina Lozano Duarte, Georgios Panagopoulos, Mehdi B. Tahoori, Georgios Zervakis 0001. 1-9 [doi]
• AI Analog Circuit Design Agents : On Knowledge Extraction and Transfer with Knowledge GraphsKarthik Somayaji N. S, Peng Li. 1-9 [doi]
• Invited Paper: Optimizing Privacy-Preserving Primitives to Support LLM-Scale ApplicationsYaman Jandali, Ruisi Zhang, Nojan Sheybani, Farinaz Koushanfar. 1-9 [doi]
• STAR: Improving Lifetime and Performance of High-Capacity Modern SSDs Using State-Aware RandomizerOmin Kwon, Kyungjun Oh, Jaeyong Lee, Myungsuk Kim, Jihong Kim 0001. 1-9 [doi]
• MoE-OPU: An FPGA Overlay Processor Leveraging Expert Parallelism for MoE-based Large Language ModelsShaoqiang Lu, Yangbo Wei, Junhong Qian, Chen Wu, Xiao Shi 0001, Lei He 0001. 1-9 [doi]
• Quantum State Preparation Based on LimTDDXin Hong, Chenjian Li, Aochu Dai, Sanjiang Li, Shenggang Ying, Mingsheng Ying. 1-8 [doi]
• DevTrace: Lightweight Plug-In Design for PCIe Transaction Tracing in Edge Intelligence WorkloadsZhibai Huang, Kailiang Xu, Zhixiang Wei, Yinghao Deng, Chen Chen, Yun Wang, Fangxin Liu, Mingyuan Xia 0001, Zhengwei Qi. 1-9 [doi]
• EarDVFS: Environment-Adaptable RL-based DVFS for Mobile DevicesJaeheon Kwak, Sangeun Oh, Jinkyu Lee 0001, Insik Shin. 1-9 [doi]
• CIMWise: An IREE-based End-To-End AI Compiler with Auto-Tuning for CIM ProcessorsBo Mai, Jin Wang, Zhen Zhai, Liang Zhang, Yufu Zhang, Longyang Lin. 1-8 [doi]
• BITLUME: Precision-Flexible Photonic Computing for Ultra-Fast and Energy-Efficient DNN AccelerationChengpeng Xia, Haibo Zhang 0001, Hao Zhang 0058, Yawen Chen 0001, Amanda Susan Barnard. 1-9 [doi]
• GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder AlignmentWenji Fang, Wang Jing, Yao Lu 0031, Shang Liu 0006, Zhiyao Xie. 1-9 [doi]
• EqMap: FPGA LUT Remapping using E-GraphsMatthew Hofmann, Berk Gokmen, Zhiru Zhang. 1-9 [doi]
• HyperEF 2.0: Spectral Hypergraph Coarsening via Krylov Subspace Expansion and Resistance-Based Local ClusteringHamed Sajadinia, Zhuo Feng. 1-9 [doi]
• MM-GRADE: A Multi-Modal EDA Tool Documentation QA Framework Leveraging Retrieval Augmented GenerationYuan Pu 0001, Zhuolun He, Shutong Lin, Jiajun Qin, Xinyun Zhang, Hairuo Han, Haisheng Zheng, Yuqi Jiang, Cheng Zhuo, Qi Sun 0002, David Z. Pan, Bei Yu 0001. 1-9 [doi]
• An Efficient Routing Optimization Framework for Silicon-Based Spin-Qubit DevicesChing-Yao Huang, Wai-Kei Mak. 1-9 [doi]
• STMC: Small-Tile Multiple-Copy Compilation for Reliable Measurement-Based Quantum ComputingRongchao Dong, Zewei Mo, Yingheng Li, Aditya Pawar, Jun Yang 0002, Youtao Zhang, Xulong Tang. 1-9 [doi]
• BUFFALO: PPA-Configurable, LLM-based Buffer Tree Generation via Group Relative Policy OptimizationHao-Hsiang Hsiao, Yi-Chen Lu, Sung Kyu Lim, Haoxing Ren. 1-9 [doi]
• CoP&R: Co-Optimizing Place-and-Route for Standard Cell Layout via MCTS and AllSATYen-Ju Su, Jiun-Cheng Tsai, Hsuan-Ming Huang, Aaron C.-W. Liang, Han-Ya Tsai, Wei-Min Hsu, Jen-Hang Yang, Charles H.-P. Wen. 1-9 [doi]
• Invited Paper: Liquid Computing: Towards Programmable MicrofluidicsLuca Pezzarossa, Joel August Vest Madsen, Alexander Marc Collignon, Jan Madsen. 1-7 [doi]
• Towards Multi-Objective Routing: A Novel Coreset-based Transfer Learning FrameworkXianglu Wang, Hu Ding. 1-9 [doi]
• GeoFA: A Geometric Finite Automaton Engine for Efficient Layout Pattern MatchingQingsheng Qiu, Ziwen Zheng, Boyu Shi, Chao Wang. 1-9 [doi]
• QQ: Is 2-bit Enough? Exploiting Quantization to Enhance Computation and Memory Efficiency in Quantum SimulationHyoju Seo, Seokhyeon Lee, Yongtae Kim. 1-9 [doi]
• Efficient Analytical Placement Algorithm with Hybrid Fence Region Constraints Using Non-Newtonian Fluid ModelJai-Ming Lin, Hung-Wei Hsu, Tan Huang, Chen-Fa Tsai, De-Shiun Fu, Shih-Cheng Huang. 1-9 [doi]
• TREX-F: TRustability of Electronics using X-ray based FingerprintingTishya Sarma Sarkar, Shuvodip Maitra, Abhishek Chakraborty 0001, Sarani Bhattacharya, Debdeep Mukhopadhyay. 1-9 [doi]
• COBRA: Algorithm-Architecture Co-optimized Binary Transformer Accelerator for Edge InferenceYe Qiao, Zhiheng Chen, Yian Wang, Yifan Zhang, Yunzhe Deng, Sitao Huang. 1-8 [doi]
• Diff-DiT: Temporal Differential Accelerator for Low-bit Diffusion Transformers on FPGAShidi Tang, Pengwei Zheng, Ruiqi Chen 0001, Yuxuan Lv, Bruno da Silva 0001, Ming Ling. 1-9 [doi]
• Automatic Microarchitecture-Aware Custom Instruction Design for RISC-V ProcessorsEvgenii Rezunov, Niko Zurstraßen, Lennart M. Reimann, Rainer Leupers. 1-9 [doi]
• MIRAGE: Microarchitectural Footprints for Detecting Adversarial Attacks in One-Shot InferenceSoumi Chatterjee, Debadrita Talapatra, Nimish Mishra, Aritra Hazra, Debdeep Mukhopadhyay. 1-9 [doi]
• Opto-ViT: Architecting a Near-Sensor Region of Interest-Aware Vision Transformer Accelerator with Silicon PhotonicsMehrdad Morsali, Chengwei Zhou, Deniz Najafi, Sreetama Sarkar, Pietro Mercati, Navid Khoshavi, Peter A. Beerel, Mahdi Nikdast, Gourav Datta, Shaahin Angizi. 1-9 [doi]
• Advanced Packaging Warpage Modeling with DeepONet-Based Operator LearningShao-Yu Lo, Che-Ming Chang, Yao-Wen Chang. 1-9 [doi]
• OptiRange: An Efficient ReRAM-Based PIM Accelerator with ADC Resolution OptimizationSangkyu Jeon, Gisan Ji, Yeonggeon Kim, Youngjun Park, Sangyeon Kim, Sungju Ryu. 1-9 [doi]
• MuSTNet: SAT-based Exact Multi-Stage Transistor Network Synthesis with Placement AwarenessJiun-Cheng Tsai, Wei-Min Hsu, Kuei-Lin Wu, Hsuan-Ming Huang, Jen-Hang Yang, Heng-Liang Huang, Yen-Ju Su, Charles H.-P. Wen. 1-8 [doi]
• SERA-Float: A Soft Error Resilient Approximate Floating-Point Computing FormatVishesh Mishra, Marcello Traiola, Angeliki Kritikakou, Olivier Sentieys, Urbi Chatterjee. 1-9 [doi]
• HRAMTran: A Hybrid-RAM Transformer Accelerator With Dynamic Sparsity Floating-Point CIM and Written-Back Transpose ArrayBojun Zhang, Jinkai Wang, Xianan Zhu, Ziyuan Guo, Zhengkun Gu, Kaili Zhang, Zhizhong Zhang 0004, Kun Zhang 0030, Weisheng Zhao, Yue Zhang 0010. 1-9 [doi]
• Invited Paper: 2025 ICCAD CAD Contest Problem C: Incremental Placement Optimization Beyond Detailed Placement: Simultaneous Gate Sizing, Buffering, and Cell RelocationYi-Chen Lu, Rongjian Liang, Wen-Hao Liu 0001, Haoxing Ren. 1-3 [doi]
• FeNOMS: Enhancing Open Modification Spectral Library Search with In-Storage Processing on Ferroelectric NAND (FeNAND) FlashSumukh Pinge, Ashkan Moradifirouzabadi, Keming Fan, Prasanna Venkatesan Ravindran, Tanvir H. Pantha, Po-Kai Hsu, Zheyu Li, Weihong Xu, Zihan Xia, Flavio Ponzina, Winston Chern, TaeYoung Song, Priyankka Gundlapudi Ravikumar, Mengkun Tian, Lance Fernandes, Huy Tran, Hari Jayasankar, Hang Chen, Chinsung Park, Amrit Garlapati, Kijoon Kim, Jongho Woo, Suhwan Lim, Kwangsoo Kim, Wanki Kim, Daewon Ha, Duygu Kuzum, Shimeng Yu, Sourav Dutta, Asif Khan, Tajana Rosing, Mingu Kang. 1-9 [doi]
• Towards Accurate Characterization of In-Memory Computing Non-Idealities: A Physics & Data Co-Driven Generative FrameworkJing Kou, Guangyao Wang, Saiya Wang, Yuexi Lv, Liang Zhang, Chenglin Yu, Xinghao Cui, Yulong Liu, Wei. W. Xing, Wang Kang 0001. 1-9 [doi]
• SAFF: Scalable Acceleration of GNN-based Machine Learning Force Fields using Tensor-Aware Hardware for Molecular SimulationSeohye Ha, Yunki Han, Taehwan Kim, Jiwan Kim, Junyoung Park, GunHee Park, Lee-Sup Kim. 1-9 [doi]
• WROXIM: A Network-Level Simulation Platform for Wavelength-Routed Optical Networks-on-ChipJeng-De Chang, Zhidan Zheng, Liaoyuan Cheng, Liu-Xuan-Wei Zhang, Tsun-Ming Tseng, Ing-Chao Lin, Ulf Schlichtmann. 1-9 [doi]
• Invited Paper: FEMU: An Open-Source and Configurable Emulation Framework for Prototyping TinyAI Heterogeneous SystemsSimone Machetti, Deniz Kasap, Juan Sapriza, Rubén Rodríguez Álvarez, Hossein Taji, José Miranda, Miguel Peón Quirós, David Atienza. 1-8 [doi]
• Diffusion-Model-Enhanced Layout Pattern Generation for Sub-3nm DFMGuanglei Zhou, Chen-Chia Chang, Junyao Zhang, Jingyu Pan, Yiran Chen 0001. 1-7 [doi]
• Routing-Aware Placement for Zoned Neutral Atom-based Quantum ComputingYannick Stade, Wan-Hsuan Lin, Jason Cong, Robert Wille. 1-9 [doi]
• Defense in the Reverse Fragment: RL-Based Partial Netlist Hardware Trojan DetectionBolun Li, Chen Dong, Decheng Qiu, Mingzhi Chen, Yang Yang. 1-7 [doi]
• Open3DFlow: An Open-Source EDA Platform for 3D Chip Design with AI EnhancementYifei Zhu, Dawei Feng, Zhenxuan Luan, Lei Ren, Weiwei Chen, Zhangxi Tan. 1-9 [doi]
• MASIM: An Energy-Efficient Multi-Array Scheduler for SIMD Logic-in-Memory ArchitecturesXingyue Qian, Chen Nie, Zhezhi He, Weikang Qian. 1-9 [doi]
• Invited Paper: Hardware-Software Co-Design for Highly Optimized, Customized, and Reliable AI SystemsJörg Henkel, Mehdi B. Tahoori, Heba Khdr, Hassan Nassar, Vincent Meyers, Deming Chen, Selin Yildirim, Yingbing Huang, Nirmal R. Saxena, Saurabh Hukerikar, Srivi Dhruvanarayan. 1-9 [doi]
• DiSPlace: Diffusion-Sharing-Driven Transistor-Level Placement Beyond Standard-Cell Boundaries for DTCOKeyu Peng, Yinuo Wu, Zhengzhe Zheng, Hao Gu, Ziran Zhu, Chao Wang 0068, Jun Yang 0006. 1-9 [doi]
• Invited Paper: Unitho: A Unified Multi-Task Framework for Computational LithographyQian Jin, Yumeng Liu, Yuqi Jiang, Qi Sun 0002, Cheng Zhuo. 1-9 [doi]
• SetupKit: Efficient Multi-Corner Setup/Hold Time Characterization Using Bias-Enhanced Interpolation and Active LearningJunzhuo Zhou, Ziwen Wang, Haoxuan Xia, Yuxin Yan, Chengyu Zhu, Ting-Jung Lin, Wei W. Xing, Lei He 0001. 1-8 [doi]
• K-PACT: Kernel Planning for Adaptive Context Switching - A Framework for Clustering, Placement, and Prefetching in Spectrum SensingHasan Umut Suluhan, Jiahao Lin, Serhan Gener, Chaitali Chakrabarti, Ümit Y. Ogras, Ali Akoglu. 1-9 [doi]
• HIPPO: A Hierarchy-Preserving and Noise-Tolerant Pre-HLS Power Modeling Framework for FPGAZefan Lin, Zedong Peng, Mingzhe Gao, Jieru Zhao, Zhe Lin 0007. 1-9 [doi]
• Ultra Energy-Efficient Butterfly Counting in Bipartite Networks via Algorithm-Architecture Co-OptimizationHaiyang Liu, Xueyan Wang, Jianlei Yang 0001, Xiaotao Jia, Gang Qu 0001, Weisheng Zhao. 1-9 [doi]
• Invited Paper: Security Under the Lens: Vulnerabilities in In-Sensor Computing SystemsMashrafi Alam Kajol, Wei Lu, Qiaoyan Yu. 1-7 [doi]
• MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMsChenchen Zhao 0001, Zhengyuan Shi, Xiangyu Wen, Chengjie Liu, Yi Liu 0081, Yunhao Zhou, Yuxiang Zhao, Hefei Feng, Yinan Zhu, Gwok-Waa Wan, Xin Cheng, Weiyu Chen, Yongqi Fu, Chujie Chen, Chenhao Xue, Ying Wang 0001, Yibo Lin, Jun Yang 0006, Ning Xu 0009, Xi Wang, Qiang Xu 0001. 1-9 [doi]
• PCBFormer: Understanding 3D Structure of RealWorld PCB Traces for S-Parameter PredictionTaejin Paik, Jaemin Park, Taehee Kim, Daniel Hyunsuk Jung, Doyun Kim. 1-8 [doi]
• SiGNoR: Similarity-based Graph Partitioning and Node Reuse for Memory Efficient GNN AccelerationSeung-Eon Hwang 0001, Hyeon Gwon Kim, Dongwoo Lew, Jongsun Park 0001. 1-9 [doi]
• GROOT: Graph Edge Re-growth and Partitioning for the Verification of Large Designs in Logic SynthesisKiran Thorat, Hongwu Peng, Yuebo Luo, Xi Xie, Shaoyi Huang, Amit Hasan 0001, Jiahui Zhao, Yingjie Li, Zhijie Shi, Cunxi Yu, Caiwen Ding. 1-9 [doi]
• DiffCCD: Differentiable Concurrent Clock and Data OptimizationYuhao Ji, Yuntao Lu, Zuodong Zhang, Zizheng Guo 0001, Yibo Lin, Bei Yu 0001. 1-9 [doi]
• FPGA-CC: Confidential Containers for Virtualized FPGAsKe Xia, Sheng Wei 0001. 1-9 [doi]
• From Concept to Practice: an Automated LLM-aided UVM Machine for RTL VerificationJunhao Ye, Yuchen Hu, Ke Xu, Dingrong Pan, Qichun Chen, Jie Zhou 0001, Shuai Zhao 0004, Xinwei Fang, Xi Wang 0009, Nan Guan, Zhe Jiang 0004. 1-9 [doi]
• VLSI Design and Experimental Demonstration of Photonic Interposers in Thin-Film Lithium NiobateGeorgios Kyriazidis, Aristotelis Tsekouras, John Davis, Vasilis F. Pavlidis, Gage Hills. 1-9 [doi]
• LLM-Augmented Multi-Modal Fusion for SoC Design Space ExplorationDonger Luo, Tianyi Li, Xinheng Li, Qi Sun 0002, Cheng Zhuo, Bei Yu 0001, Jingyi Yu 0002, Hao Geng. 1-8 [doi]
• SLTarch: Towards Scalable Point-Based Neural Rendering by Taming Workload Imbalance and Memory IrregularityXingyang Li, Jie Jiang, Yu Feng 0007, Yiming Gan, Jieru Zhao, Zihan Liu 0002, Jingwen Leng, Minyi Guo. 1-9 [doi]
• RePM: Reconfigurable Elastic Computing for Polynomial Multiplier with Hybrid NTT AlgorithmSizhao Li, Chenyu Zhai, Xinhua Wang, Zhujun Guo, Shan He 0003, Donghui Guo. 1-9 [doi]
• GauPRE: A Pattern-based Rendering Engine for Gaussian Splatting on Edge DeviceYuzheng Lin, Lizhou Wu, Chixiao Chen, Xiaoyang Zeng, Haozhe Zhu. 1-9 [doi]
• Row-Column Hybrid Grouping for Fault-Resilient Multi-Bit Weight Representation on IMC ArraysKang Eun Jeon, Sangheum Yeon, Jinhee Kim, Hyeonsu Bang, Johnny Rhe, Jong Hwan Ko. 1-9 [doi]
• SAGE: Saliency-Aware Grouping for Efficient Mapping of LLMs on Analog Compute-in-MemoryYayue Hou, Zhenyu Liu, Garrett Gagnon, Hsinyu Tsai, Kaoutar El Maghraoui, Geoffrey W. Burr, Liu Liu 0017. 1-9 [doi]
• GenomeDPU: A Cost-Effective In-Memory Data Processing Unit for GPU-based Genome AnalysisShouzhe Zhang, Zhuren Liu, Ruixiao Huang, Hui Zhao. 1-9 [doi]
• Automatic Design for Modular Microfluidic Routing BlocksPhilipp Ebner, Maria Emmerich, Eric Safai, Aniruddha Paul, Mathieu Odijk, Joshua Loessberg-Zahl, Robert Wille. 1-7 [doi]
• DeepCell: Self-Supervised Multiview Fusion for Circuit Representation LearningZhengyuan Shi, Chengyu Ma, Ziyang Zheng, Lingfeng Zhou, Hongyang Pan, Wentao Jiang, Fan Yang 0001, Xiaoyan Yang, Zhufei Chu, Qiang Xu 0001. 1-9 [doi]
• Parallel Non-Integer Multiple-Cell-Height Node RemappingZong-Han Wu, Bo-Ying Huang, Yu-Chen Chen, Yao-Wen Chang. 1-9 [doi]
• SiST: Token Similarity and Sparsity Aware Optimization for Transformers on FPGAYifan Zhang, Hongji Wang, Genhao Zhang, Jianli Chen, Jun Yu 0010, Kun Wang 0005. 1-9 [doi]
• Network and Compiler Optimizations for Efficient Linear Algebra Kernels in Private Transformer Inference (Invited Paper)Karthik Garimella, Negar Neda, Austin Ebel, Nandan Kumar Jha, Brandon Reagen. 1-10 [doi]
• Leaks beyond Bits: Deep Learning-Assisted Side-Channel Attacks on Hyperdimensional Computing AcceleratorsBrojogopal Sapui, Mehdi B. Tahoori. 1-9 [doi]
• MF-MOR: Multi-Fidelity Model Order Reduction for Many-Port Linear Systems in Chip Power ModelingZhenjie Lu, Hang Zhou, Quan Chen. 1-9 [doi]
• Invited Paper: 2025 ICCAD CAD Contest Problem B: Power and Timing Optimization Using Multibit Flip-FlopSheng-Wei Yang, Jhih-Wei Hsu, Yu-Hsuan Cheng, Cindy Chin-Fang Shen. 1-6 [doi]
• BMCFuzz: Hybrid Verification of Processors by Synergistic Integration of Bound Model Checking and FuzzingShidong Shen, Jinyu Liu, Weizhi Feng, Fu Song, Zhilin Wu. 1-9 [doi]
• SCArmor: Layer-Bit Joint Hardening with a Fast Genetic Optimization for Cost-Efficient and High-Reliable SC-DCNN CircuitsJihe Wang, Yulu Liu, Yubin Zhang, Danghui Wang. 1-9 [doi]
• ISO 26262-Aligned Functional Safety Verification Framework with Explainable Graph Neural NetworkYutao Sun, Jiehua Huang, Xiangping Liao, Zhijun Wang, Liping Liang. 1-9 [doi]
• ThermoPhoton: Fast 3D Thermal Simulation of Photonic Integrated Circuits via Operator LearningWeilong Guan, Li Huang, Yuxuan Lin, Yuchao Wu, Yeyu Tong, Yuzhe Ma. 1-8 [doi]
• JSA-CIM: A Joint-Sparse AdderNet Compute-In-Memory Accelerator for Energy-Efficient Edge AI ApplicationsOmar Al Kailani, Yunxiang Zhang, Wenfeng Zhao. 1-8 [doi]
• When Semi-Supervised LVM Meets Frequency-Based Critical Layout Pattern SelectionLiuke Wang, Shenshuo Yao, Shihan Wang 0007, Zhen Wang, Zicheng Huang, Jingyi Yu 0002, Hao Geng. 1-9 [doi]
• SO3-Cell: Standard Cell Layout Automation Framework for Simultaneous Optimization of Topology, Placement, and RoutingChung-Kuan Cheng, Andrew B. Kahng, Byeonggon Kang, Seokhyeong Kang, Jakang Lee, Bill Lin 0001. 1-9 [doi]
• Designing and Training Neural Networks for Analog In-Sensor Deployment: A Hardware-Aware AnalysisMark Horton, Haoxuan Shan, James Kiessling, Huanrui Yang, Yiran Chen 0001, Hai Helen Li. 1-7 [doi]
• VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMsKimia Tasnia, Alexander Garcia, Tasnuva Farheen, Sazadur Rahman. 1-9 [doi]
• GPU Acceleration for Versatile Buffer InsertionYuan Pu 0001, Yuhao Ji, SiYing Yu, Zuodong Zhang, Zizheng Guo 0001, Zhuolun He, Yibo Lin, David Z. Pan, Bei Yu 0001. 1-9 [doi]
• Invited Paper: Multi-Agent Generative Synthesis for Analog/RF Circuit: from Scalable Topology Generation to Efficient Inverse DesignShikai Wang, Qiufeng Li, Houbo He, Jian Gao, Zining Wang, Yu Sun, Xuan Zhang, Taiyun Chi, Weidong Cao. 1-9 [doi]
• LMLitho: A Large Vision Model-Driven Lithography Simulation FrameworkZhen Wang, Hongquan He, Tao Wu, Xuming He 0001, Qi Sun 0002, Cheng Zhuo, Bei Yu 0001, Jingyi Yu 0002, Hao Geng. 1-9 [doi]
• Accelerating Electro-Thermal Co-Analysis via Coarse-to-Fine Physics-Informed Neural NetworksXiao Dong, Songyu Sun, Xunzhao Yin, Zhou Jin 0001, Zhiguo Shi 0001, Cheng Zhuo. 1-9 [doi]
• Invited Paper: Toward Secure In-Sensor Intelligence: Threats and Defenses in SNNsArchisman Ghosh 0001, Swaroop Ghosh. 1-7 [doi]
• SparCIM: A Heterogeneous CIM-Based Accelerator for Large Language Models with Contextual and Unstructured Bit SparsityXingyu Xu 0008, Yuan Song, Bo Hu, Peng Zheng, Zihan Zou, Xin Si, Bo Liu 0019. 1-9 [doi]
• FRESCO: Efficient Subgraph Enumeration for Scalable Clustering in Heterogeneous CGRAsLouis Coulon, Adham Ragab, Jason Anderson 0001, Mirjana Stojilovic, Paolo Ienne. 1-9 [doi]