Table of Contents

• The In-Car Computing Network: An Embedded Systems ChallengeKarl-Thomas Neumann. 3-3
• Clear and Present Tensions in Microprocessor DesignJohn Paul Shen. 4-4
• Moore s Law Meets Shannon s Law: The Evolution of the Communication s IndustryLee Harrison. 5-8
• MOUSETRAP: Ultra-High-Speed Transition-Signaling Asynchronous PipelinesMontek Singh, Steven M. Nowick. 9-17
• Arithmetic Logic Circuits Using Self-Timed Bit Level Dataflow and Early EvaluationRobert B. Reese, Mitchell A. Thornton, Cherrice Traver. 18-23
• Efficient Systematic Error-correcting Codes for Semi-Delay-Insensitive Data TransmissionFu-Chiung Cheng, Shuen-Long Ho. 24-31
• Minimal Subset Evaluation: Rapid Warm-Up for Simulated Hardware StateJohn W. Haskins Jr., Kevin Skadron. 32-39
• A Framework for Energy Estimation of VLIW ArchitectureHyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. 40-45
• High-Level Power Modeling of CPLDs and FPGAsLi Shang, Niraj K. Jha. 46-53
• Symbolic Cache: Fast Memory Access Based on Program Syntax Correlation of Loads and StoresQianrong Ma, Jih-Kwon Peir, Lu Peng, Konrad Lai. 54-61
• In-Line Interrupt Handling for Software-Managed TLBsAamer Jaleel, Bruce L. Jacob. 62-67
• Design of a Predictive Filter Cache for Energy Savings in High Performance Processor ArchitecturesWeiyu Tang, Rajesh K. Gupta, Alexandru Nicolau. 68-75
• A New Functional Test Program Generation MethodologyFarzan Fallah, Koichiro Takayama. 76-81
• A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based CoverageSerdar Tasiran, Farzan Fallah, David G. Chinnery, Scott J. Weber, Kurt Keutzer. 82-88
• Selecting A Well Distributed Hard Case Test Suite for IEEE Standard Floating Point DivisionLee D. McFearin, David W. Matula. 89-97
• Linear Time Hierarchical Capacitance Extraction without Multipole ExpansionSaisanthosh Balakrishnan, Jong Hyuk Park, Hyungsuk Kim, Yu-Min Lee, Charlie Chung-Ping Chen. 98-103
• Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI CircuitsPayam Heydari, Massoud Pedram. 104-109
• Crosstalk Noise Estimation for Generic RC TreesMasao Takahashi, Masanori Hashimoto, Hidetoshi Onodera. 110-117
• A Banked-Promotion TLB for High Performance and Low PowerJung Hoon Lee, Jang-Soo Lee, Seh-Woong Jeong, Shin-Dug Kim. 118-123
• Filtering Superfluous Prefetches Using Density VectorsWei-Fen Lin, Steven K. Reinhardt, Doug Burger, Thomas R. Puzak. 124-132
• Allocation by Conflict: A Simple Effective Multilateral Cache Management SchemeEdward S. Tam, Stevan A. Vlaovic, Gary S. Tyson, Edward S. Davidson. 133-141
• COREL: A Dynamic Compaction Procedure for Synchronous Sequential Circuits with Repetition and Local Static CompactionIrith Pomeranz, Sudhakar M. Reddy. 142-147
• A Partitioning and Storage Based Built-in Test Pattern Generation Method for Synchronous Sequential CircuitsIrith Pomeranz, Sudhakar M. Reddy. 148-153
• Cost-Effective Non-Scan Design for Testability for Actual Testability ImprovementDong Xiang, Yi Xu. 154-160
• Improved ZDN-arithmetic for Fast Modulo MultiplicationHagen Ploog, Sebastian Flügel, Dirk Timmermann. 166-171
• Design Alternatives for Parallel Saturating Multioperand AddersPablo I. Balzola, Michael J. Schulte, Jie Ruan, C. John Glossner, Erdem Hokenek. 172-177
• A Single-Multiplier Quadratic Interpolator for LNS ArithmeticMark G. Arnold, Mark D. Winkel. 178-185
• Gate Sizing to Eliminate Crosstalk Induced Timing ViolationTong Xiao, Malgorzata Marek-Sadowska. 186-191
• Performance Optimization By Wire and Buffer Sizing Under The Transmission Line ModelTai-Chen Chen, Song-Ra Pan, Yao-Wen Chang. 192-198
• Buffered Interconnect Tree Optimization Using Lagrangian Relaxation and Dynamic ProgrammingShih-Yih Lai, Ross Baldick. 199-207
• Jitter-Induced Power/ground Noise in CMOS PLLs: A Design PerspectivePayam Heydari, Massoud Pedram. 209-213
• On The Micro-architectural Impact of Clock Distribution Using Multiple PLLsMartin Saint-Laurent, Madhavan Swaminathan, James D. Meindl. 214-220
• On-Chip Oscilloscopes for Noninvasive Time-domain Measurement of WaveformsKenneth L. Shepard, Yu Zheng. 221-227
• Selective Branch Prediction Reversal By Correlating with Data Values and Control FlowJuan L. Aragón, José González, José M. García, Antonio González. 228-233
• Mutable Functional Units and Their Applications on MicroprocessorsYan Solihin, Kirk W. Cameron, Yong Luo, Dominique Lavenier, Maya Gokhale. 234-239
• Compiler-Directed Classification of Value Locality BehaviorQing Zhao, David J. Lilja. 240-248
• A Hierarchical Dependence Check and Folded Rename Mapping Based Scalable Dispatch StageVadhiraj Sankaranarayanan, Akhilesh Tyagi. 249-255
• Designing Circuits for Disk DrivesGeorg Pelz. 256-261
• Hard Disk Controller: The Disk Drive s Brain and BodyJames Jeppensen, Walt Allen, Steve Anderson, Michael Pilsl. 262-267
• Motion-Control: The Power Side of Disk DrivesWolfgang Sereinig. 268-275
• Static Energy Reduction Techniques for Microprocessor CachesHeather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger. 276-283
• Parallel CacheletsDeepak Limaye, Ryan Rakvic, John Paul Shen. 284-292
• Access Region Cache: A Multi-Porting Solution for Future Wide-Issue ProcessorsBhooshan S. Thakar, Gyungho Lee. 293-301
• Distributed Event-Driven Simulation of VHDL-SPICE Mixed-Signal CircuitsDragos Lungeanu, C.-J. Richard Shi. 302-307
• High Performance Parallel Fault SimulationAmit K. Varshney, Bapiraju Vinnakota, Eric Skuldt, Brion L. Keller. 308-313
• On-Line Integrity Monitoring of Microprocessor Control LogicSeongwoo Kim, Arun K. Somani. 314-321
• A Timing-Driven Macro-Cell Placement AlgorithmFan Mo, Abdallah Tabbara, Robert K. Brayton. 322-327
• Fixed-outline Floorplanning through Better Local SearchSaurabh N. Adya, Igor L. Markov. 328-334
• Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA PartitioningGuang-Ming Wu, Jai-Ming Lin, Mango Chia-Tso Chao, Yao-Wen Chang. 335-347
• Arithmetic Transforms for Verifying Compositions of Sequential DatapathsKatarzyna Radecka, Zeljko Zilic. 348-353
• Hierarchical Image Computation with Dynamic Conjunction SchedulingChristoph Meinel, Christian Stangier. 354-359
• Introduction to Generalized Symbolic Trajectory EvaluationJin Yang, Carl-Johan H. Seger. 360-367
• BDD Variable Ordering by Scatter SearchWilliam N. N. Hung, Xiaoyu Song. 368-373
• Lower Bound Based DDD Minimization for Efficient Symbolic Circuit AnalysisAlicia Manthe, C.-J. Richard Shi. 374-379
• Run-Time Execution of Reconfigurable Hardware in a Java EnvironmentLaurie A. Smith King, Heather Quinn, Miriam Leeser, Demetris G. Galatopoullos, Elias S. Manolakos. 380-387
• Realization of Multiple-Output Functions by Reconfigurable CascadesYukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura. 388-393
• A Low-Power Cache Design for CalmRISC:::TM:::-Based SystemsSangyeun Cho, Wooyoung Jung, Yongchun Kim, Seh-Woong Jeong. 394-399
• Interconnect-centric Array Architectures for Minimum SRAM Access TimeAzeez J. Bhavnagarwala, Stephen V. Kosonocky, James D. Meindl. 400-405
• Understanding and Addressing the Noise Induced By Electrostatic Discharge in Multiple Power Supply SystemsJaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang. 406-414
• Cost-effective Hardware Acceleration of Multimedia ApplicationsDeependra Talla, Lizy Kurian John. 415-424
• MPEG Macroblock Parsing and Pel Reconstruction On An FPGA-Augmented TriMedia ProcessorMihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers. 425-430
• Low-Energy DSP Code Generation Using a Genetic AlgorithmMarkus Lorenz, Rainer Leupers, Peter Marwedel, Thorsten Dräger, Gerhard Fettweis. 431-437
• Voltage Scaling for Energy Minimization with QoS ConstraintsAli Manzak, Chaitali Chakrabarti. 438-446
• Matching Architecture to Application Via Configurable Processors: A Case Study with Boolean Satisfiability ProblemYing Zhao, Sharad Malik, Albert Wang, Matthew W. Moskewicz, Conor F. Madigan. 447-452
• Architectural Enhancements for Fast Subword Permutations with Repetitions in Cryptographic ApplicationsJohn Patrick McGregor, Ruby B. Lee. 453-461
• 3DCGiRAM: An Intelligent Memory Architecture for Photo-Realistic Image SynthesisHiroaki Kobayashi, Ken-ichi Suzuki, Kentaro Sano, Yoshiyuki Kaeriyama, Yasumasa Saida, Nobuyuki Oba, Tadao Nakamura. 462-467
• Use of Local Memory for Efficient Java ExecutionSamarjeet Singh Tomar, Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. 468-476
• An Analytical Model for Trace Cache Instruction Fetch PerformanceAfzal Hossain, Daniel J. Pease. 477-480
• Performance Driven Global Routing Through Gradual RefinementJiang Hu, Sachin S. Sapatnekar. 481-483
• Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI PlacementSadiq M. Sait, Habib Youssef, Junaid A. Khan, Aiman H. El-Maleh. 484-487
• Fast Specification of Cycle-accurate Processor ModelsFelix Sheng-Ho Chang, Alan J. Hu. 488-492
• A Performance Analysis of the Active Memory SystemWitawas Srisa-an, Chia-Tien Dan Lo, J. Morris Chang. 493-496
• Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power DissipationKent E. Wires, Michael J. Schulte, James E. Stine. 497-500
• An Algorithm for Dynamically Reconfigurable FPGA PlacementGuang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang. 501-504
• RC-in RC-out Model Order Reduction Accurate up to Second Order MomentsPradeepsunder Ganesh, Charlie Chung-Ping Chen. 505-506
• Efficient Function Approximation for Embedded and ASIC ApplicationsJames W. Hauser, Carla Neaderhouser Purdy. 507-510
• An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed ClockingMyoung-Cheol Shin, Se-Hyeon Kang, In-Cheol Park. 511-512
• A Heuristic for Multiple Weight Set GenerationHong Sik Kim, Jin-kyue Lee, Sungho Kang. 513-514
• towards A formal Model of Shared Memory Consistency for Intel Itanium:::TM:::Prosenjit Chatterjee, Ganesh Gopalakrishnan. 515-518
• Efficient Algorithms for Subcircuit Enumeration and Classification for the Module Identification ProblemJennifer L. White, Moon-Jung Chung, Anthony S. Wojcik, Travis E. Doom. 519-522
• MCOMA: A Multithreaded COMA ArchitectureHalima El Naga, Jean-Luc Gaudiot. 523-525
• Automatic Generation and Validation of Memory Test Models for High Performance MicroprocessorsKamran Zarrineh, Thomas A. Ziaja, Amitava Majumdar. 526-529
• Reducing Cache Pollution of Prefetching in a Small Data CachePipat Reungsang, Sun Kyu Park, Seh-Woong Jeong, Hyung-Lae Roh, Gyungho Lee. 530-533
• Alloyed Path-pattern Scheme for Branch PredictionRajesh Ramanujam, Murali Ravirala, Gyungho Lee. 534-537
• Timing Characterization of Dual-edge Triggered Flip-flopsNikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija. 538-541
• Performance Impact of Addressing Modes on Encryption AlgorithmsA. Murat Fiskiran, Ruby B. Lee. 542-545
• Determining Schedules for Reducing Power Consumption Using Multiple Supply VoltagesNoureddine Chabini, El Mostapha Aboulhamid, Yvon Savaria. 546-552
• Pre-routing Estimation of Shielding for RLC Signal IntegrityJames D. Z. Ma, Arvind Parihar, Lei He. 553-556