Table of Contents

• Design issues of a rate 8/10 matched-spectral-null trellis code chip for partial response channelsC. Bernard Shung, Paul H. Siegel, Hemant K. Thapar, Razmik Karabed. [doi]
• BiCMOS design overview and implementation methodologyRamesh S. Iyer. 3-6 [doi]
• Submicron BiCMOS technologies for supercomputer and high speed system implementationB. Bastani, M. Biswal, Ali Iranmanesh, C. Lage, L. Bouknight, V. Ilderem, A. Solheim, W. Burger, R. Lahri, J. Small. 7-10 [doi]
• BiCMOS Futurebus transceiverT. Fletcher, E. Hahn, J. West. 11-13 [doi]
• A strategy for avoiding pipeline interlock delays in a microprocessorToyohiko Yoshida, Masahito Matsuo, Tatsuya Ueda, Yuichi Saito. 14-19 [doi]
• Exploitation of operation-level parallelism in a processor of the CRAY X-MPSriram Vajapeyam, Gurindar S. Sohi, Wei-Chung Hsu. 20-23 [doi]
• A parameter adjustment method for analog circuits based on convex fuzzy decision using constraints of satisfactory levelMasaki Hashizume, Takeomi Tamesada, Koji Nii. 24-28 [doi]
• Automatic layout generation for mixed analog-digital VLSI neural chipsDavid J. Chen, Bing J. Sheu. 29-32 [doi]
• MxSICO: a silicon compiler for mixed analog digital circuitsErtugrul Berkcan. 33-36 [doi]
• A global feedback detection algorithm for VLSI circuitsH.-C. Shih, Predrag G. Kovijanic, Rahul Razdan. 37-40 [doi]
• Fault tolerance in RNS: an efficient approachDamu Radhakrishnan, Taejin Pyon. 41-44 [doi]
• The observability don't-care set and its approximationsPatrick C. McGeer, Robert K. Brayton. 45-48 [doi]
• Figures of merit for system path time estimationC. G. Hsi, Stuart G. Tucker. 49-55 [doi]
• Design for routability of a high-density gate arrayDick W. Harberts, Dré A. J. M. van den Elshout, Harry J. M. Veendrick. 56-59 [doi]
• Concurrent testing of VLSI circuits using conservative logicGnanasekaran Swaminathan, James H. Aylor, Barry W. Johnson. 60-65 [doi]
• Reliability analysis of a computer system for a data collection applicationAndrew L. Reibman. 66-69 [doi]
• Reliable design of multichip nonblocking crossbarsJoydeep Ghosh, Anujan Varma. 70-73 [doi]
• Task assignment by parallel simulated annealingEllen E. Witte, Roger D. Chamberlain, Mark A. Franklin. 74-77 [doi]
• Fast parallel communication on mesh connected machines with low buffer requirementsFillia Makedon, Adonios Simvonis. 78-81 [doi]
• A trace-driven analysis of the 'wrap-around' networkCaroline Benveniste, Yarsun Hsu. 82-85 [doi]
• Vector processor design for parallel DSP systems using hierarchical behavioral description based synthesizerHiroshi Nakada, N. Sakurai, Y. Kanayama, Naohisa Ohta, Kiyoshi Oguri. 86-89 [doi]
• Formal semantics of UDL/I and its applications to CAD/DA toolsHiroto Yasuura, Nagisa Ishiura. 90-94 [doi]
• Rule-based testability rule check programYasushi Koseko, C. Hiramine, Takuji Ogihara, Shinichi Murai. 95-98 [doi]
• Practical design assistance at register transfer level using a data path verifierHiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka. 99-102 [doi]
• Design of robustly testable static CMOS parity trees derived from binary decision diagramsNiraj K. Jha, Carol Q. Tong. 103-106 [doi]
• Test generation in circuits constructed by input decompositionGueesang Lee, Mary Jane Irwin, Robert Michael Owens. 107-111 [doi]
• Design of repairable and fully testable folded PLAsChin-Long Wey, Jyhyeung Ding. 112-115 [doi]
• Synthesis of testable PLAs using adaptive heuristics for efficiencyPradip Bose, Subir Bandyopadhyay, D. Dutta Majumder. 116-120 [doi]
• Real-time computing of optical flow using adaptive VLSI neuroprocessorsWai-Chi Fang, Bing J. Sheu, Ji-chien Lee. 122-125 [doi]
• Parallel digital image restoration using adaptive VLSI neural chipsJi-chien Lee, Bing J. Sheu. 126-129 [doi]
• An analog parallel distributed solution to the shortest path problemScott E. Ritter, K. Soumyanath. 130-134 [doi]
• DEBBIE: a configurable user interface for CAD frameworksMarcus S. Yoo, Arding Hsu. 135-140 [doi]
• ASIC design using the high-level synthesis system CALLAS: a case studyM. Koster, M. Geiger, Peter Duzy. 141-146 [doi]
• A design environment for high performance VLSI signal processingSailesh K. Rao, Mehdi Hatamian, Bryan D. Ackland. 147-152 [doi]
• Compacting randomly generated test setsJames H. Aylor, James P. Cohoon, E. L. Feldhousen, Barry W. Johnson. 153-156 [doi]
• Estimating aliasing in CA and LFSR based signature registersD. Michael Miller, Shujian Zhang, Werner Pries, Robert D. McLeod. 157-160 [doi]
• Built-in self-test with weighted random pattern hardwareFranc Brglez, Clay S. Gloster Jr., Gershon Kedem. 161-166 [doi]
• HAL III: function level hardware logic simulationShigeru Takasaki, Nobuyoshi Nomizu, Yoshihiro Hirabayashi, Hiroshi Ishikura, Masahiro Kurashita, Nobuhiko Koike, Toshiyuki Nakata. 167-170 [doi]
• High speed VLSI logic simulation using bitwise operations and parallel processingYoung-Hyun Jun, Ibrahim N. Hajj, Sang-Heon Lee, Song-Bai Park. 171-174 [doi]
• Automatic classification of node types in switch-level descriptionsDavid T. Blaauw, P. Banerjee, Jacob A. Abraham. 175-178 [doi]
• 68040 memory modules and bus controllerBrad Martin, Steve McMahan, Lal Sood. 179-182 [doi]
• 68040 integer moduleKirk Holden, Renny Eisele, Mike Kobe, James Raleigh, Thomas Spohrer. 183-186 [doi]
• A floating point unit for the 68040Shawn McCloud, Donnie Anderson, Chris DeWitt, Chris Hinds, Ying-wai Ho, Danny Marquette, Eric Quintana. 187-190 [doi]
• Test architecture of the Motorola 68040Thomas Spohrer, Danny Marquette, Michael Gallup. 191-194 [doi]
• An edge based netlist extractor for IC layoutsSandeep Aranake, Anil Dikshit, A. Arun. 195-200 [doi]
• Approximate time-domain models of three-dimensional interconnectsHansruedi Heeb, Albert E. Ruehli. 201-205 [doi]
• Derivation of signal flow direction in MOS VLSI: an alternativeW. De Rammelaere, Ivo Bolsens, Luc J. M. Claesen, Hugo De Man. 206-209 [doi]
• Digital magnetic recording systemsJack Keil Wolf. 210-213 [doi]
• Complexity issues in RAM-DFE design for magnetic disk drivesPhilip S. Bednarz, William L. Abbott, Kevin D. Fisher, John M. Cioffi. 215-219 [doi]
• A parallel algorithm for constructing binary decision diagramsShinji Kimura, Edmund M. Clarke. 220-223 [doi]
• New ideas on symbolic manipulations of finite state machinesChristian Berthet, Olivier Coudert, Jean Christophe Madre. 224-227 [doi]
• Formal verification of cache systems using refinement relationsPaul Loewenstein, David L. Dill. 228-233 [doi]
• Modular BIST concept for microprocessorsHartmut C. Ritter, Thomas M. Schwair. 234-237 [doi]
• VLSI asynchronous sequential circuit designSuresh K. Gopalakrishnan, Gary K. Maki. 238-242 [doi]
• A functional diagnostics methodologyRamachandra P. Kunda, Bharat Deep Rathi. 243-246 [doi]
• Architectures for pipelined Wallace tree multiplier-accumulatorsKing Fai Pang. 247-250 [doi]
• A class of close-to-optimum adder trees allowing regular and compact layoutZhi-Jian Mou, Francis Jutand. 251-254 [doi]
• A reduced area scheme for carry-select addersAkhilesh Tyagi. 255-258 [doi]
• 2.5 Gbits/sec telecommunications gate arrayN. Hendrickson, R. Langer, T. Coe, M. Vana, I. Deyhimy. 259-262 [doi]
• An approach to 150 K gate low power ECL cell based integrated circuitsG. Taylor, G. Sanguinetti, R. Lane. 263-268 [doi]
• Design and application trade-offs between high-density and high-speed ASICsPatrick Lampin, J. C. Le Garrec, C. Marion, J. P. Mifsud, T. Mille, S. Nicot, B. Rousseau, R. Saura, T. Tatry, C. J. Glossner, R. D. Kilmoyer. 269-272 [doi]
• Testability driven synthesis of interacting finite state machinesPranav Ashar, Srinivas Devadas, A. Richard Newton. 273-276 [doi]
• Heuristic minimization of Boolean relations using testing techniquesAbhijit Ghosh, Srinivas Devadas, A. Richard Newton. 277-281 [doi]
• SYLON-REDUCE: an MOS network optimization algorithms using permissible functionsJohnson Chan Limqueco, Saburo Muroga. 282-285 [doi]
• Boolean technology mapping for both ECI and CMOS circuits based on permissible functions and binary decision diagramsHitomi Sato, Norikazu Takahashi, Yusuke Matsunaga, Masahiro Fujita. 286-290 [doi]
• Fault grading of large digital systemsDaniel G. Saab, Robert B. Mueller-Thuns, David Blaauw, Joseph T. Rahmeh, Jacob A. Abraham. 290-293 [doi]
• BiCMOS fault models: is stuck-at adequate?Marc E. Levitt, Kaushik Roy, Jacob A. Abraham. 294-297 [doi]
• The fault dropping problem in concurrent event driven simulationSilvano Gai, Pier Luca Montessoro. 298-301 [doi]
• Optimized bit level architectures for IIR filteringO. C. McNally, John V. McCanny, Roger F. Woods. 302-306 [doi]
• Wavefront array processor for video applicationsUlrich Schmidt, Sönke Mehrgardt. 307-310 [doi]
• A 75 MHz CMOS digital convolverP. J. Rose, B. G. Koether. 311-314 [doi]
• SAP: design of a systolic array processor for computation in visionSanjay Nichani, N. Ranganathan. 315-318 [doi]
• Experiments with an efficient heuristic algorithm for local microcode generationM. Mahmood, Farhad Mavaddat, M. I. Elmastry. 319-323 [doi]
• Automatic generation of control circuits in pipelined DSP architecturesChing-Yi Wang, Keshab K. Parhi. 324-327 [doi]
• Combined hardware selection and pipelining in high performance data-path designStefaan Note, Francky Catthoor, Gert Goossens, Hugo De Man. 328-331 [doi]
• A hierarchical floorplanning approachMassoud Pedram, Bryan Preas. 332-338 [doi]
• Pin assignment for improved performance in standard cell designMalgorzata Marek-Sadowska, Shen P. Lin. 339-342 [doi]
• Pseudo pin assignment for single-layer over-the-cell routingHoward H. Chen. 343-346 [doi]
• A 64-bit floating-point processing unit with a horizontal instruction code for parallel operationsAkira Katsuno, Hiromasa Takahashi, Hajime Kubosawa, Tomio Sato, Atsuhiro Suga, Gensuke Goto. 347-350 [doi]
• Application specific microprocessor [NS3200/EP family]Gideon D. Intrater, Dan Biran. 351-354 [doi]
• A pipelined microprocessor for logic programming languagesHiroshi Nakashima, Yasutaka Takeda, Katsuto Nakajima, Hideki Andou, Kiyohiro Furutani. 355-359 [doi]
• Minimization of multioutput TANT networks for unlimited fan-in network modelMarek A. Perkowski, Malgorzata Chrzanowska-Jeske, Tuhar Shah. 360-363 [doi]
• Logic synthesis for programmable logic devicesTing Ting Hwang, Robert Michael Owens, Mary Jane Irwin. 364-367 [doi]
• On the estimation of logic complexity for design automation applicationsDevadas Varma, E. A. Trachtenberg. 368-371 [doi]
• An improved algorithm for the minimization of mixed polarity Reed-Muller representationsJ. M. Saul. 372-375 [doi]
• An area-efficient reconfigurable binary tree architectureChung-Han Chen, Nian-Feng Tzeng. 376-379 [doi]
• Empirical evaluation of randomly-wire multistage networksTom Leighton, Derek Linsinski, Bruce M. Maggs. 380-385 [doi]
• Design aids and test results for laser-programmable logic arraysDavid L. Allen, Richard Goldenberg. 386-390 [doi]
• Preliminary description of Tabula Rasa, an electrically reconfigurable hardware engineDwight D. Hill, Daniel R. Cassiday. 391-395 [doi]
• Multiterminal-net routing by grid stretchingTeofilo F. Gonzalez, Si-Qing Zheng. 396-399 [doi]
• An efficient parallel algorithm for channel routingSridhar Krishnamurthy, Joseph JáJá. 400-403 [doi]
• The complexity of adaptive annealingRalph H. J. M. Otten, Lukas P. P. P. van Ginneken. 404-407 [doi]
• Early resolution of address translation in cache designK. Hua, A. Hunt, L. Liu, J.-K. Peir, D. Pruett, J. Temple. 408-412 [doi]
• Cache design for high performance computers with BiCMOS VLSIsM. Morioka, K. Kurita, H. Kobayashi, H. Sawamoto. 413-416 [doi]
• QRAM-Quick access memory systemHideto Niijima, Nobuyuki Oba. 417-420 [doi]
• Associative and data processing Mbit-DRAMOskar Kowarik, Rainer Kraus, Kurt Hoffmann, Karl H. Horninger. 421-424 [doi]
• Computer systems employing reconfigurable board-to-board free-space optical interconnections: COSINE-1 and -2Takao Matsumoto, Toshikazu Sakano, Kazuhiro Noguchi, Tomoko Sawabe. 426-429 [doi]
• Simultaneous bidirectional signalling for IC systemsKevin Lam, Larry R. Dennison, William J. Dally. 430-433 [doi]
• Accurate interconnect modeling for high frequency LSI/VLSI circuits and systemsC. G. Lin-Hendel. 434-442 [doi]
• Towards a VLSI packaging design support environment (PDSE); concepts and implementationJerzy W. Rozenblit, John L. Prince, Olgierd A. Palusinski. 443-448 [doi]
• A linear time algorithm for optimal CMOS functional cell layoutsPo-Yang F. Lin, Kazuo Nakajima. 449-453 [doi]
• Placement algorithms for CMOS cell synthesisDwight D. Hill, Marw A. Aranha, Donald D. Shugard. 454-458 [doi]
• An area estimation technique for module generationArun Rajanala, Akhilesh Tyagi. 459-462 [doi]
• A file-based adaptive prefetch caching designF. Warren Shih, Tze Chiang Lee, Shauchi Ong. 463-466 [doi]
• Design of a custom processing unit based on Intel i486 architectures and performances trade-offsJean-Luc Peter. 467-470 [doi]
• On-the-fly circuit to measure the average working set sizeKwangkeun Yi, Luddy Harrison. 471-474 [doi]