Abstract is missing.
- Imperfection-immune Carbon Nanotube digital VLSINishant Patil, Subhasish Mitra. 1 [doi]
- Computer-aided design for microfluidic chips based on multilayer soft lithography Nada Amin, William Thies, Saman P. Amarasinghe. 2-9 [doi]
- Reincarnate historic systems on FPGA with novel design methodologyNaohiko Shimizu. 10-15 [doi]
- Automatic synthesis of computation interference constraints for relative timing verificationYang Xu, Ken S. Stevens. 16-22 [doi]
- Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variationsRenshen Wang, Takumi Okamoto, Chung-Kuan Cheng. 23-28 [doi]
- Statistical timing analysis based on simulation of lithographic processAswin Sreedhar, Sandip Kundu. 29-34 [doi]
- Compiler-directed leakage reduction in embedded microprocessorsSoumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori. 35-40 [doi]
- Efficient calibration of thermal models based on application behaviorYoungwoo Ahn, Inchoon Yeo, Riccardo Bettati. 41-46 [doi]
- Using checksum to reduce power consumption of display systems for low-motion contentKyungtae Han, Zhen Fang, Paul Diefenbaugh, Richard Forand, Ravi R. Iyer, Donald Newell. 47-53 [doi]
- A disruptive computer design idea: Architectures with repeatable timingStephen A. Edwards, Sungjun Kim, Edward A. Lee, Isaac Liu, Hiren D. Patel, Martin Schoeberl. 54-59 [doi]
- Algorithmic approach to designing an easy-to-program system: Can it lead to a HW-enhanced programmer's workflow add-on?Uzi Vishkin. 60-63 [doi]
- Quality improvement and cost reduction using statistical outlier methodsAmit Nahar, Kenneth M. Butler, John M. Carulli Jr., Charles Weinberger. 64-69 [doi]
- Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCsBrandon Noia, Krishnendu Chakrabarty, Yuan Xie. 70-77 [doi]
- Hierarchical parametric test metrics estimation: A ΣΔ converter BIST case studyMatthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir. 78-83 [doi]
- Design and test strategies for microarchitectural post-fabrication tuningXiaoyao Liang, Benjamin C. Lee, Gu-Yeon Wei, David Brooks. 84-90 [doi]
- Impact analysis of performance faults in modern microprocessorsNaghmeh Karimi, Michail Maniatakos, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris. 91-96 [doi]
- A robust pulsed flip-flop and its use in enhanced scan designRajesh Kumar, Kalyana C. Bollapalli, Rajesh Garg, Tarun Soni, Sunil P. Khatri. 97-102 [doi]
- Enabling resonant clock distribution with scaled on-chip magnetic inductorsSaurabh Sinha, Wei Xu, Jyothi Bhaskarr Velamala, Tawab Dastagir, Bertan Bakkaloglu, Hongbin Yu, Yu Cao. 103-108 [doi]
- A flexible communication scheme for rationally-related clock frequenciesJean-Michel Chabloz, Ahmed Hemani. 109-116 [doi]
- VariPipe: Low-overhead variable-clock synchronous pipelinesNavid Toosizadeh, Safwat G. Zaky, Jianwen Zhu. 117-124 [doi]
- N-way ring and square arbitersMasashi Imai, Tomohiro Yoneda, Takashi Nanya. 125-130 [doi]
- On-chip bidirectional wiring for heavily pipelined systems using network codingKalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri. 131-136 [doi]
- WHOLE: A low energy I-Cache with separate way historyZichao Xie, Dong Tong, Xu Cheng. 137-143 [doi]
- Reducing dynamic power dissipation in pipelined forwarding enginesWeirong Jiang, Viktor K. Prasanna. 144-149 [doi]
- A power-aware hybrid RAM-CAM renaming mechanism for fast recoverySalvador Petit, Rafael Ubal, Julio Sahuquillo, Pedro López. 150-157 [doi]
- Resource sharing of pipelined custom hardware extension for energy-efficient application-specific instruction set processor designHai Lin 0004, Yunsi Fei. 158-165 [doi]
- Deterministic clock gating to eliminate wasteful activity due to wrong-path instructions in out-of-order superscalar processorsNasir Mohyuddin, Kimish Patel, Massoud Pedram. 166-172 [doi]
- Real-time, unobtrusive, and efficient program execution tracing with stream caches and last stream predictorsVladimir Uzelac, Aleksandar Milenkovic, Milena Milenkovic, Martin Burtscher. 173-178 [doi]
- A distributed concurrent on-line test scheduling protocol for many-core NoC-based systemsJason D. Lee, Rabi N. Mahapatra, Praveen Bhojwani. 179-185 [doi]
- Transaction-based debugging of system-on-chips with patternsAmir Masoud Gharehbaghi, Masahiro Fujita. 186-192 [doi]
- A new verification method for embedded systemsRobert A. Thacker, Chris J. Myers, Kevin R. Jones, Scott Little. 193-200 [doi]
- A hierarchical approach towards system level static timing verification of SoCsRupsa Chakraborty, Dipanwita Roy Chowdhury. 201-206 [doi]
- Timing variation-aware high-level synthesis considering accurate yield computationJongyoon Jung, Taewhan Kim. 207-212 [doi]
- Fault-tolerant synthesis using non-uniform redundancyKeven L. Woo, Matthew R. Guthaus. 213-218 [doi]
- Low-overhead error detection for Networks-on-ChipAmit Berman, Idit Keidar. 219-224 [doi]
- 3D stacked power distribution considering substrate couplingAmirali Shayan Arani, Xiang Hu, Wanping Zhang, Chung-Kuan Cheng, A. Ege Engin, Xiaoming Chen, Mikhail Popovich. 225-230 [doi]
- Interconnect performance corners considering crosstalk noiseRavikishore Gandikota, David Blaauw, Dennis Sylvester. 231-237 [doi]
- Reducing register file size through instruction pre-execution enhanced by value predictionYusuke Tanaka, Hideki Ando. 238-245 [doi]
- Reusing cached schedules in an out-of-order processor with in-order issue logicOscar Palomar, Toni Juan, Juan J. Navarro. 246-253 [doi]
- 3D GPU architecture using cache stacking: Performance, cost, power and thermal analysisAhmed Al-Maashri, Guangyu Sun, Xiangyu Dong, Vijay Narayanan, Yuan Xie. 254-259 [doi]
- Extending data prefetching to cope with context switch missesHanyu Cui, Suleyman Sair. 260-267 [doi]
- The salvage cache: A fault-tolerant cache architecture for next-generation memory technologiesCheng-Kok Koh, Weng-Fai Wong, Yiran Chen, Hai Li. 268-274 [doi]
- LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessorsJavier Lira, Carlos Molina, Antonio González. 275-281 [doi]
- Avoiding cache thrashing due to private data placement in last-level cache for manycore scalingJiayuan Meng, Kevin Skadron. 282-288 [doi]
- SHIELDSTRAP: Making secure processors truly secureSiddhartha Chhabra, Brian Rogers, Yan Solihin. 289-296 [doi]
- Rapid early-stage microarchitecture design using predictive modelsChristophe Dubach, Timothy M. Jones, Michael F. P. O'Boyle. 297-304 [doi]
- Efficient binary translation system with low hardware costWeiwu Hu, Qi Liu, Jian Wang, Songsong Cai, Menghao Su, Xiaoyu Li. 305-312 [doi]
- Defect-based test optimization for analog/RF circuits for near-zero DPPM applicationsEnder Yilmaz, Sule Ozev. 313-318 [doi]
- Iterative built-in testing and tuning of mixed-signal/RF systemsAbhijit Chatterjee, Donghoon Han, Vishwanath Natarajan, Shyam Kumar Devarakond, Shreyas Sen, Hyun Woo Choi, Rajarajan Senguttuvan, Soumendu Bhattacharya, Abhilash Goyal, Deuk Lee, Madhavan Swaminathan. 319-326 [doi]
- Testing bio-chipsKrishnendu Chakrabarty. 327 [doi]
- Framework for massively parallel testing at wafer and package testA. Hakan Baba, Kee Sup Kim. 328-334 [doi]
- Online multiple error detection in crossbar nano-architecturesNavid Farazmand, Mehdi Baradaran Tahoori. 335-342 [doi]
- Adaptive online testing for efficient hard fault detectionShantanu Gupta, Amin Ansari, Shuguang Feng, Scott A. Mahlke. 343-349 [doi]
- FinFET-based dynamic power management of on-chip interconnection networks through adaptive back-gate biasingChun-Yi Lee, Niraj K. Jha. 350-357 [doi]
- Analysis and optimization of pausible clocking based GALS designXin Fan, Milos Krstic, Eckhard Grass. 358-365 [doi]
- Reliable cache design with detection of gate oxide breakdown using BISTFahad Ahmed, Linda S. Milor. 366-371 [doi]
- Efficient architectures for elliptic curve cryptography processors for RFIDLawrence Leinweber, Christos A. Papachristou, Francis G. Wolff. 372-377 [doi]
- Multiplier-less and table-less linear approximation for square and square-rootIn-Cheol Park, Tae-Hwan Kim. 378-383 [doi]
- On improving the algorithmic robustness of a low-power FIR filterSourabh Khire, Saibal Mukhopadhyay. 384-389 [doi]
- Pragmatic design of gated-diode FinFET DRAMsAjay N. Bhoj, Niraj K. Jha. 390-397 [doi]
- Empirical performance models for 3T1D memoriesKristen Lovin, Benjamin C. Lee, Xiaoyao Liang, David Brooks, Gu-Yeon Wei. 398-403 [doi]
- ColSpace: Towards algorithm/implementation co-optimizationJiawei Huang, John Lach. 404-411 [doi]
- A novel SoC architecture on FPGA for ultra fast face detectionChun He, Alexandros Papakonstantinou, Deming Chen. 412-418 [doi]
- Accelerating mobile augmented reality on a handheld platformSeung Eun Lee, Yong Zhang, Zhen Fang, Sadagopan Srinivasan, Ravi Iyer, Donald Newell. 419-426 [doi]
- Optical lithography simulation using wavelet transformRance Rodrigues, Aswin Sreedhar, Sandip Kundu. 427-432 [doi]
- Computational bit-width allocation for operations in vector calculusAdam B. Kinsman, Nicola Nicolici. 433-438 [doi]
- Topology-driven cell layout migration with collinear constraintsDe-Shiun Fu, Ying-Zhih Chaung, Yen-Hung Lin, Yih-Lang Li. 439-444 [doi]
- A fast routability- and performance-driven droplet routing algorithm for digital microfluidic biochipsTsung-Wei Huang, Tsung-Yi Ho. 445-450 [doi]
- Accurate estimation of vector dependent leakage power in the presence of process variationsRomana Fernandes, Ranga Vemuri. 451-458 [doi]
- Code density concerns for new architecturesVincent M. Weaver, Sally A. McKee. 459-464 [doi]
- Performance analysis of decimal floating-point libraries and its impact on decimal hardware and software solutionsMichael J. Anderson, Chuck Tsen, Liang-Kai Wang, Katherine Compton, Michael J. Schulte. 465-471 [doi]
- The impact of liquid cooling on 3D multi-core processorsHyung Beom Jang, Ikroh Yoon, Cheol Hong Kim, Seungwon Shin, Sung Woo Chung. 472-478 [doi]
- Intra-vector SIMD instructions for core specializationCor Meenderinck, Ben H. H. Juurlink. 479-484 [doi]
- A high throughput FFT processor with no multipliersShakeel S. Abdulla, Haewoon Nam, Mark McDermot, Jacob A. Abraham. 485-490 [doi]
- Panoptic DVS: A fine-grained dynamic voltage scaling framework for energy scalable CMOS designMateja Putic, Liang Di, Benton H. Calhoun, John Lach. 491-497 [doi]
- 3D simulation and analysis of the radiation tolerance of voltage scaled digital circuitRajesh Garg, Sunil P. Khatri. 498-504 [doi]
- A radiation tolerant Phase Locked Loop design for digital electronicsRajesh Kumar, Vinay Karkala, Rajesh Garg, Tanuj Jindal, Sunil P. Khatri. 505-510 [doi]
- A PLL design based on a standing wave resonant oscillatorVinay Karkala, Kalyana C. Bollapalli, Rajesh Garg, Sunil P. Khatri. 511-516 [doi]
- Mid-range wireless energy transfer using inductive resonance for wireless sensorsShahrzad Jalali Mazlouman, Alireza Mahanfar, Bozena Kaminska. 517-522 [doi]
- A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processesSatyanand Nalam, Mudit Bhargava, Kyle Ringgenberg, Ken Mai, Benton H. Calhoun. 523-528 [doi]