Table of Contents

• Welcome to ICCD 2011!Georgi Gaydadjiev, Sofiène Tahar, Greg Byrd, Klaus Schneider. [doi]
• Memory coherence in the age of multicoresMieszko Lis, Keun Sup Shim, Myong Hyon Cho, Srinivas Devadas. 1-8 [doi]
• The convergence of HPC and embedded systems in our heterogeneous computing futureDavid R. Kaeli, David Akodes. 9-11 [doi]
• A GALS Network-on-Chip based on rationally-related frequenciesJean-Michel Chabloz, Ahmed Hemani. 12-18 [doi]
• EM and circuit co-simulation of a reconfigurable hybrid wireless NoC on 2D ICsAnkit More, Baris Taskin. 19-24 [doi]
• Leveraging torus topology with deadlock recovery for cost-efficient on-chip networkMinjeong Shin, John Kim. 25-30 [doi]
• A dynamic and distributed TDM slot-scheduling protocol for QoS-oriented Networks-on-ChipNicola Concer, Andrea Vesco, Riccardo Scopigno, Luca P. Carloni. 31-38 [doi]
• DPPC: Dynamic power partitioning and capping in chip multiprocessorsKai Ma, Xiaorui Wang, Yefu Wang. 39-44 [doi]
• A machine learning approach to modeling power and performance of chip multiprocessorsChangshu Zhang, Arun Ravindran, Kushal Datta, Arindam Mukherjee, Bharat Joshi. 45-50 [doi]
• Using content-aware bitcells to reduce static energy dissipationFahrettin Koc, Osman Seckin Simsek, Oguz Ergin. 51-56 [doi]
• Tree structured analysis on GPU power studyJianmin Chen, Bin Li, Ying Zhang, Lu Peng, Jih-Kwon Peir. 57-64 [doi]
• Pre-assignment RDL routing via extraction of maximal net sequenceJin-Tai Yan, Zhi-Wei Chen. 65-70 [doi]
• Path aware event scheduler in HoldAdvisor for fixing min timing violationsTong Xiao, Harshinder Bagga, George J. Chen, Richard Cheung, Raghu Pattipati. 71-77 [doi]
• A tool set for the design of asynchronous circuits with bundled-data implementationMinoru Iizuka, Naohiro Hamada, Hiroshi Saito, Ryoichi Yamaguchi, Minoru Yoshinaga. 78-83 [doi]
• Applying verification intention for design customization via property mining under constrained testbenchesChih-Neng Chung, Chia-Wei Chang, Kai-Hui Chang, Sy-Yen Kuo. 84-89 [doi]
• Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded coresDean L. Lewis, Shreepad Panth, Xin Zhao, Sung Kyu Lim, Hsien-Hsin S. Lee. 90-95 [doi]
• Reduced complexity test generation algorithms for transition fault diagnosisYu Zhang, Vishwani D. Agrawal. 96-101 [doi]
• Enhanced symbolic simulation of a round-robin arbiterYongjian Li, Naiju Zeng, William N. N. Hung, Xiaoyu Song. 102-107 [doi]
• Using analog circuit behavior to generate SystemC events for an acceleration of mixed-signal simulationStefan Hoelldampf, Daniel Zaum, Markus Olbrich, Erich Barke. 108-112 [doi]
• An optimized scaled neural branch predictorDaniel A. Jimenez. 113-118 [doi]
• TAP prediction: Reusing conditional branch predictor for indirect branches with Target Address PointersZichao Xie, Dong Tong, Mingkai Huang, Xiaoyin Wang, Qinqing Shi, Xu Cheng. 119-126 [doi]
• Simultaneous continual flow pipeline architectureKomal Jothi, Mageda Sharafeddine, Haitham Akkary. 127-134 [doi]
• Thread-aware dynamic shared cache compression in multi-core processorsYuejian Xie, Gabriel H. Loh. 135-141 [doi]
• Memristor-based IMPLY logic design procedureShahar Kvatinsky, Avinoam Kolodny, Uri C. Weiser, Eby G. Friedman. 142-147 [doi]
• A memristor-based memory cell using ambipolar operationPilin Junsangsri, Fabrizio Lombardi. 148-153 [doi]
• Using stochastic computing to implement digital image processing algorithmsPeng Li, David J. Lilja. 154-161 [doi]
• A simple pipelined squaring circuit for DSPVladimir Risojevic, Aleksej Avramovic, Zdenka Babic, Patricio Bulic. 162-167 [doi]
• AURA: An application and user interaction aware middleware framework for energy optimization in mobile devicesBrad K. Donohoo, Chris Ohlsen, Sudeep Pasricha. 168-174 [doi]
• Energy-efficient multi-level cell phase-change memory system with data encodingJue Wang, Xiangyu Dong, Guangyu Sun, Dimin Niu, Yuan Xie. 175-182 [doi]
• Distributed thermal management for embedded heterogeneous MPSoCs with dedicated hardware acceleratorsYen-Kuan Wu, Shervin Sharifi, Tajana Simunic Rosing. 183-189 [doi]
• Energy-aware Standby-Sparing Technique for periodic real-time applicationsMohammad A. Haque, Hakan Aydin, Dakai Zhu. 190-197 [doi]
• A queueing theoretic approach for performance evaluation of low-power multi-core embedded systemsArslan Munir, Ann Gordon-Ross, Sanjay Ranka. 198-205 [doi]
• A study on relating redundancy removal in classical circuits to reversible mappingSayeeda Sultana, Katarzyna Radecka, Yu Pang. 206-211 [doi]
• Positive Davio-based synthesis algorithm for reversible logicYu Pang, Shaoquan Wang, Zhilong He, Jinzhao Lin, Sayeeda Sultana, Katarzyna Radecka. 212-218 [doi]
• Special-purposed VLIW architecture for IEEE-754 quadruple precision elementary functions on FPGAYuanwu Lei, Yong Dou, Li Shen, Jie Zhou, Song Guo. 219-225 [doi]
• Fast and compact binary-to-BCD conversion circuits for decimal multiplicationOsama Al-Khaleel, Zakaria Al-Qudah, Mohammad Al-Khaleel, Christos A. Papachristou, Francis G. Wolff. 226-231 [doi]
• RoShaQ: High-performance on-chip router with shared queuesAnh Thien Tran, Bevan M. Baas. 232-238 [doi]
• Hybrid system level power consumption estimation for FPGA-based MPSoCSanthosh Kumar Rethinagiri, Rabie Ben Atitallah, Smaïl Niar, Eric Senn, Jean-Luc Dekeyser. 239-246 [doi]
• Video quality-driven buffer dimensioning in MPSoC platforms via prioritized frame dropsDeepak Gangadharan, Haiyang Ma, Samarjit Chakraborty, Roger Zimmermann. 247-252 [doi]
• Techniques for LI-BDN synthesis for hybrid microarchitectural simulationTyler S. Harris, Zhuo Ruan, David A. Penry. 253-260 [doi]
• Runtime adaptable concurrent error detection for linear digital systemsYu Liu, Kaijie Wu. 261-266 [doi]
• A novel shared-buffer router for network-on-chip based on Hierarchical Bit-line BufferWei Shi, Weixia Xu, Hongguang Ren, Qiang Dou, Zhiying Wang, Li Shen, Cong Liu. 267-272 [doi]
• ROA-brick topology for rotary resonant clocksYing Teng, Jianchao Lu, Baris Taskin. 273-278 [doi]
• Impact and optimization of lithography-aware regular layout in digital circuit designVinícius Dal Bem, Paulo F. Butzen, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas. 279-284 [doi]
• Blue team red team approach to hardware trust assessmentJeyavijayan Rajendran, Vinayaka Jyothi, Ramesh Karri. 285-288 [doi]
• Circumventing a ring oscillator approach to FPGA-based hardware Trojan detectionJustin Rilling, David Graziano, Jamin Hitchcock, Tim Meyer, Xinying Wang, Phillip H. Jones, Joseph Zambreno. 289-292 [doi]
• Hardware Trojans: The defense and attack of integrated circuitsTrey Reece, William H. Robinson. 293-296 [doi]
• Sequential hardware Trojan: Side-channel aware design and placementXinmu Wang, Seetharam Narasimhan, Aswin Raghav Krishna, Tatini Mal-Sarkar, Swarup Bhunia. 297-300 [doi]
• Implementing hardware Trojans: Experiences from a hardware Trojan challengeGeorg T. Becker, Ashwin Lakshminarasimhan, Lang Lin, Sudheendra Srivathsa, Vikram B. Suresh, Wayne Burleson. 301-304 [doi]
• Is single-scheme Trojan prevention sufficient?Yier Jin, Yiorgos Makris. 305-308 [doi]
• Red team: Design of intelligent hardware trojans with known defense schemesXuehui Zhang, Nicholas Tuzzio, Mohammad Tehranipoor. 309-312 [doi]
• Evaluation of issue queue delay: Banking tag RAM and identifying correct critical pathKyohei Yamaguchi, Yuya Kora, Hideki Ando. 313-319 [doi]
• Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upsetSheng Lin, Yong-Bin Kim, Fabrizio Lombardi. 320-325 [doi]
• Multi-level wordline driver for low power SRAMs in nano-scale CMOS technologyFarshad Moradi, Georgios Panagopoulos, Georgios Karakonstantis, Dag T. Wisland, Hamid Mahmoodi, Jens Kargaard Madsen, Kaushik Roy. 326-331 [doi]
• Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitorsShrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio. 332-338 [doi]
• Adaptable architectures for distributed visual target trackingDomenic Forte, Ankur Srivastava. 339-345 [doi]
• Improving GPU Robustness by making use of faulty partsArtem Durytskyy, Mohamed Zahran, Ramesh Karri. 346-351 [doi]
• Functional correctness for CMP interconnectsRawan Abdel-Khalek, Ritesh Parikh, Andrew DeOrio, Valeria Bertacco. 352-359 [doi]
• Task model for on-chip communication infrastructure design for multicore systemsBharath Phanibhushana, Kunal P. Ganeshpure, Sandip Kundu. 360-365 [doi]
• Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memoryGuangyu Sun, Eren Kursun, Jude A. Rivers, Yuan Xie. 366-372 [doi]
• A morphable phase change memory architecture considering frequent zero valuesMohammad Arjomand, Amin Jadidi, Ali Shafiee, Hamid Sarbazi-Azad. 373-380 [doi]
• An energy- and performance-aware DRAM cache architecture for hybrid DRAM/PCM main memory systemsHyung Gyu Lee, Seungcheol Baek, Chrysostomos Nicopoulos, Jongman Kim. 381-387 [doi]
• The DIMM tree architecture: A high bandwidth and scalable memory systemKanit Therdsteerasukdi, Gyungsu Byun, Jeremy Ir, Glenn Reinman, Jason Cong, M. Frank Chang. 388-395 [doi]
• CPACT - The conditional parameter adjustment cache tuner for dual-core architecturesMarisha Rawlins, Ann Gordon-Ross. 396-403 [doi]
• SoftBeam: Precise tracking of transient faults and vulnerability analysis at processor design timeMichael Gschwind, Valentina Salapura, Catherine Trammell, Sally A. McKee. 404-410 [doi]
• ARCc: A case for an architecturally redundant cache-coherence architecture for large multicoresOmer Khan, Henry Hoffmann, Mieszko Lis, Farrukh Hijaz, Anant Agarwal, Srinivas Devadas. 411-418 [doi]
• Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessorsPramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson. 419-426 [doi]
• Analysis of on-chip interconnection network interface reliability in multicore systemsYong Zou, Yi Xiang, Sudeep Pasricha. 427-428 [doi]
• AIG rewriting using 5-input cutsNan Li, Elena Dubrova. 429-430 [doi]
• FIMSIM: A fault injection infrastructure for microarchitectural simulatorsGulay Yalcin, Osman S. Unsal, Adrián Cristal, Mateo Valero. 431-432 [doi]
• A reconfigurable fault-tolerant routing algorithm to optimize the network-on-chip performance and latency in presence of intermittent and permanent faultsReyhaneh Jabbarvand Behrouz, Mehdi Modarressi, Hamid Sarbazi-Azad. 433-434 [doi]
• 3D vs. 2D analysis of FinFET logic gates under process variationsSourindra Chaudhuri, Niraj K. Jha. 435-436 [doi]
• Precise exception support for decoupled run-time monitoring architecturesDaniel Y. Deng, G. Edward Suh. 437-438 [doi]
• Analysis of reliability of flip-flops under transistor aging effects in nano-scale CMOS technologyVikram G. Rao, Hamid Mahmoodi. 439-440 [doi]
• Towards a tool for implementing delay-free ECC in embedded memoriesThierry Bonnoit, Michael Nicolaidis, Nacer-Eddine Zergainoh. 441-442 [doi]
• A novel software-based defect-tolerance approach for application-specific embedded systemsDa Cheng, Sandeep K. Gupta. 443-444 [doi]
• Output process of variable bit-rate flows in on-chip networks based on aggregate schedulingFahimeh Jafari, Axel Jantsch, Zhonghai Lu. 445-446 [doi]
• Comparative analysis of copper and CNT interconnects for H-tree clock distributionVish Ganti, Hamid Mahmoodi. 447-448 [doi]
• Energy aware task mapping algorithm for heterogeneous MPSoC based architecturesAmr M. A. Hussien, Ahmed M. Eltawil, Rahul Amin, Jim Martin. 449-450 [doi]
• A novel cryptographic key exchange scheme using resistorsPey-Chang Kent Lin, Alex Ivanov, Bradley Johnson, Sunil P. Khatri. 451-452 [doi]
• Low power, high throughput network-on-chip fabric for 3D multicore processorsVivek S. Nandakumar, Malgorzata Marek-Sadowska. 453-454 [doi]
• Static window addition: A new paradigm for the design of variable latency addersKai Du, Peter J. Varman, Kartik Mohanram. 455-456 [doi]
• Energy-aware and quality-scalable data placement and retrieval for disks in video server environmentsDomenic Forte, Ankur Srivastava. 457-458 [doi]