Abstract is missing.
- Cloud computing: Virtualization and resiliency for data center computingValentina Salapura. 1-2 [doi]
- FlexRAM: Toward an advanced Intelligent Memory system: A retrospective paperJosep Torrellas. 3-4 [doi]
- FlexRAM: Toward an advanced Intelligent Memory systemYi Kang, Wei Huang, Seung-Moon Yoo, Diana Keen, Zhenzhou Ge, Vinh Vi Lam, Pratap Pattnaik, Josep Torrellas. 5-14 [doi]
- Retrospective on "Power-Sensitive Multithreaded Architecture"John S. Seng, Dean M. Tullsen, George Z. N. Cai. 15-16 [doi]
- Power-sensitive multithreaded architectureJohn S. Seng, Dean M. Tullsen, George Z. N. Cai. 17-24 [doi]
- Architectural impact of secure socket layer on Internet servers: A retrospectKrishna Kant, Ravishankar K. Iyer, Prasant Mohapatra. 25-26 [doi]
- Architectural impact of secure socket layer on Internet serversKrishna Kant, Ravishankar K. Iyer, Prasant Mohapatra. 27-34 [doi]
- Exploiting microarchitectural redundancy for defect tolerancePremkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger. 35-42 [doi]
- A retrospective look at xpipes: The exciting ride from a design experience to a design platform for nanoscale networks-on-chipDavide Bertozzi, Luca Benini. 43-44 [doi]
- Xpipes: A latency insensitive parameterized network-on-chip architecture for multi-processor SoCsMatteo Dall'Osso, Gianluca Biccari, Luca Giovannini, Davide Bertozzi, Luca Benini. 45-48 [doi]
- Task model suitable for dynamic load balancing of real-time applications in NoC-based MPSoCsSergio Johann Filho, Alexandra Aguiar, Felipe Gohring de Magalhaes, Oliver B. Longhi, Fabiano Hessel. 49-54 [doi]
- BIXBAR: A low cost solution to support dynamic link reconfiguration in networks on chipPablo Abad, Pablo Prieto, Valentin Puente, José-Ángel Gregorio. 55-60 [doi]
- Exploiting multi-level scratchpad memories for time-predictable multicore computingYu Liu, Wei Zhang 0002. 61-66 [doi]
- SECRET: Selective error correction for refresh energy reduction in DRAMsChung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang. 67-74 [doi]
- DuSCA: A multi-channeling strategy for doubling communication capacity in wireless NoCYi Wang 0007, Dan Zhao, Jian Li. 75-80 [doi]
- Reinforcement learning based dynamic power management with a hybrid power supplySiyu Yue, Di Zhu, Yanzhi Wang, Massoud Pedram. 81-86 [doi]
- A PRET microarchitecture implementation with repeatable timing and competitive performanceIsaac Liu, Jan Reineke, David Broman, Michael Zimmer, Edward A. Lee. 87-93 [doi]
- Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetimeYu Cai, Gulay Yalcin, Onur Mutlu, Erich F. Haratsch, Adrián Cristal, Osman S. Ünsal, Ken Mai. 94-101 [doi]
- A high-performance, low-overhead microarchitecture for secure program executionArun K. Kanuparthi, Ramesh Karri, Gaston Ormazabal, Sateesh Addepalli. 102-107 [doi]
- Robust optimization of a Chip Multiprocessor's performance under power and thermal constraintsMohammad Ghasemazar, Hadi Goudarzi, Massoud Pedram. 108-114 [doi]
- Hierarchical modeling of Phase Change memory for reliable designZihan Xu, Ketul Sutaria, Chengen Yang, Chaitali Chakrabarti, Yu Cao. 115-120 [doi]
- Clock mesh synthesis method using the Earth Mover's Distance under transformationsYing Teng, Baris Taskin. 121-126 [doi]
- Malicious key emission via hardware Trojan against encryption systemDavid Hély, Maurin Augagneur, Yves Clauzel, Jeremy Dubeuf. 127-130 [doi]
- Exposing vulnerabilities of untrusted computing platformsYier Jin, Michail Maniatakos, Yiorgos Makris. 131-134 [doi]
- A physical unclonable function based on setup time violationDavid Hély, Maurin Augagneur, Yves Clauzel, Jeremy Dubeuf. 135-138 [doi]
- Stealth assessment of hardware Trojans in a microcontrollerTrey Reece, Daniel B. Limbrick, Xiaowen Wang, Bradley T. Kiddie, William H. Robinson. 139-142 [doi]
- Design and evaluation of a delay-based FPGA Physically Unclonable FunctionAaron Mills, Sudhanshu Vyas, Michael Patterson, Christopher Sabotta, Phillip H. Jones, Joseph Zambreno. 143-146 [doi]
- Adaptable intrusion detection using partial runtime reconfigurationMehryar Rahmatian, Hessam Kooti, Ian G. Harris, Elaheh Bozorgzadeh. 147-152 [doi]
- Timing aware partitioning for multi-FPGA based logic simulation using top-down selective hierarchy flatteningSubramanian Poothamkurissi Swaminathan, Pey-Chang Kent Lin, Sunil P. Khatri. 153-158 [doi]
- Maximizing crosstalk-induced slowdown during path delay testDibakar Gope, D. M. H. Walker. 159-166 [doi]
- Embedded way prediction for last-level cachesFaissal M. Sleiman, Ronald G. Dreslinski, Thomas F. Wenisch. 167-174 [doi]
- Thermal characterization of cloud workloads on a power-efficient server-on-chipDragomir Milojevic, Sachin Idgunji, Djordje Jevdjic, Emre Özer, Pejman Lotfi-Kamran, Andreas Panteli, Andreas Prodromou, Chrysostomos Nicopoulos, Damien Hardy, Babak Falsafi, Yiannakis Sazeides. 175-182 [doi]
- RFiop: RF-memory path to address on-package I/O pad and memory controller scalabilityMario Donato Marino. 183-188 [doi]
- Design methodology for sample preparation on digital microfluidic biochipsYi-Ling Hsieh, Tsung-Yi Ho, Krishnendu Chakrabarty. 189-194 [doi]
- An efficient arithmetic Sum-of-Product (SOP) based multiplication approach for FIR filters and DFTRajeev Kumar, Ayan Mandal, Sunil P. Khatri. 195-200 [doi]
- Multi-voltage domain clock mesh designCan Sitik, Baris Taskin. 201-206 [doi]
- Acceleration of Monte-Carlo molecular simulations on hybrid computing architecturesClaus Braun, Stefan Holst, Hans-Joachim Wunderlich, Juan Manuel Castillo-Sanchez, Joachim Gross. 207-212 [doi]
- Understanding variance propagation in stochastic computing systemsChengguang Ma, Shun'an Zhong, Hua Dang. 213-218 [doi]
- Parametric throughput analysis of scenario-aware dataflow graphsMorteza Damavandpeyma, Sander Stuijk, Marc Geilen, Twan Basten, Henk Corporaal. 219-226 [doi]
- A polynomial time flow for implementing free-choice Petri-netsPavlos M. Mattheakis, Christos P. Sotiriou, Peter A. Beerel. 227-234 [doi]
- A flexible structure of standard cell and its optimization method for near-threshold voltage operationShinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera. 235-240 [doi]
- WaveSync: A low-latency source synchronous bypass network-on-chip architectureYoon Seok Yang, Reeshav Kumar, Gwan Choi, Paul Gratz. 241-248 [doi]
- HPRA: A pro-active Hotspot-Preventive high-performance routing algorithm for Networks-on-ChipsElena Kakoulli, Vassos Soteriou, Theocharis Theocharides. 249-255 [doi]
- Phase-based passive stereovision systems dedicated to cortical visual stimulatorsFiras Hawi, Mohamad Sawan. 256-262 [doi]
- Interface design for synthesized structural hybrid microarchitectural simulatorsZhuo Ruan, David A. Penry. 263-270 [doi]
- A comparative study of wearout mechanisms in state-of-art microprocessorsChang-Chih Chen, Fahad Ahmed, Linda Milor. 271-276 [doi]
- Mamba: A scalable communication centric multi-threaded processor architectureGregory A. Chadwick, Simon W. Moore. 277-283 [doi]
- Dynamic phase-based tuning for embedded systems using phase distance mappingTosiron Adegbija, Ann Gordon-Ross, Arslan Munir. 284-290 [doi]
- SOLE: Speculative one-cycle load execution with scalability, high-performance and energy-efficiencyZhen-Hao Zhang, Dong Tong, Xiaoyin Wang, Jiangfang Yi, Keyi Wang. 291-296 [doi]
- Analyzing the optimal ratio of SRAM banks in hybrid cachesAlejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato. 297-302 [doi]
- A stochastic reconfigurable architecture for fault-tolerant computation with sequential logicPeng Li, Weikang Qian, David J. Lilja. 303-308 [doi]
- Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETsZoran Jaksic, Ramon Canal. 309-314 [doi]
- A spectral transform approach to stochastic circuitsArmin Alaghi, John P. Hayes. 315-321 [doi]
- Fast error aware model for arithmetic and logic circuitsSamy Zaynoun, Muhammed S. Khairy, Ahmed M. Eltawil, Fadi J. Kurdahi, Amin Khajeh. 322-328 [doi]
- Designing pipelined delay lines with dynamically-adaptive granularity for low-energy applicationsChristos Vezyrtzis, Yannis P. Tsividis, Steven M. Nowick. 329-336 [doi]
- Row buffer locality aware caching policies for hybrid memoriesHanbin Yoon, Justin Meza, Rachata Ausavarungnirun, Rachael Harding, Onur Mutlu. 337-344 [doi]
- Mitigating NBTI in the physical register file through stress predictionSaurabh Kothawade, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy. 345-351 [doi]
- An efficient reliability simulation flow for evaluating the hot carrier injection effect in CMOS VLSI circuitsMehdi Kamal, Qing Xie, Massoud Pedram, Ali Afzali-Kusha, Saeed Safari. 352-357 [doi]
- Memory module-level testing and error behaviors for phase change memoryZhe Zhang, Weijun Xiao, Nohhyun Park, David J. Lilja. 358-363 [doi]
- CoNA: Dynamic application mapping for congestion reduction in many-core systemsMohammad Fattah, Marco Ramírez, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila. 364-370 [doi]
- DIPLOMA: Consistent and coherent shared memory over mobile phonesJason Gao, Anirudh Sivaraman, Niket Agarwal, HaoQi Li, Li-Shiuan Peh. 371-378 [doi]
- Aurora: A thermally resilient photonic network-on-chip architectureAmer Qouneh, Zhongqi Li, Madhura Joshi, Wangyuan Zhang, Xin Fu, Tao Li. 379-386 [doi]
- Improving inclusive cache performance with two-level eviction priorityLingda Li, Dong Tong, Zichao Xie, Junlin Lu, Xu Cheng. 387-392 [doi]
- Fast development of hardware-based run-time monitors through architecture framework and high-level synthesisMohamed Ismail, G. Edward Suh. 393-400 [doi]
- Parameterized free space redistribution for engineering change in placement of integrated circuitsTaraneh Taghavi, Shyam Ramji, Frank Musante, Suhasini Rege. 401-406 [doi]
- Providing cost-effective on-chip network bandwidth in GPGPUsHanjoon Kim, John Kim, Woong Seo, Yeon Gon Cho, Soojung Ryu. 407-412 [doi]
- 3D-NoC: Reconfigurable 3D photonic on-chip interconnect for multicoresRandy Morris, Avinash Karanth Kodi, Ahmed Louri. 413-418 [doi]
- Adaptive Backpressure: Efficient buffer management for on-chip networksDaniel U. Becker, Nan Jiang, George Michelogiannakis, William J. Dally. 419-426 [doi]
- Oblivious routing design for mesh networks to achieve a new worst-case throughput boundGuang Sun, Chia-Wei Chang, Bill Lin, Lieguang Zeng. 427-432 [doi]
- A novel profiled side-channel attack in presence of high Algorithmic NoiseMostafa M. I. Taha, Patrick Schaumont. 433-438 [doi]
- Architecture and design flow for a debug event distribution interconnectArnaldo Azevedo, Bart Vermeulen, Kees Goossens. 439-444 [doi]
- MSE minimization and fault-tolerant data fusion for multi-sensor systemsAtena Roshan Fekr, Majid Janidarmian, Omid Sarbishei, Benjamin Nahill, Katarzyna Radecka, Zeljko Zilic. 445-452 [doi]
- Locating faults in application-dependent interconnects of SRAM based FPGAsT. Nandha Kumar, Haider A. F. Almurib, Fabrizio Lombardi. 453-459 [doi]
- Timing-test scheduling for constraint-graph based post-silicon skew tuningMineo Kaneko. 460-465 [doi]
- Adaptive memory architecture for real-time image warpingAndy Motten, Luc Claesen, Yun Pan. 466-471 [doi]
- A novel variation-tolerant 4T-DRAM cell with enhanced soft-error toleranceShrikanth Ganapathy, Ramon Canal, Dan Alexandrescu, Enrico Costenaro, Antonio González, Antonio Rubio. 472-477 [doi]
- Engineering crossbar based emerging memory technologiesSachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu. 478-479 [doi]
- Protecting pipelined asynchronous communication channels against single event upsetsJakob Lechner, Martin Lampacher. 480-481 [doi]
- Architectural simulations of a fast, source-synchronous ring-based Network-on-Chip designAyan Mandal, Sunil P. Khatri, Rabi N. Mahapatra. 482-483 [doi]
- A case for small row buffers in non-volatile main memoriesJustin Meza, Jing Li, Onur Mutlu. 484-485 [doi]
- Energy modelling of embedded multimedia streaming applications with GStreamer on heterogeneous MPSoCMickael Lanoe, Eric Senn. 486-487 [doi]
- Efficient code compression for coarse grained reconfigurable architecturesMoo-Kyoung Chung, Yeon Gon Cho, Soojung Ryu. 488-489 [doi]
- Integration of correct-by-construction BIP models into the MetroII design space exploration flowAlena Simalatsar, Liangpeng Guo, Marius Bozga, Roberto Passerone. 490-491 [doi]
- The performance of hypermesh NoCs in FPGAsM. Binesh Marvasti, Ted H. Szymanski. 492-493 [doi]
- Distributed thermal-aware task scheduling for 3D Network-on-ChipYingnan Cui, Wei Zhang, Hao Yu. 494-495 [doi]
- System level modeling of real-time embedded softwareRichard Lee, Samar Abdi, Doug Regehr, Frederic Risacher. 496-497 [doi]
- A 3D stacked high performance scalable architecture for 3D Fourier TransformGeorge Razvan Voicu, Marius Enachescu, Sorin Dan Cotofana. 498-499 [doi]
- Design and evaluation of a four-port data cache for high instruction level parallelism reconfigurable processorsKiyeon Lee, Moo-Kyoung Chung, Soojung Ryu, Yeon Gon Cho, Sangyeun Cho. 500-501 [doi]
- Dynamic warp resizing: Analysis and benefits in high-performance SIMTAhmad Lashgar, Amirali Baniasadi, Ahmad Khonsari. 502-503 [doi]
- Post-layout OPE-predicted redundant wire insertion for clock skew minimizationJin-Tai Yan, Zhi-Wei Chen. 504-505 [doi]
- Track assignment considering crosstalk-induced performance degradationQiong Zhao, Jiang Hu. 506-507 [doi]
- DOC: Fast and accurate congestion analysis for global routingYiding Han, Koushik Chakraborty, Sanghamitra Roy. 508-509 [doi]
- Efficient verification of out-of-order behaviors with relaxed scoreboardsLeandro S. Freitas, Gabriel A. G. Andrade, Luiz C. V. dos Santos. 510-511 [doi]
- ECC string: Flexible ECC management for low-cost error protection of L2 cachesJeongkyu Hong, Soontae Kim. 512-513 [doi]
- Non-enumerative generation of statistical path delays for ATPGAhish Mysore Somashekar, Spyros Tragoudas, Sreenivas Gangadhar, Rathish Jayabharathi. 514-515 [doi]
- Modeling economics of LSI design and manufacturing for test design selectionHideyuki Ichihara, Noboru Shimizu, Tsuyoshi Iwagaki, Tomoo Inoue. 516-517 [doi]
- Balancing performance and fault detection for GPGPU workloadsJerry Backer, Ramesh Karri. 518-519 [doi]
- Ring oscillator physical unclonable function with multi level supply voltagesShohreh Sharif Mansouri, Elena Dubrova. 520-521 [doi]
- Automatic assertion extraction in gate-level simulation using GPGPUsShohei Ono, Takeshi Matsumoto, Masahiro Fujita. 522-523 [doi]