Abstract is missing.
- Special Session: ADAPT: ANN-ControlleD System-Level Runtime Adaptable APproximate CompuTingPrattay Chowdhury, Benjamin Carrión Schafer. 1-4 [doi]
- Special Session: How much quality is enough quality? A case for acceptability in approximate designsIsaías B. Felzmann, João Fabrício Filho, Juliane Regina de Oliveira, Lucas Wanner. 5-8 [doi]
- Special Session: When Dataflows Converge: Reconfigurable and Approximate Computing for Emerging Neural NetworksDi Wu 0016, Joshua San Miguel. 9-12 [doi]
- Special Session: Approximate TinyML Systems: Full System Approximations for Extreme Energy-Efficiency in Intelligent Edge DevicesArnab Raha, Soumendu Kumar Ghosh, Debabrata Mohapatra, Deepak A. Mathaikutty, Raymond Sung, Cormac Brick, Vijay Raghunathan. 13-16 [doi]
- Flipping Bits to Share Crossbars in ReRAM-Based DNN AcceleratorLei Zhao, Youtao Zhang, Jun Yang. 17-24 [doi]
- Block-LSM: An Ether-aware Block-ordered LSM-tree based Key-Value Storage EngineZehao Chen, Bingzhe Li, Xiaojun Cai, Zhiping Jia, Zhaoyan Shen, Yi Wang 0003, Zili Shao. 25-32 [doi]
- DynPaC: Coarse-Grained, Dynamic, and Partially Reconfigurable Array for Streaming ApplicationsCheng Tan 0002, Tong Geng, Chenhao Xie 0001, Nicolas Bohm Agostini, Jiajia Li, Ang Li, Kevin J. Barker, Antonino Tumeo. 33-40 [doi]
- NIST-Lite: Randomness Testing of RNGs on an Energy-Constrained PlatformCheng-Yen Lee, Kunal Bharathi, Joellen Lansford, Sunil P. Khatri. 41-48 [doi]
- Seer-SSD: Bridging Semantic Gap between Log-Structured File Systems and SSDs to Reduce SSD Write AmplificationYou Zhou, Ke Wang, Fei Wu 0005, Changsheng Xie, Hao Lv. 49-56 [doi]
- Novel Ultra-Low-Voltage Flip-Flops: Near-Vth Modeling and VLSI IntegrationAnuradha Chathuranga Ranasinghe, Sabih H. Gerez. 57-65 [doi]
- Flexible Instruction Set Architecture for Programmable Look-up Table based Processing-in-MemoryMark Connolly, Purab Ranjan Sutradhar, Mark Indovina, Amlan Ganguly. 66-73 [doi]
- Stochastic Iterative Approximation: Software/hardware techniques for adjusting aggressiveness of approximationTomoki Nakamura, Kazutaka Tomida, Shouta Kouno, Hidetsugu Irie, Shuichi Sakai. 74-82 [doi]
- The Accuracy and Efficiency of Posit ArithmeticStefan Dan Ciocirlan, Dumitrel Loghin, Lavanya Ramapantulu, Nicolae Tapus, Yong Meng Teo. 83-87 [doi]
- Accurate and Fast Performance Modeling of Processors with Decoupled Front-endYuya Degawa, Toru Koizumi 0001, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai. 88-92 [doi]
- AdaptBit-HD: Adaptive Model Bitwidth for Hyperdimensional ComputingJustin Morris, Si Thu Kaung Set, Gadi Rosen, Mohsen Imani, Baris Aksanli, Tajana Rosing. 93-100 [doi]
- MasterMind: Many-Accelerator SoC Architecture for Real-Time Brain-Computer InterfacesGuy Eichler, Luca Piccolboni, Davide Giri, Luca P. Carloni. 101-108 [doi]
- An Efficient Hybrid Parallel Compression Approximate MultiplierShangshang Yao, Liang Zhang, Qiong Wang, Li Shen 0007. 109-116 [doi]
- Run-time Configurable Approximate Multiplier using Significance-Driven Logic CompressionIbrahim Haddadi, Issa Qiqieh, Rishad A. Shafik, Fei Xia, Mohammed A. Noaman Al-Hayanni, Alex Yakovlev. 117-124 [doi]
- A Comprehensive Exploration of the Parallel Prefix Adder Tree SpaceTeodor-Dumitru Ene, James E. Stine. 125-129 [doi]
- CROP: FPGA Implementation of High-Performance Polynomial Multiplication in Saber KEM based on Novel Cyclic-Row Oriented Processing StrategyJiafeng Xie, Pengzhou He, Chiou-Yng Lee. 130-137 [doi]
- Energy-Efficient MAC Units for Fused Posit ArithmeticRaul Murillo 0001, David Mallasén Quintana, Alberto A. Del Barrio, Guillermo Botella. 138-145 [doi]
- NRHI: A Concurrent Non-Rehashing Hash Index for Persistent MemoryXinyu Li, Huimin Cui, Lei Liu. 146-153 [doi]
- HASDH: A Hotspot-Aware and Scalable Dynamic Hashing for Hybrid DRAM-NVM MemoryZhengtao Li, Zhipeng Tan, Jianxi Chen. 154-161 [doi]
- EFM: Elastic Flash Management to Enhance Performance of Hybrid Flash MemoryBingzhe Li, Bo Yuan 0001, David Hung-Chang Du. 162-169 [doi]
- Dynamic File Cache Optimization for Hybrid SSDs with High-Density and Low-Cost Flash MemoryBen Gu, Longfei Luo, Yina Lv, Changlong Li, Liang Shi. 170-173 [doi]
- Consistent RDMA-Friendly Hashing on Remote Persistent MemoryXinxin Liu, Yu Hua 0001, Rong Bai. 174-177 [doi]
- Low-Cost Sequential Logic Circuit Design Considering Single Event Double-Node Upsets and Single Event TransientsRamin Rajaei, Michael T. Niemier, Xiaobo Sharon Hu. 178-185 [doi]
- Rectification of Integer Arithmetic Circuits using Computer Algebra TechniquesVikas Rao, Haden Ondricek, Priyank Kalla, Florian Enescu. 186-195 [doi]
- Differential Testing of x86 Instruction Decoders with Instruction Operand Inferring AlgorithmGuang Wang, Ziyuan Zhu, Shuan Li, Xu Cheng, Dan Meng. 196-203 [doi]
- Comprehensive Failure Analysis against Soft Errors from Hardware and Software PerspectivesYohan Ko, Hwisoo So, Jinhyo Jung, Kyoungwoo Lee, Aviral Shrivastava. 204-207 [doi]
- MetaTableLite: An Efficient Metadata Management Scheme for Tagged-Pointer-Based Spatial SafetyDongwei Chen, Dong Tong 0001, Chun Yang, Xu Cheng 0001. 208-211 [doi]
- HammerFilter: Robust Protection and Low Hardware Overhead Method for RowHammerKwangrae Kim, Jeonghyun Woo, Junsu Kim, Ki-Seok Chung. 212-219 [doi]
- SimiEncode: A Similarity-based Encoding Scheme to Improve Performance and Lifetime of Non-Volatile Main MemorySuzhen Wu, Jiapeng Wu, Zhirong Shen, Zhihao Zhang, Zuocheng Wang, Bo Mao. 220-227 [doi]
- Accelerating Sub-Block Erase in 3D NAND Flash MemoryHongbin Gong, Zhirong Shen, Jiwu Shu. 228-235 [doi]
- Understanding and Optimizing Hybrid SSD with High-Density and Low-Cost Flash MemoryLiang Shi, Longfei Luo, Yina Lv, Shicheng Li, Changlong Li, Edwin Hsing-Mean Sha. 236-243 [doi]
- WAS-Deletion: Workload-Aware Secure Deletion Scheme for Solid-State DrivesBingzhe Li, David H. C. Du. 244-247 [doi]
- Write-Optimized and Consistent RDMA-based Non-Volatile Main Memory SystemsXinxin Liu, Yu Hua 0001, Xuan Li, Qifan Liu. 248-251 [doi]
- An Ultra-efficient Look-up Table based Programmable Processing in Memory Architecture for Data EncryptionPurab Ranjan Sutradhar, Kanad Basu, Sai Manoj Pudukotai Dinakarrao, Amlan Ganguly. 252-259 [doi]
- ReSpar: Reordering Algorithm for ReRAM-based Sparse Matrix-Vector Multiplication AcceleratorYi-Jou Hsiao, Chin-Fu Nien, Hsiang-Yun Cheng. 260-268 [doi]
- Fast and Low-Cost Mitigation of ReRAM Variability for Deep Learning ApplicationsSugil Lee, Mohammed E. Fouda, Jongeun Lee, Ahmed M. Eltawil, Fadi J. Kurdahi. 269-276 [doi]
- WiNN: Wireless Interconnect based Neural Network AcceleratorSiqin Liu, Sushanth Karmunchi, Avinash Karanth, Soumyasanta Laha, Savas Kaya. 277-284 [doi]
- Universal Neural Network Acceleration via Real-Time Loop BlockingJiaqi Zhang 0002, Xiangru Chen, Sandip Ray. 285-289 [doi]
- Exploiting Intra-SM Parallelism in GPUs via Persistent and Elastic BlocksHan Zhao 0005, Weihao Cui, Quan Chen, Jieru Zhao, Jingwen Leng, Minyi Guo. 290-298 [doi]
- Improved GPU Implementations of the Pair-HMM Forward Algorithm for DNA Sequence AlignmentEnliang Li, Subho S. Banerjee, Sitao Huang, Ravishankar K. Iyer, Deming Chen. 299-306 [doi]
- CHARM: Collaborative Host and Accelerator Resource Management for GPU DatacentersWei Zhang, Kaihua Fu, Ningxin Zheng, Quan Chen, Chao Li, Wenli Zheng, Minyi Guo. 307-315 [doi]
- Empirical Guide to Use of Persistent Memory for Large-Scale In-Memory Graph AnalysisHanyeoreum Bae, Miryeong Kwon, Donghyun Gouk, Sanghyun Han, Sungjoon Koh, Changrim Lee, Dongchul Park, Myoungsoo Jung. 316-320 [doi]
- Stochastic-HD: Leveraging Stochastic Computing on Hyper-Dimensional ComputingYilun Hao, Saransh Gupta, Justin Morris, Behnam Khaleghi, Baris Aksanli, Tajana Rosing. 321-325 [doi]
- HyperData: A Data Transfer Accelerator for Software Data Planes Based on Targeted PrefetchingHossein Golestani, Thomas F. Wenisch. 326-334 [doi]
- UH-JLS: A Parallel Ultra-High Throughput JPEG-LS Encoding Architecture for Lossless Image CompressionXuan Wang, Lei Gong, Chao Wang, Xi Li, Xuehai Zhou. 335-343 [doi]
- PRL: Standardizing Performance Monitoring Library for High-Integrity Real-Time SystemsJeremy Giesen, Enrico Mezzetti, Jaume Abella 0001, Francisco J. Cazorla. 344-348 [doi]
- CIDAN: Computing in DRAM with Artificial NeuronsGian Singh, Ankit Wagle, Sarma B. K. Vrudhula, Sunil P. Khatri. 349-356 [doi]
- Resonance-Based Power-Efficient Pulse Generator Design with Corresponding Distribution NetworkKe Jia, Liang Yang, Jian Wang, Bin Lin, Hao Wang, Ruikai Shi. 357-360 [doi]
- Reconfigurable Array for Analog ApplicationsZiyi Chen, Ioannis Savidis. 361-365 [doi]
- CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO AutomationChung-Kuan Cheng, Andrew B. Kahng, Ilgweon Kang, Minsoo Kim, Daeyeal Lee, Bill Lin, Dongwon Park, Mingyu Woo. 366-373 [doi]
- Efficient Table-Based Polynomial on FPGAMarco Barbone, Bas W. Kwaadgras, Uwe Oelfke, Wayne Luk, Georgi Gaydadjiev. 374-382 [doi]
- Legion: Tailoring Grouped Neural Execution Considering Heterogeneity on Multiple Edge DevicesKyunghwan Choi, Seongju Lee, Beom Woo Kang, Yongjun Park. 383-390 [doi]
- Premier: A Concurrency-Aware Pseudo-Partitioning Framework for Shared Last-Level CacheXiaoyang Lu, Rujia Wang, Xian-He Sun. 391-394 [doi]
- Chopin: Composing Cost-Effective Custom Chips with Algorithmic ChipletsPete Ehrett, Todd M. Austin, Valeria Bertacco. 395-399 [doi]
- Compiling and Optimizing Real-world Programs for STRAIGHT ISAToru Koizumi 0001, Shu Sugita, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai. 400-408 [doi]
- GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT ProcessorsNazareno Bruschi, Germain Haugou, Giuseppe Tagliavini, Francesco Conti 0001, Luca Benini, Davide Rossi. 409-416 [doi]
- SME: ReRAM-based Sparse-Multiplication-Engine to Squeeze-Out Bit Sparsity of Neural NetworkFangxin Liu, Wenbo Zhao, Zhezhi He, Zongwu Wang, Yilong Zhao, Tao Yang, Jingnai Feng, Xiaoyao Liang, Li Jiang. 417-424 [doi]
- Improving the Heavy Re-encryption Overhead of Split Counter Mode Encryption for NVMQi Pei, Seunghee Shin. 425-432 [doi]
- Discreet-PARA: Rowhammer Defense with Low Cost and High EfficiencyYicheng Wang, Yang Liu, Peiyun Wu, Zhao Zhang 0010. 433-441 [doi]
- Conciliating Speed and Efficiency on Cache CompressorsDaniel Rodrigues Carvalho, André Seznec. 442-446 [doi]
- POMI: Polling-Based Memory Interface for Hybrid Memory SystemTrung Le, Zhao Zhang, Zhichun Zhu. 447-455 [doi]
- Fault-Aware Prediction-Guided Page Offlining for Uncorrectable Memory Error PreventionXiaoming Du, Cong Li, Shen Zhou, Xian Liu, Xiaohan Xu, Tianjiao Wang, Shijian Ge. 456-463 [doi]
- A High-performance Post-deduplication Delta Compression Scheme for Packed DatasetsYucheng Zhang, Hong Jiang, Mengtian Shi, Chunzhi Wang, Nan Jiang, Xinyun Wu. 464-471 [doi]
- Erasure-Coded Multi-Block Updates Based on Hybrid Writes and Common XORs FirstYujun Liu, Bing Wei, Jigang Wu, Limin Xiao. 472-479 [doi]
- PSACS: Highly-Parallel Shuffle Accelerator on Computational StorageChen Zou, Hui Zhang, Andrew A. Chien, Yang-Seok Ki. 480-487 [doi]
- Intelligent Prediction of Flash Lifetime via Online Domain AdaptationRuixiang Ma, Fei Wu 0005, Changsheng Xie. 488-491 [doi]
- Model Synthesis for Communication Traces of System DesignsHao Zheng, Md Rubel Ahmed, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang. 492-499 [doi]
- T-TSP: Transient-Temperature Based Safe Power Budgeting in Multi-/Many-Core ProcessorsSobhan Niknam, Anuj Pathania, Andy D. Pimentel. 500-508 [doi]
- HosNa: A DPC++ Benchmark Suite for Heterogeneous ArchitecturesNajmeh Nazari Bavarsad, Hosein Mohammadi Makrani, Hossein Sayadi, Lawrence Landis, Setareh Rafatirad, Houman Homayoun. 509-516 [doi]
- Optimal Transistor Placement Combined with Global In-cell Routing in Standard Cell Layout SynthesisKyeongrok Jo, Taewhan Kim. 517-524 [doi]
- 3: Rapid Domain Platform Performance Prediction for Design Space ExplorationJinghan Zhang, Mehrshad Zandigohar, Gunar Schirner. 525-532 [doi]
- Smart-DNN: Efficiently Reducing the Memory Requirements of Running Deep Neural Networks on Resource-constrained PlatformsZhenbo Hu, Xiangyu Zou, Wen Xia, Yuhong Zhao, Weizhe Zhang, Donglei Wu. 533-541 [doi]
- QD-Compressor: a Quantization-based Delta Compression Framework for Deep Neural NetworksShuyu Zhang, Donglei Wu, Haoyu Jin, Xiangyu Zou, Wen Xia, Xiaojia Huang. 542-550 [doi]
- AGQFL: Communication-efficient Federated Learning via Automatic Gradient Quantization in Edge Heterogeneous SystemsZirui Lian, Jing Cao, Yanru Zuo, Weihong Liu, Zongwei Zhu. 551-558 [doi]
- ModelShield: A Generic and Portable Framework Extension for Defending Bit-Flip based Adversarial Weight AttacksYanan Guo, Liang Liu, Yueqiang Cheng, Youtao Zhang, Jun Yang. 559-562 [doi]
- WidePipe: High-Throughput Deep Learning Inference System on a Cluster of Neural Processing UnitsLixian Ma, En Shao, Yueyuan Zhou, Guangming Tan. 563-566 [doi]
- Exploiting Online Locality and Reduction Parallelism for Sampled Dense Matrix Multiplication on GPUsZhongming Yu, Guohao Dai, Guyue Huang, Yu Wang 0002, Huazhong Yang. 567-574 [doi]
- APT: Efficient Side-Channel Analysis Framework against Inner Product Masking SchemeJingdian Ming, Wei Cheng, Yongbin Zhou, Huizhong Li. 575-582 [doi]
- An Efficient Non-Profiled Side-Channel Attack on the CRYSTALS-Dilithium Post-Quantum SignatureZhaohui Chen, Emre Karabulut, Aydin Aysu, Yuan Ma, Jiwu Jing. 583-590 [doi]
- Functional Locking through Omission: From HLS to Obfuscated DesignZi Wang, Shayan Omais Mohammed, Yiorgos Makris, Benjamin Carrión Schafer. 591-598 [doi]
- Security Analysis of State-of-the-art Scan Obfuscation TechniqueYogendra Sao, Sk Subidh Ali. 599-602 [doi]
- QFlow: Quantitative Information Flow for Security-Aware Hardware Design in VerilogLennart M. Reimann, Luca Hanel, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers. 603-607 [doi]
- Efficient Methods for SoC Trust Validation Using Information Flow VerificationKhitam M. Alatoun, Shanmukha Murali Achyutha, Ranga Vemuri. 608-616 [doi]