Table of Contents

• Mapping Multiple LSTM models on FPGAsStefano Ribes, Pedro Trancoso, Ioannis Sourdis, Christos-Savvas Bouganis. 1-9 [doi]
• Beyond Peak Performance: Comparing the Real Performance of AI-Optimized FPGAs and GPUsAndrew Boutros, Eriko Nurvitadhi, Rui Ma, Sergey Gribok, Zhipeng Zhao, James C. Hoe, Vaughn Betz, Martin Langhammer. 10-19 [doi]
• A Reconfigurable Multithreaded Accelerator for Recurrent Neural NetworksZhiqiang Que, Hiroki Nakahara, Hongxiang Fan, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi, Wayne Luk. 20-28 [doi]
• An FPGA Accelerator for Bayesian Network Structure Learning with Iterative Use of Processing ElementsYasuhiro Nitta, Hideki Takase. 29-34 [doi]
• A Low-Cost Reconfigurable Nonlinear Core for Embedded DNN ApplicationsYue Li, Wei Cao 0002, Xuegong Zhou, Lingli Wang. 35-38 [doi]
• Optimizing Fully Spectral Convolutional Neural Networks on FPGAShuanglong Liu, Wayne Luk. 39-47 [doi]
• Memory-Efficient Dataflow Inference for Deep CNNs on FPGALucian Petrica, Tobias Alonso, Mairin Kroes, Nicholas J. Fraser, Sorin Cotofana, Michaela Blott. 48-55 [doi]
• From TensorFlow Graphs to LUTs and Wires: Automated Sparse and Physically Aware CNN Hardware GenerationMathew Hall, Vaughn Betz. 56-65 [doi]
• INFER: INterFerence-aware Estimation of Runtime for Concurrent CNN Execution on DPUsShikha Goel, Rajesh Kedia, M. Balakrishnan, Rijurekha Sen. 66-71 [doi]
• DASH: Design Automation for Synthesis and Hardware Generation for CNNArish Sateesan, Sharad Sinha, Smitha K. G.. 72-75 [doi]
• How Much Does Regularity Help FPGA Placement?Hongxin Kong, Lang Feng, Chunhua Deng, Bo Yuan 0001, Jiang Hu. 76-84 [doi]
• Learn to Place: FPGA Placement Using Reinforcement Learning and Directed MovesMohamed A. Elgammal, Kevin E. Murray, Vaughn Betz. 85-93 [doi]
• Revisiting FPGA Routing under Varying Operating ConditionsBehnam Khaleghi, Sahand Salamat, Tajana Simunic Rosing. 94-102 [doi]
• Neighbors From Hell: Voltage Attacks Against Deep Learning Accelerators on Multi-Tenant FPGAsAndrew Boutros, Mathew Hall, Nicolas Papernot, Vaughn Betz. 103-111 [doi]
• Jitter-based Adaptive True Random Number Generation for FPGAs in the CloudXiang Li, Peter Stanwicks, George Provelengios, Russell Tessier, Daniel E. Holcomb. 112-119 [doi]
• New Directions for NewHope: Improving Performance of Post-Quantum Cryptography through Algorithm-level PipeliningLuke Beckwith, William Diehl. 120-128 [doi]
• Bandwidth Efficient Near-Storage Accelerator for High-Dimensional Similarity SearchGongjin Sun, Sang-Woo Jun. 129-138 [doi]
• CHIP-KNN: A Configurable and High-Performance K-Nearest Neighbors Accelerator on Cloud FPGAsAlec Lu, Zhenman Fang, Nazanin Farahpour, Lesley Shannon. 139-147 [doi]
• A High Throughput Parallel Hash Table Accelerator on HBM-enabled FPGAsYang Yang, Sanmukh R. Kuppannagari, Viktor K. Prasanna. 148-153 [doi]
• Cloud FPGA Security with RO-Based PrimitivesShanquan Tian, Andrew Krzywosz, Ilias Giechaskiel, Jakub Szefer. 154-158 [doi]
• A Reconfigurable Compute-in-the-Network FPGA Assistant for High-Level Collective Support with Distributed Matrix Multiply Case StudyPouya Haghi, Anqi Guo, Tong Geng, Justin T. Broaddus, Derek Schafer, Anthony Skjellum, Martin C. Herbordt. 159-164 [doi]
• Designing Universal Logic Module FPGA Architectures for Use With Ambipolar Transistor TechnologyJohannes Pfau, Maximilian Reuter, Klaus Hofmann, Jürgen Becker 0001. 165-173 [doi]
• GIB: A Novel Unidirectional Interconnection Architecture for FPGAKaichuang Shi, Hao Zhou, Xuegong Zhou, Lingli Wang. 174-181 [doi]
• A Complete Open Source Design Flow for Gowin FPGAsPepijn de Vos, Michael Kirchhoff, Daniel Ziener. 182-189 [doi]
• FlexBex: A RISC-V with a Reconfigurable Instruction ExtensionNguyen-Dao, Andrew Attwood, Bea Healy, Dirk Koch. 190-195 [doi]
• Fast Linking of Separately-Compiled FPGA Blocks without a NoCYuanlong Xiao, Syed Tousif Ahmed, André DeHon. 196-205 [doi]
• StateReveal: Enabling Checkpointing of FPGA Designs with Buried StateSameh Attia, Vaughn Betz. 206-214 [doi]
• Build Automation and Runtime Abstraction for Partial Reconfiguration on Xilinx Zynq UltraScale+Alex R. Bucknall, Shanker Shreejith, Suhaib A. Fahmy. 215-220 [doi]
• Moving Compute towards Data in Heterogeneous multi-FPGA Clusters using Partial Reconfiguration and I/O VirtualisationKhoa Dang Pham, Dirk Koch, Anuj Vaishnav, Konstantinos Georgopoulos, Pavlos Malakonakis, Aggelos Ioannou, Iakovos Mavroidis. 221-226 [doi]
• Automatic Selection and Insertion of HLS Directives Via a Source-to-Source CompilerTiago Santos, João M. P. Cardoso. 227-232 [doi]
• A Design Exploration of Scalable Mesh-based Fully Pipelined AcceleratorsWesterley Carvalho, Michael Canesche, Lucas Reis, Frank Sill Torres, Lucas B. da Silva, Peter Jamieson, José Augusto Miranda Nacif, Ricardo S. Ferreira. 233-236 [doi]
• Quantisation-aware Dimensionality ReductionCe Guo, Wayne Luk. 237-240 [doi]
• A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol for Network-Attached Hardware AcceleratorsNiklas Schelten, Fritjof Steinert, Anton Schulte, Benno Stabernack. 241-249 [doi]
• Hardware Implementations with High Throughput, Low-Latency and Low-Area for Matrix InversionSultan Alqahtani, Yiqun Zhu, Qizhi Shi, Xiaolin Meng, Xinhua Wang. 250-255 [doi]
• Acceleration of Short Read Alignment with Runtime ReconfigurationHo-Cheung Ng, Shuanglong Liu, Izaak Coleman, Ringo S. W. Chu, Man-Chung Yue, Wayne Luk. 256-262 [doi]
• Service Chaining for Heterogeneous MiddleboxesXuzhi Zhang, Russell Tessier. 263-267 [doi]
• ReconROS: Flexible Hardware Acceleration for ROS2 ApplicationsChristian Lienen, Marco Platzner, Bernhard Rinner. 268-276 [doi]
• A Bucket-Stream rBRIEF Extraction Architecture for SLAM Applications on Embedded PlatformsHaowen Chen, Feiteng Li, Zhuo Zhang. 277-280 [doi]
• Battling the CPU Bottleneck in Apache Parquet to Arrow Conversion Using FPGAJohan Peltenburg, Lars T. J. van Leeuwen, Joost Hoozemans, Jian Fang 0004, Zaid Al-Ars, H. Peter Hofstee. 281-286 [doi]
• Ultra-Low-Latency Video Encoding on Heterogenous Hardware PlatformsMartin Koppehel, Thilo Pionteck. 287 [doi]
• Nonintrusive and Adaptive Monitoring for Locating Voltage Attacks in Virtualized FPGAsSeyedeh Sharareh Mirzargar, Gaiëtan Renault, Andrea Guerrieri, Mirjana Stojilovic. 288-289 [doi]
• High Throughput and Low Latency Multi-Version Management Key-Value Storage AcceleratorHankun Lv, Yuchen Ren, Yunhui Qiu, Wenbo Yin, Lingli Wang. 290-291 [doi]
• Automated Integration of High-Level Synthesis FPGA Modules with ROS2 SystemsDaniel Pinheiro Leal, Midori Sugaya, Hideharu Amano, Takeshi Ohkawa. 292-293 [doi]
• Design Method for an LUT Network-Based CNN with a Sparse Local ConvolutionNaoto Soga, Hiroki Nakahara. 294-295 [doi]
• An FPGA-Based Upper-Limb Rehabilitation Device for Gesture Recognition and Motion Evaluation Using Multi-Task Recurrent Neural NetworksHaoyan Liu, Atiyehsadat Panahi, David Andrews, Alexander Nelson. 296-297 [doi]
• Performance Exploration on Pre-implemented CNN Hardware Accelerator on FPGADanielle Tchuinkou Kwadjo, Joel Mandebi Mbongue, Christophe Bobda. 298-299 [doi]
• Exploring performance enhancement of event-driven processor networksTim Todman, David B. Thomas, Wayne Luk. 300 [doi]
• Towards Overlay-based Rapid In-Circuit Tuning of Deep Learning DesignsZhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Xinyu Niu, Steven J. E. Wilton, Wayne Luk. 301 [doi]