Table of Contents

• Impact of device and interconnect process variability on clock distributionNathalie Fievet, Praveen Raghavan, Rogier Baert, Frédéric Robert, Abdelkarim Mercha, Diederik Verkest, Aaron Thean. 1-4 [doi]
• NEMS switches: Opportunities and challenges in emerging IC technologiesPhilip X.-L. Feng. 1-6 [doi]
• Current pulse generator for multilevel cell programming of innovative PCMAthanasios Kiouseloglou, Gabriele Navarro, Alessandro Cabrini, Guido Torelli, Luca Perniola. 1-4 [doi]
• Impact of time-dependent variability on the yield and performance of 6T SRAM cells in an advanced HK/MG technologyPieter Weckx, Ben Kaczer, Philippe J. Roussel, Francky Catthoor, Guido Groeseneken. 1-4 [doi]
• Assessment of SiGe quantum well transistors for DRAM peripheral applicationsRomain Ritzenthaler, Tom Schram, Geert Eneman, Anda Mocuta, Naoto Horiguchi, Aaron Voon-Yew Thean, Alessio Spessot, Marc Aoulaiche, Pierre Fazan, K. B. Noh, Y. Son. 1-4 [doi]
• ESD protection diodes in optical interposer technologyRoman Boschke, Guido Groeseneken, Mirko Scholz, Shih-Hung Chen, Geert Hellings, Peter Verheyen, Dimitri Linten. 1-4 [doi]
• Impact of random telegraph noise on ring oscillators evaluated by circuit-level simulationsAzusa Oshima, Pieter Weckx, Ben Kaczer, Kazutoshi Kobayashi, Takashi Matsumoto. 1-4 [doi]
• I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integrationRomain Ritzenthaler, Tom Schram, M. J. Cho, Anda Mocuta, Naoto Horiguchi, Aaron Voon-Yew Thean, Alessio Spessot, C. Caillat, Marc Aoulaiche, Pierre Fazan, K. B. Noh, Y. Son. 1-4 [doi]
• Thermal experimental and modeling analysis of high power 3D packagesHerman Oprins, Vladimir Cherman, Geert Van der Plas, F. L. T. Maggioni, Joeri De Vos, Eric Beyne. 1-4 [doi]
• PBTI for N-type tunnel FinFETsWataru Mizubayashi, T. Mori, K. Fukuda, Y. X. Liu, Takashi Matsukawa, Yuki Ishikawa, Kazuhiko Endo, Shin-ichi O'Uchi, Junichi Tsukada, Hiromi Yamauchi, Yukinori Morita, Shinji Migita, Hiroyuki Ota, Meishoku Masahara. 1-4 [doi]
• Lateral NWFET optimization for beyond 7nm nodesDmitry Yakimets, Doyoung Jang, Praveen Raghavan, Geert Eneman, Hans Mertens, P. Schuddinck, Arindam Mallik, Marie Garcia Bardon, Nadine Collaert, Abdelkarim Mercha, Diederik Verkest, Aaron Thean, Kristin De Meyer. 1-4 [doi]
• Simple technique for prediction of breakdown voltage of ultrathin gate insulator under ESD testingYuichiro Mitani, Kazuya Matsuzawa. 1-4 [doi]
• Integrated front-end/back-end simulation of electromagnetic fields, Lorentz force effects and fast current surges in microelectronic protection devicesWim Schoenmaker, Philippe Galy. 1-4 [doi]
• Design of a low-power fixed-point 16-bit digital signal processor using 65nm SOTB processDuc-Hung Le, Nobuyuki Sugii, Shiro Kamohara, Xuan-Thuan Nguyen, Koichiro Ishibashi, Cong-Kha Pham. 1-4 [doi]
• Nonparabolicity and confinement effects of IIIV materials in novel transistorsM. Ali Pourghaderi, Anda Mocuta, Aaron Thean. 1-3 [doi]
• Selectors for high density crosspoint memory arrays: Design considerations, device implementations and some challenges aheadBogdan Govoreanu, Leqi Zhang, Malgorzata Jurczak. 1-4 [doi]
• Deadspace-aware Power/Ground TSV planning in 3D floorplanningShengcheng Wang, Farshad Firouzi, Fabian Oboril, Mehdi Baradaran Tahoori. 1-4 [doi]
• Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devicesTse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang. 1-4 [doi]
• Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMsAnuj Grover, Promod Kumar, Mohammad Daud, G. S. Visweswaran, Chittoor Parthasarathy, Jean-Philippe Noel, David Turgis, Bastien Giraud, Guillaume Moritz. 1-4 [doi]
• Dimensioning for power and performance under 10nm: The limits of FinFETs scalingMarie Garcia Bardon, P. Schuddinck, Praveen Raghavan, Doyoung Jang, Dmitry Yakimets, Abdelkarim Mercha, Diederik Verkest, Aaron Thean. 1-4 [doi]
• Modeling FinFET metal gate stack resistance for 14nm node and beyondKenichi Miyaguchi, Bertrand Parvais, Lars-Åke Ragnarsson, Piet Wambacq, Praveen Raghavan, Abdelkarim Mercha, Anda Mocuta, Diederik Verkest, Aaron Thean. 1-4 [doi]
• Countering early propagation and routing imbalance of DPL designs in a tree-based FPGAEmna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger. 1-4 [doi]
• Plasma-induced photon irradiation damage on low-k dielectrics enhanced by Cu-line layoutTaro Ikeda, Akira Tanihara, Nobuhiko Yamamoto, Shigeru Kasai, Koji Eriguchi, Kouichi Ono. 1-4 [doi]
• Plasma induced damage investigation in the fully depleted SOI technologyM. Akbal, G. Ribes, M. Guillermet, L. Vallier. 1-4 [doi]
• Through silicon via to FinFET noise coupling in 3-D integrated circuitsA. Rouhi Najaf Abadi, W. Guo, X. Sun, K. Ben Ali, Jean-Pierre Raskin, M. Rack, C. Roda Neve, M. Choi, V. Moroz, Geert Van der Plas, Ingrid De Wolf, Eric Beyne, P. Absil. 1-4 [doi]
• Impact of fin shape variability on device performance towards 10nm nodeKazuyuki Tomida, Keizo Hiraga, Morin Dehan, Geert Hellings, Doyoung Jang, Kenichi Miyaguchi, Thomas Chiarella, Minsoo Kim, Anda Mocuta, Naoto Horiguchi, Abdelkarim Mercha, Diederik Verkest, Aaron Thean. 1-4 [doi]
• A 6T-SRAM in 28nm FDSOI technology with Vmin of 0.52V using assisted read and write operationAshish Kumar, Vinay Kumar, Dhori Kedar Janardan, G. S. Visweswaran, Kaushik Saha. 1-4 [doi]
• Low-phase noise variation VCO implementing resistorless digitally controlled varactorMohammed Aqeeli, Abdullah Alburaikan, Xianjun Huang, Zhirun Hu. 1-4 [doi]
• FinFET stressor efficiency on alternative wafer and channel orientations for the 14 nm node and belowGeert Eneman, A. De Keersgieter, Anda Mocuta, Nadine Collaert, Aaron Thean. 1-4 [doi]
• Static and dynamic power management in 14nm FDSOI technologyOlivier Weber, Emmanuel Josse, J. Mazurier, Michel Haond. 1-4 [doi]
• Impact of local interconnects on ESD designMirko Scholz, Shih-Hung Chen, Geert Hellings, Dimitri Linten, Roman Boschke. 1-4 [doi]
• Surface orientation dependence of ion bombardment damage during plasma processingYukimasa Okada, Koji Eriguchi, Kouichi Ono. 1-5 [doi]
• Area and routing efficiency of SWD circuits compared to advanced CMOSOdysseas Zografos, Praveen Raghavan, Yasser Sherazi, Adrien Vaysset, Florin Ciubatoru, Bart Soree, Rudy Lauwereins, Iuliana Radu, Aaron Thean. 1-4 [doi]
• Reliability impact of advanced doping techniques for DRAM peripheral MOSFETsAlessio Spessot, Romain Ritzenthaler, Tom Schram, Marc Aoulaiche, Moonju Cho, Maria Toledano-Luque, Naoto Horiguchi, Pierre Fazan. 1-4 [doi]
• A high-speed 2×VDD output buffer with PVTL detection using 40-nm CMOS technologyChua-Chin Wang, Tsung-Yi Tsai, Wei Lin. 1-4 [doi]
• Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAMTrong Huynh Bao, Sushil Sakhare, Julien Ryckaert, Dmitry Yakimets, Abdelkarim Mercha, Diederik Verkest, Aaron Voon-Yew Thean, Piet Wambacq. 1-4 [doi]
• Optimal design to maximize efficiency of single-inductor multiple-output buck converters in discontinuous conduction mode for IoT applicationsYoshitaka Yamauchi, Yuki Yanagihara, Hiroshi Fuketa, Takayasu Sakurai, Makoto Takamiya. 1-4 [doi]
• Simple wafer stacking 3D-FPGA architectureMotoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi. 1-4 [doi]
• Power measurements and cooling of the DOME 28nm 1.8GHz 24-thread ppc64 μServer compute nodeRonald P. Luijten, Matteo Cossale, Rolf Clauberg, Andreas C. Döring. 1-4 [doi]
• High-speed analog-to-digital converters in downscaled CMOSAnnachiara Spagnolo, Bob Verbruggen, Stefano D'Amico, Piet Wambacq. 1-4 [doi]
• Trapping induced parasitic effects in GaN-HEMT for power switching applicationsGaudenzio Meneghesso, Matteo Meneghini, Enrico Zanoni, Piet Vanmeerbeek, Peter Moens. 1-4 [doi]
• Wide band study of silicon-on-insulator photodiodes on suspended micro-hotplates platformsN. Andre, G. Li, P. Gerard, Olivier Poncelet, Y. Zeng, S. Z. Ali, Florin Udrea, Laurent A. Francis, Denis Flandre. 1-4 [doi]
• Overview of methods to increase linearity of high-performance ADCHua Fan, Kehong Liu, Airong Liu, Lishan Lv, Zhiliang Qiao, Qiang Li. 1-4 [doi]
• Metallization scheme optimization of plastic-encapsulated electronic power devicesJan Ackaert, Tony Colpaert, Aditi Malik, Mario Gonzalez. 1-4 [doi]
• Off-state stress degradation mechanism on advanced p-MOSFETsMoonju Cho, Alessio Spessot, Ben Kaczer, Marc Aoulaiche, Romain Ritzenthaler, Tom Schram, Pierre Fazan, Naoto Horiguchi, Dimitri Linten. 1-4 [doi]
• Characterization of onset tunneling voltage (Vonset) walkout in high-voltage deep trench isolation on SOIThuy Dao, Mu-Ling Ger, Jiangkai Zuo. 1-4 [doi]
• 3D monolithic integration: Stacking technology and applicationsIonut Radu, Bich-Yen Nguyen, Gweltaz Gaudin, Carlos Mazure. 1-3 [doi]
• Preliminary 3D TCAD electro-thermal simulations of BIMOS transistor in thin silicon film for ESD protection in FDSOI UTBB CMOS technologyS. Athanasiou, Sorin Cristoloveanu, Philippe Galy. 1-4 [doi]