Abstract is missing.
- Author retrospective for PTRAN's analysis and optimization techniquesRon K. Cytron, Jeanne Ferrante, Frances E. Allen, Michael G. Burke, Philippe Charles. 1-3 [doi]
- Author retrospective for code scheduling and register allocation in large basic blocksJames R. Goodman, Wei-Chung Hsu. 4-5 [doi]
- Author retrospective for array expansion, array shrinking, or there and back againPaul Feautrier. 6 [doi]
- global resource-constrained parallelization techniqueKemal Ebcioglu, Alexandru Nicolau. 7-8 [doi]
- Author retrospective for compiler-directed data prefetching in multiprocessors with memory hierarchiesEdward H. Gornish, Elana D. Granston, Alexander V. Veidenbaum. 9-11 [doi]
- Author retrospective for semantical interprocedural parallelization: an overview of the PIPS projectFrançois Irigoin, Pierre Jouvelot, Rémi Triolet. 12-14 [doi]
- Author retrospective for optimizing for parallelism and data localityKathryn S. McKinley. 15-17 [doi]
- Author retrospective for PYRROS: static task scheduling and code generation for message passing multiprocessorsTao Yang, Apostolos Gerasoulis. 18-20 [doi]
- Author's retrospective for array privatization for parallel execution of loopsZhiyuan Li. 21-23 [doi]
- Author retrospective for increasing the instruction fetch rate via multiple branch prediction and a branch address cacheTse-Yu Yeh, Deborah T. Marr, Yale N. Patt. 24-25 [doi]
- Author retrospective for anatomy of a message in the alewife multiprocessorJohn Kubiatowicz. 26-28 [doi]
- Author retrospective: compilation techniques for block-cyclic distributionsJohn M. Mellor-Crummey, Seema Hiranandani, Ajay Sethi. 29-31 [doi]
- Author retrospective for the dual data cacheAntonio González, Carlos Aliagas. 32-34 [doi]
- Author retrospective for optimum modulo schedules for minimum register requirementsAlexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham. 35-36 [doi]
- Author retrospective for counting solutions to linear and nonlinear constraints through ehrhart polynomials: applications to analyze and transform scientific programsPhilippe Clauss. 37-39 [doi]
- Author retrospective improving data cache performance by pre-executing instructions under a cache missTrevor N. Mudge. 40-41 [doi]
- Author retrospective for optimizing matrix multiply using PHiPAC: a portable high-performance ANSI C coding methodologyJeff A. Bilmes, Krste Asanovic, Chee-Whye Chin, Jim Demmel. 42-44 [doi]
- Author retrospective for software trace cacheAlex Ramírez, Ayose Falcón, Oliverio J. Santana, Mateo Valero. 45-47 [doi]
- Author retrospective of Dynamic application scheduling using on-line analytics: then and nowRich Wolski. 48-50 [doi]
- Author's retrospective for: improving the performance of speculatively parallel applications on the hydra CMPKunle Olukotun, Lance Hammond, Mark Willey. 51-53 [doi]
- Author retrospective for characterizing processor architectures for programmable network interfacesPatrick Crowley. 54-55 [doi]
- Author retrospective for synthesizing transformations for locality enhancement of imperfectly-nested loop nestsKeshav Pingali. 56-58 [doi]
- Author retrospective for adaptive reduction parallelization techniquesHao Yu, Lawrence Rauchwerger. 59-60 [doi]
- Author retrospective for analytical cache models with applications to cache partitioningG. Edward Suh, George Kurian, Srinivas Devadas, Larry Rudolph. 61-63 [doi]
- Author retrospective for search and replication in unstructured peer-to-peer networksQin Lv, Pei Cao, Edith Cohen, Kai Li, Scott Shenker. 64-82 [doi]
- Author retrospective for bloom filtering cache misses for accurate data speculation and prefetchingJih-Kwon Peir, Shih-Chang Kevin Lai, Shih-Lien Lu, Jared Stark, Konrad Lai. 65-67 [doi]
- Author retrospective AEGIS: architecture for tamper-evident and tamper-resistant processingG. Edward Suh, Christopher W. Fletcher, Dwaine E. Clarke, Blaise Gassend, Marten van Dijk, Srinivas Devadas. 68-70 [doi]
- Author retrospective on energy conservation techniques for disk array-based serversEduardo Pinheiro, Ricardo Bianchini. 71-73 [doi]
- Author retrospective for a NUCA substrate for flexible CMP cache sharingJaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhang 0002, Doug Burger, Stephen W. Keckler. 74-76 [doi]
- Author retrospective for design tradeoffs for tiled CMP on-chip networksWilliam J. Dally, James D. Balfour. 77-79 [doi]
- Author retrospective for cooperative cache partitioning for chip multiprocessorsJichuan Chang, Gurindar S. Sohi. 80-81 [doi]
- Author's retrospective for biomedical image analysis on a cooperative cluster of gpus and multicoresTimothy D. R. Hartley, Ümit V. Çatalyürek, Antonio Ruiz, Francisco D. Igual, Rafael Mayo, Manuel Ujaldon. 82-84 [doi]