Abstract is missing.
- Static analysis for worst-case battery utilizationDmitry Ivanov, Sibylle Schupp. 1-10 [doi]
- Clock reduction in timed automata while preserving design parametersBeyazit Yalcinkaya, Ebru Aydin Gol. 11-20 [doi]
- Rigorous design and deployment of IoT applicationsAjay Krishna 0001, Michel Le Pallec, Radu Mateescu 0001, Ludovic Noirie, Gwen Salaün. 21-30 [doi]
- Parallelizable reachability analysis algorithms for feed-forward neural networksHoang-Dung Tran, Patrick Musau, Diego Manzanas Lopez, Xiaodong Yang, Luan Viet Nguyen, Weiming Xiang, Taylor T. Johnson. 31-40 [doi]
- FASTEN: an open extensible framework to experiment with formal specification approaches: using language engineering to develop a multi-paradigm specification environment for NuSMVDaniel Ratiu, Marco Gario, Hannes Schoenhaar. 41-50 [doi]
- Epistemic model checking of distributed commit protocols with byzantine faultsOmar I. Al-Bataineh, Mark Reynolds. 51-60 [doi]
- Towards sampling and simulation-based analysis of featured weighted automataMaxime Cordy, Axel Legay, Sami Lazreg, Philippe Collet. 61-64 [doi]
- Verifying channel communication correctness for a multi-core cooperatively scheduled runtime using CSPJan Bækgaard Pedersen, Kevin Chalmers. 65-74 [doi]
- A generalized program verification workflow based on loop elimination and SA formCláudio Belo Lourenço, Maria João Frade, Jorge Sousa Pinto. 75-84 [doi]
- Modular synthesis of verified verifiers of computation with STV algorithmsMilad K. Ghale, Dirk Pattinson, Michael Norrish. 85-94 [doi]
- A vision for helping developers use APIs by leveraging temporal patternsErick Raelijohn, Michalis Famelis, Houari A. Sahraoui. 95-98 [doi]
- A proof-producing translator for verilog development in HOLAndreas Lööw, Magnus O. Myreen. 99-108 [doi]
- On the formalization of importance measures using HOL theorem provingWaqar Ahmad, Shahid Ali Murtza, Osman Hasan, Sofiène Tahar. 109-118 [doi]