Abstract is missing.
- Keynote 2: "Computing for big-data: Beyond CMOS and beyond Von-Neumann"Said Hamdioui. 1 [doi]
- Keynote 3: "Ensuring robustness in today's IoT era"Yervant Zorian. 1 [doi]
- Keynote 1: "Merger mania"Hanna Windele. 1 [doi]
- Transforming between logic locking and IC camouflagingMuhammad Yasin, Ozgur Sinanoglu. 1-4 [doi]
- Obfuscated arbitrary computation using cryptographic primitivesNektarios Georgios Tsoutsos, Michail Maniatakos. 5-8 [doi]
- Reliability degradation in the scope of aging - From physical to system levelHussam Amrouch, Jörg Henkel. 9-12 [doi]
- Revolutionizing validation: The Intel approach for TTMRa'ed Al-Omari, Shahil Rais. 13 [doi]
- SoC verification platforms using HW emulation and co-modeling Testbench technologiesMohamed AbdElSalam, Ashraf Salem. 14-19 [doi]
- Chip-level programming of heterogeneous multiprocessorsMwaffaq Otoom, JoAnn M. Paul. 20-25 [doi]
- Heterogeneous multi-core architecture for a 4G communication in high-speed railwayMariem Makni, Mouna Baklouti, Smaïl Niar, Morteza Biglari-Abhari, Mohamed Abid. 26-31 [doi]
- Memory profiling for intra-application data-communication quantification: A surveyImran Ashraf, Mottaqiallah Taouil, Koen Bertels. 32-37 [doi]
- A 10 Gbps ADC-based equalizer for serial I/O receiverKhaled A. El-Gammal, Ahmed N. Hassan, Sameh A. Ibrahim. 38-43 [doi]
- A low-temperature-coefficient curvature-compensated bandgap reference with mismatch attenuationMahitab F. Eladwy, Sameh A. Ibrahim, Mohamed Dessouky. 44-48 [doi]
- Toward the interfacing of systemC-AMS models with hardware-emulated platformsHanan Tawfik, Mona Safar, Mohamed Abdel Salam, M. Watheq El-Kharashi, Ashraf Salem. 54-59 [doi]
- Guiding intelligent testbench automation using data mining and formal methodsEman El Mandouh, Amr G. Wassal. 60-65 [doi]
- Multiple fault testing in systems-on-chip with high-level decision diagramsRaimund Ubar, Stephen Adeboye Oyeniran, Mario Schölzel, Heinrich Theodor Vierhaus. 66-71 [doi]
- Reconfigurable test platform for modular embedded systems in manufacturing processesSilviu Folea, Szilárd Enyedi, Liviu Miclea, Horia Hedesiu. 72-77 [doi]
- An automatic ECG generator for testing and evaluating ECG sensor algorithmsHussam M. N. Al Hamadi, Amjad Gawanmeh, Mahmoud Al-Qutayri. 78-83 [doi]
- Efficient data management on 3D stacked memory for big data applicationsCheng Qian, Libo Huang, Peng Xie, Nong Xiao, Zhiying Wang. 84-89 [doi]
- A bi-objective heuristic for heterogeneous MPSoC design space explorationLotfi Braham Mediouni, Smaïl Niar, Rachid Benmansour, Karima Benatchba, Mouloud Koudil. 90-95 [doi]
- NRTBox: A Matlab Simulink toolbox for NoC switch performance evaluation and early architectural exploration using discrete event simulationSamir Ben Abid, Nejib Mediouni, Oussama Kallel, Salem Hasnaoui. 96-99 [doi]
- BTI analysis of SRAM write driverInnocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor. 100-105 [doi]
- Aging and leakage tradeoff in VLSI circuitsHao Luo, Mehrdad Nourani. 106-111 [doi]
- Testing of 3D IC with minimum power using genetic algorithmTanusree Kaibartta, Debesh K. Das. 112-117 [doi]
- A method of LFSR seed generation for hierarchical BISTKosuke Sawaki, Satoshi Ohtake. 118-123 [doi]
- SR-TPG: A low transition test pattern generator for test-per-clock and test-per-scan BISTAbdallatif S. Abu-Issa, Iyad K. Tumar, Wasel T. Ghanem. 124-128 [doi]
- Facilitating side channel analysis by obfuscation for Hardware Trojan detectionArash Nejat, David Hély, Vincent Beroulle. 129-134 [doi]
- FPGA implementation of scalar multiplication over Fp for elliptic curve cryptosystemAhmed Bellemou, Mohamed Anane, Nadjia Benblidia, Mohamed Issad. 135-140 [doi]
- A novel wavelet-based method for TSV modelingKhaled Salah. 141-142 [doi]
- High level NoC modeling using discrete event simulationNejib Mediouni, Samir Ben Abid, Oussama Kallel, Salem Hasnaoui. 143-144 [doi]
- A proposed methodology to improve UVM-based test generation and coverage closureKhaled Fathy, Khaled Salah, Rafik Guindi. 147-148 [doi]
- Automatic test pattern generation for virtual hardware model using constrained symbolic executionNahla Mohamed, Mona Safar, Ayman M. Wahba, Ashraf Salem. 149-150 [doi]
- SimEvents based high level early design space exploration and modeling of a 3D Network on ChipNejib Mediouni, Samir Ben Abid, Oussama Kallel, Salem Hasnaoui. 157-158 [doi]
- Design constraints and challenges behind fault tolerance systems in a mobile application frameworkVenkata Narasimha Inukollu, TaegHyun Kang, Nina Sakhnini. 159-160 [doi]