Abstract is missing.
- RTL Controller SynthesisChiLai Huang, Joseph Lis, Michael Quayle, Saurin Shroff. 3-17
- Timing-Driven State Assignment for Controller-Datapath SystemsSteve C.-Y. Huang, Wayne Wolf. 19-31
- Tokenized State Machine Model for Synthesis of Sequential Circuits into EPLDs and FPGAsAlan J. Coppola, Marek A. Perkowski, Robert Anderson, Jeffrey S. Freedman, Edmund Pierzchala. 33-46
- Synthesis of large controllers using ROM or PLA generatorsL. Gerbaux, Régis Leveugle, Gabriele Saucier. 47-59
- Flag/Condition Handling and Branch Assignment for Large Microcoded ControllersAugusli Kifli, R. De Wulf, J. Zegers, Gert Goossens, Paul Six, Hugo De Man. 61-71
- The Synthesis of a Parallel Controller from a Petri Net ModelJames Pardey. 73-89
- Specification and Synthesis of Communicating Finite State MachinesH. Belhadj, L. Gerbaux, Marie-Claude Bertrand, Gabriele Saucier. 91-102
- Controller Implementation by Communicating Asynchronous Sequential Circuits Generated from a Petri Net Specification of Required BehaviorJochen Beister, Ralf Wollowski. 103-115
- Pathway: A datapath layout assemblerAmnon Baron Cohen, Michael Shechory. 119-131
- FITPATH: A Process-Independent Datapath Compiler Providing High Density LayoutLotfi Ben Ammar, Alain Greiner. 133-151
- Generation of optimized datapaths: bit-slice versus standard cellsRégis Leveugle, C. Safina. 153-166
- Regular Module Generation or Standard Cells: Two Alternative Implementations of a Library of Functional Building BlocksEvagelos Katsadas, Zohair Sahraoui, M. Wouters, Veerle Derudder, Ivo Bolsens, Paul Six, Hugo De Man. 167-181
- Design of data-path module generators from algorithmic representationsVasily G. Moshnyaga, Keikichi Tamaru, Hiroto Yasuura. 183-192
- Data-Path Synthesis as Grammar InferenceFarhad Mavaddat. 193-205
- Microarchitecture/Microcode Synthesis from VHDLE. T. Kapuya, M. D. Edwards. 209-218
- AMICAL: Architectural Synthesis based on VHDLI. Park, Kevin O Brien, Ahmed Amine Jerraya. 219-234
- RTL OptimizA: From Control Data Flow Graph to Logic CircuitYang Wu, Ian Dorrington. 235-247
- Implementations of IF-statements in the TODOS microarchitecture synthesis systemPeter Marwedel. 249-262
- Data Part Optimizations in the CALLAS Synthesis EnvironmentJ. Biesenack, Norbert Wehn, A. Stoll, Michael Payer. 263-274
- ASYL: A Control Driven RTL Synthesis System using Library BlocksAnne Mignotte, Marie-Claude Bertrand, Michel Crastes de Paulet, Jérôme Rampon, Gabriele Saucier. 275-291
- Clocking scheme selection for circuits made up of a controller and a datapathC. Safina, Régis Leveugle. 293-308
- Optimization strategies in symbolic compactionFrancesco Curatelli, Daniele D. Caviglia, Marco Chirico, Giacomo M. Bisio. 311-322
- A general and efficient mask pattern generator for non-series-parallel CMOS transistor networkH. Zhang, Kunihiro Asada. 323-333
- Logic Synthesis for Automatic LayoutPierre Abouzeid, Régis Leveugle, Gabriele Saucier. 335-343
- MADMACS: an environment for the layout of regular arraysEric Gautrin, Laurent Perraudeau. 345-358
- Module Generation in an Architectural Synthesis EnvironmentJ. F. M. Theeuwen, H. M. A. M. Arts, Jos T. J. van Eijndhoven, H. J. H. Sleuters, J. H. P. Wijdeven. 359-371
- BADGE - A synthesis tool for customized arithmetic building blocksAndreas Münzner. 373-384
- Automatic Layout Synthesis of Pipelined Multipliers for Systolic ArraysA. G. Jost, L. F. Wang, S. Periyalwar, William Robertson. 385-398
- Floorplan Optimized Topological Partitioning of Programmed Logic ArraysA. J. W. M. ten Berg. 399-411
- Timing Model Accuracy Issues and Automated Library CharacterizationAntonio Martinez. 413-426
- Design Library Portability: A Case StudyB. Conq, R. Etienne, T. Perez-Segovia. 427-436
- Benchmarking and the Art of Syntesis Tool ComparisonDaniel Gajski, Nikil D. Dutt. 439-453