Abstract is missing.
- VLSI Programming of a Modulo-N Counter with Constant Response Time and Constant PowerKees van Berkel. 1-11
- Linear Test Times for Delay-Insensitive Circuits: a Compilation StrategyMarly Roncken, Ronald Saeijs. 13-27
- Self-Timed Architecture of a Reduced Instruction Set ComputerIlana David, Ran Ginosar, Michael Yoeli. 29-43
- Self-Timed Fully Pipelined MultipliersO. Salomon, Heinrich Klar. 45-55
- Normal Form in a Delay-Insensitive AlgebraRix Groenboom, Mark B. Josephs, Paul G. Lucassen, Jan Tijmen Udding. 57-70
- Synthesis of Asynchronous Control Circuits from Symbolic Signal Transition GraphsAlexandre Yakovlev, A. I. Petrov, Leonid Ya. Rosenblum. 71-85
- Hazard-Free Asynchronous Circuit SynthesisMeng-Lin Yu, P. A. Subrahmanyam. 87-105
- Automated Synthesis of Asynchronous Interface CircuitsLuciano Lavagno, Alberto L. Sangiovanni-Vincentelli. 107-121
- Implementing a Stack as a Delay-insensitive CircuitMark B. Josephs, Jan Tijmen Udding. 123-135
- Solving a Mutual Exclusion Problem with the RGD ArbiterJo C. Ebergen, P. F. Bertrand, S. Gingras. 137-147
- Asynchronous Multipliers as Combinational Handshake CircuitsJaco Haans, Kees van Berkel, Ad M. G. Peeters, Frits D. Schalij. 149-163
- Design of Self-timed Multipliers: A ComparisonJens Sparsø, Christian D. Nielsen, Lars Skovby Nielsen, Jørgen Staunstrup. 165-179
- A CMOS VLSI Implementation of an Asynchronous ALUJim D. Garside. 181-192
- Automatic Synthesis of Fast Compact Asynchronous Control CircuitsAl Davis, Bill Coates, Ken Stevens. 193-207
- Characterization and Evaluation of a Compiled Asynchronous ICKees van Berkel, Ronan Burgess, Joep L. W. Kessels, Marly Roncken, Frits D. Schalij. 209-221