Abstract is missing.
- On-Line Failure Detection and Confinement in CachesJaume Abella, Pedro Chaparro, Xavier Vera, Javier Carretero, Antonio González. 3-9 [doi]
- An Enhanced Logic BIST Architecture for Online TestingFan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz. 10-15 [doi]
- Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error DetectionJimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan. 16-21 [doi]
- Verification and Analysis of Self-Checking Properties through ATPGMarc Hunger, Sybille Hellebrand. 25-30 [doi]
- Physical Demonstration of Polymorphic Self-Checking CircuitsRichard Ruzicka, Lukás Sekanina, Roman Prokop. 31-36 [doi]
- New Linear SEC-DED Codes with Reduced Triple Bit Error Miscorrection ProbabilityMichael Richter, Klaus Oberländer, Michael Gössel. 37-42 [doi]
- Special Session 1: Radiation Hardening TechniquesNorbert Seifert. 43-44 [doi]
- Soft Error Protection TechniquesSubhasish Mitra. 45 [doi]
- Growing Interest of Advanced Commercial CMOS Technologies for Space and Medical Applications. Illustration with a New Nano-Power and Radiation-Hardened SRAM in 130nm CMOSPhilippe Roche, Mark Lysinger, Gilles Gasiot, Jean-Marc Daveau, Mehdi Zamanian, Pierre Dautriche. 46-48 [doi]
- Soft Error Rates of Hardened Sequentials utilizing Local RedundancyNorbert Seifert. 49-50 [doi]
- False Error Study of On-line Soft Error Detection MechanismsM. Kiran Kumar Reddy, Bharadwaj S. Amrutur, Rubin A. Parekhji. 53-58 [doi]
- Integrating Scan Design and Soft Error Correction in Low-Power ApplicationsMichael E. Imhof, Hans-Joachim Wunderlich, Christian G. Zoellin. 59-64 [doi]
- A Built-In Self-Test Scheme for Soft Error Rate CharacterizationAlodeep Sanyal, Syed M. Alam, Sandip Kundu. 65-70 [doi]
- Budget-Dependent Control-Flow Error DetectionRamtilak Vemu, Jacob A. Abraham. 73-78 [doi]
- Software Self-Testing of a Symmetric Cipher with Error Detection CapabilityPaolo Maistri, Cyril Excoffon, Régis Leveugle. 79-84 [doi]
- A Fault-Tolerant Attitude Determination System Based on COTS DevicesRicardo de Oliveira Duarte, Luiz de Siqueira Martins-Filho, Guilherme F. T. Knop, Ricardo S. Prado. 85-90 [doi]
- A New Approach for Transient Fault Injection Using Symbolic SimulationAshish Darbari, Bashir M. Al-Hashimi, Peter Harrod, Daryl Bradley. 93-98 [doi]
- SystemC-Based Minimum Intrusive Fault Injection Technique with Improved Fault RepresentationRishad A. Shafik, Paul M. Rosinger, Bashir M. Al-Hashimi. 99-104 [doi]
- Special Session 2: Benchmarking and Standardization in Software-Based SER Characterization: Towards an IEEE Task Force?Michael Nicolaidis. 105-106 [doi]
- A Systematical Method of Quantifying SEU FITShi-Jie Wen, Dan Alexandrescu, Renaud Perez. 109-114 [doi]
- Using Low Pass Filters in Mitigation Techniques against Single-Event Transients in 45nm Technology LSIsTaiki Uemura, Ryo Tanabe, Yoshiharu Tosaka, Shigeo Satoh. 117-122 [doi]
- On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFDSobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, Andreas G. Veneris. 123-128 [doi]
- Propagation of Transients Along Sensitizable PathsSreenivas Gangadhar, Michael N. Skoufis, Spyros Tragoudas. 129-134 [doi]
- On the Evaluation of Radiation-Induced Transient Faults in Flash-Based FPGAsNiccolò Battezzati, Simone Gerardin, Andrea Manuzzato, Alessandro Paccagnella, Sana Rezgui, Luca Sterpone, Massimo Violante. 135-140 [doi]
- A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCsWilson J. Perez, Jaime Velasco-Medina, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda. 143-148 [doi]
- A BISR Architecture for Embedded MemoriesKiamal Z. Pekmestzi, Nicholas Axelos, Isidoros Sideris, Nikos K. Moshopoulos. 149-154 [doi]
- Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability ImprovementCostas Argyrides, Fabian Vargas, Marlon Moraes, Dhiraj K. Pradhan. 155-160 [doi]
- Special Session 3 - Panel: SER in Automotive: what is the impact of the AEC Q100-G spec?Tino Heijmen. 161-162 [doi]
- Yield Improvement, Fault-Tolerance to the Rescue?Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. 165-166 [doi]
- Smart Hardening for Round-based Encryption Algorithms: Application to Advanced Encryption StandardCelia López-Ongil, Alejandro Jiménez-Horas, Marta Portela-GarcÃa, Mario GarcÃa-Valderas, Enrique San Millán, Luis Entrena. 167-168 [doi]
- SRAM Cell Design Protected from SEU UpsetsYuriy Shiyanovskii, Francis G. Wolff, Christos A. Papachristou. 169-170 [doi]
- A Modular Memory BIST for Optimized Memory RepairPhilipp Öhler, Alberto Bosio, Giorgio Di Natale, Sybille Hellebrand. 171-172 [doi]
- A Novel GA-Based High-Level Synthesis Technique to Enhance RT-Level Concurrent TestingNaghmeh Karimi, Soheil Aminzadeh, Saeed Safari, Zainalabedin Navabi. 173-174 [doi]
- A New Radiation Hardened by Design Latch for Ultra-Deep-Sub-Micron TechnologiesZhengfeng Huang, Huaguo Liang. 175-176 [doi]
- Basic Architecture for Logic Self RepairTobias Koal, Heinrich Theodor Vierhaus. 177-178 [doi]
- Developing Fault Injection Environment for Complex ExperimentsPiotr Gawkowski, Janusz Sosnowski. 179-181 [doi]
- Development of a Testbench for Validation of DMT and DT2 Fault-Tolerant Architectures on SOI PowerPC7448Michel Pignol, Thierry Parrain, Vincent Claverie, Christian Boléat, Guy Estaves. 182-184 [doi]
- Dynamic Scheduling of Test Routines for Efficient Online Self-Testing of Embedded MicroprocessorsNikolaos G. Bartzoudis, Vasileios Tantsios, Klaus D. McDonald-Maier. 185-187 [doi]
- Fault Tolerant Reversible Finite Field Arithmetic CircuitsJimson Mathew, Jawar Singh, Anas Abu Taleb, Dhiraj K. Pradhan. 188-189 [doi]
- On Line Testing of Single Feedback Bridging Fault in Cluster Based FPGA by Using Asynchronous ElementNachiketa Das, Pranab Roy, Hafizur Rahaman. 190-191 [doi]
- Totally Fault Tolerant RNS Based FIR FiltersSalvatore Pontarelli, Gian-Carlo Cardarilli, Marco Re, Adelio Salsano. 192-194 [doi]
- Special Session 4: Reliability and Circuit SimulationRob Aitken. 195-196 [doi]
- Modeling and Simulation of Circuit Aging in Scaled CMOS DesignYu (Kevin) Kao. 197 [doi]
- Communication Aware Recovery Configurations for Networks-on-ChipClaudia Rusu, Cristian Grecu, Lorena Anghel. 201-206 [doi]
- Reliability in Application Specific Mesh-Based NoC ArchitecturesFatemeh Refan, Homa Alemzadeh, Saeed Safari, Paolo Prinetto, Zainalabedin Navabi. 207-212 [doi]
- On-Line Testing of Lab-on-Chip Using Digital Microfluidic CompactorsYang Zhao, Krishnendu Chakrabarty. 213-218 [doi]
- Self-Configuration and Reachability Metrics in Massively Defective Multiport ChipsPiotr Zajac, Jacques Henri Collet, Andrzej Napieralski. 219-224 [doi]
- Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital CircuitsJorge Semião, Judit Freijedo, Juan J. RodrÃguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. 227-232 [doi]
- On the Detection of SSN-Induced Logic Errors through On-Chip MonitoringFlorence Azaïs, Laurent Larguier, Yves Bertrand, Michel Renovell. 233-238 [doi]
- Guided Probabilistic Checksums for Error Control in Low Power Digital-FiltersMuhammad Mudassar Nisar, Abhijit Chatterjee. 239-244 [doi]
- Soft-Error Vulnerability of Sub-100-nm Flip-FlopsTino Heijmen. 247-252 [doi]
- Variation of SRAM Alpha-Induced Soft Error Rate with Technology NodeDamien Leroy, Rémi Gaillard, Erwin Schäfer, Cyrille Beltrando, Shi-Jie Wen, Richard Wong. 253-257 [doi]
- Deterministic Built-in TPG with Segmented FSMsSamara Sudireddy, Jayawant Kakade, Dimitri Kagaris. 261-266 [doi]
- A Low-Cost Accumulator-Based Test Pattern Generation ArchitectureDimitris Magos, Ioannis Voyiatzis, Steffen Tarnick. 267-272 [doi]
- Directed Random SBST Generation for On-Line Testing of Pipelined ProcessorsAndreas Merentitis, George Theodorou, Mihalis Giorgaras, Nektarios Kranitis. 273-279 [doi]
- SDRAM Architecture & Single Event Effects Revealed with LaserAntonin Bougerol, Florent Miller, Nadine Buard. 283-288 [doi]
- Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGAGaetan Canivet, Jessy Clédière, Jean Baptiste Ferron, Frédéric Valette, Marc Renaudin, Régis Leveugle. 289-294 [doi]
- Dynamic Testing of an SRAM-Based FPGA by Time-Resolved Laser Fault InjectionVincent Pouget, Alexandre Douin, Gilles Foucard, Paul Peronnard, Dean Lewis, Pascal Fouillat, Raoul Velazco. 295-301 [doi]