Table of Contents

• Exploiting a fast and simple ECC for scaling supply voltage in level-1 cachesGulay Yalcin, Emrah Islek, Oyku Tozlu, Pedro Reviriego, Adrián Cristal, Osman S. Unsal, Oguz Ergin. 1-6 [doi]
• Comparative study of defect-tolerant multiplexers for FPGAsArwa Ben Dhia, Mariem Slimani, Lirida A. B. Naviner. 7-12 [doi]
• Online error detection and recovery in dataflow executionTiago A. O. Alves, Sandip Kundu, Leandro A. J. Marzulo, Felipe Maia Galvão França. 9-12 [doi]
• Area-efficient synthesis of fault-secure NoC switchesAtefe Dalirsani, Michael A. Kochte, Hans-Joachim Wunderlich. 13-18 [doi]
• From an analytic NBTI device model to reliability assessment of complex digital circuitsNasim Pour Aryan, A. Listl, Leonhard Heiß, C. Yilmaz, Georg Georgakos, Doris Schmitt-Landsiedel. 19-24 [doi]
• Real-time transient error and induced noise cancellation in linear analog filters using learning-assisted adaptive analog checksumsAlvaro Gómez-Pau, Suvadeep Banerjee, Abhijit Chatterjee. 25-30 [doi]
• Pre-bond testing of weak defects in TSVsDaniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras. 31-36 [doi]
• Customized cell detector for laser-induced-fault detectionFeng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. 37-42 [doi]
• Precise fault-injections using voltage and temperature manipulation for differential cryptanalysisRaghavan Kumar, Philipp Jovanovic, Ilia Polian. 43-48 [doi]
• A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware TrojansSophie Dupuis, Papa-Sidi Ba, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. 49-54 [doi]
• A noise-tolerant master-slave flip-flopYukiya Miura, Yoshihiro Ohkawa. 55-61 [doi]
• New approaches for synthesis of redundant combinatorial logic for selective fault toleranceHao Xie, Li Chen, Rui Liu, Adrian Evans, Dan Alexandrescu, Shi-Jie Wen, Rick Wong. 62-68 [doi]
• A placement strategy for reducing the effects of multiple faults in digital circuitsSamuel N. Pagliarini, Dhiraj K. Pradhan. 69-74 [doi]
• Cost-efficient of a cluster in a mesh SRAM-based FPGASaif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel. 75-80 [doi]
• Towards low-cost fault detection strategy of FPGA configuration memory in real-time systemsMichael Frischke, Andreas J. Rohatschek, Walter Stechele. 81-86 [doi]
• A novel methodology to increase fault tolerance in autonomous FPGA-based systemsStefano Di Carlo, Giulio Gambardella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta, Alessandro Vallero. 87-92 [doi]
• Improved circuitry for soft error correction in combinational logic in pipelined designsMilos Krstic, Stefan Weidling, Vladimir Petrovic, Michael Gössel. 93-98 [doi]
• A new solution to on-line detection of Control Flow ErrorsBoyang Du, Matteo Sonza Reorda, Luca Sterpone, L. Parra, Marta Portela-García, Almudena Lindoso, Luis Entrena. 105-110 [doi]
• Validation of a tool for estimating the effects of soft-errors on modern SRAM-based FPGAsMarco Desogus, Luca Sterpone, David Merodio Codinachs. 111-115 [doi]
• Modified DEC BCH codes for parallel correction of 3-bit errors comprising a pair of adjacent errorsChristian Badack, Thomas Kern, Michael Gössel. 116-121 [doi]
• Double node charge sharing SEU tolerant latch designKaterina Katsarou, Yiorgos Tsiatouhas. 122-127 [doi]
• Improving the significance of probabilistic circuit fault emulationsDavid May, Walter Stechele. 128-133 [doi]
• Error masking with approximate logic circuits using dynamic probability estimationsAntonio Sanchez-Clemente, Luis Entrena, M. Garcia-Valderas. 134-139 [doi]
• Versatile architecture-level fault injection framework for reliability evaluation: A first reportNikos Foutris, Manolis Kaliorakis, Sotiris Tselonis, Dimitris Gizopoulos. 140-145 [doi]
• Framework for economical error recovery in embedded coresGaurang Upasani, Xavier Vera, Antonio González. 146-153 [doi]
• Power-aware optimization of software-based self-test for L1 caches in microprocessorsGeorge Theodorou, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos. 154-159 [doi]
• Fip-flop selection for in-situ slack-time monitoring based on the activation probability of timing-critical pathsSébastien Sarrazin, Samuel Evain, Ivan Miro Panades, Lirida Alves de Barros Naviner, Valentin Gherman. 160-163 [doi]
• Multivariate outlier modeling for capturing customer returns - How simple it can beJeff Tikkanen, Nik Sumikawa, Li-C. Wang, Magdy S. Abadir. 164-169 [doi]
• Fault injection and fault handling: An MPSoC demonstrator using IEEE P1687Kim Petersen, Dimitar Nikolov, Urban Ingelsson, Gunnar Carlsson, Farrokh Ghani Zadegan, Erik Larsson. 170-175 [doi]
• Permanent faults on LIN networks: On-line test generationAnna Vaskova, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Matteo Sonza Reorda. 176-181 [doi]
• A hybrid reliability assessment method and its support of sequential logic modellingSamuel N. Pagliarini, Lirida A. B. Naviner, Jean-François Naviner, Dhiraj K. Pradhan. 182-183 [doi]
• Aging-aware critical paths in deep submicronPhaninder Alladi, Spyros Tragoudas. 184-185 [doi]
• Early assessment of SEU sensitivity through untestable fault identificationLuca Cassano, Hipólito Guzmán-Miranda, Miguel A. Aguirre. 186-189 [doi]
• Timing for virtual TMR in logic circuitsSebastian Müller, Tobias Koal, Mario Schölzel, Heinrich Theodor Vierhaus. 190-193 [doi]
• Preliminary results of SEU fault-injection on multicore processors in AMP modeVanessa Vargas, Pablo Ramos, Wassim Mansour, Raoul Velazco, Nacer-Edinne Zergainoh, Jean-Francois Mehaut. 194-197 [doi]
• Novel self-test methods to reduce on-chip memory requirements and improved test coveragePrakash Narayanan, Satish Ravichandran, Balaji Ramayanam. 198-199 [doi]
• FF-DICE: An 8T soft-error tolerant cell using Independent Dual Gate SOI FinFETsNicholas Axelos, Nikolaos Eftaxiopoulos-Sarris, Georgios Zervakis, Kostas Tsoumanis, Kiamal Z. Pekmestzi. 200-201 [doi]
• Effect of ionizing radiation on TRNGs for safe telecommunications: Robustness and randomnessHonorio Martin, Anna Vaskova, Celia López-Ongil, Enrique San Millán, Marta Portela-García. 202-205 [doi]
• An innovative standard cells remapping method for in-circuit critical parameters monitoringLoic Welter, Philippe Dreux, Hassen Aziza, Jean Michel Portal. 206-209 [doi]
• Fault injection in GPGPU cores to validate and debug robust parallel applicationsM. De Carvalho, Davide Sabena, Matteo Sonza Reorda, Luca Sterpone, Paolo Rech, Luigi Carro. 210-211 [doi]
• Multi-abstraction level signature generation and comparison based on radiation single event upsetChristelle Hobeika, S. Pichette, M. A. Leonard, Claude Thibeault, Jean-François Boland, Yves Audet. 212-215 [doi]
• Managing SER costs of complex systems through Linear ProgrammingDan Alexandrescu, Nematollah Bidokhti, Andy Yu, Adrian Evans, Enrico Costenaro. 216-219 [doi]
• Two complementary approaches for studying the effects of SEUs on HDL-based designsWassim Mansour, Miguel A. Aguirre, Hipólito Guzmán-Miranda, J. Barrientos, Raoul Velazco. 220-221 [doi]
• Dependable reconfigurable space systems: Challenges, new trends and case studiesAntonis M. Paschalis, Harald Michalik, Nektarios Kranitis, Celia Lopez-Ongil, Pedro Reviriego Vasallo. 222-227 [doi]
• Cross-layer early reliability evaluation: Challenges and promisesStefano Di Carlo, Alessandro Vallero, Dimitris Gizopoulos, Giorgio Di Natale, Antonio González, R. Canal, Riccardo Mariani, M. Pipponzi, Arnaud Grasset, Philippe Bonnot, Frank Reichenbach, G. Rafiq, T. Loekstad. 228-233 [doi]
• Solutions for the self-adaptation of communicating systems in operationMartin Andraud, Anthony Deluthault, Mouhamadou Dieng, Florence Azaïs, Serge Bernard, Philippe Cauvet, Mariane Comte, Thibault Kervaon, Vincent Kerzerho, Salvador Mir, Paul-Henri Pugliesi-Conti, Michel Renovell, Fabien Soulier, Emmanuel Simeu, Haralampos-G. D. Stratigopoulos. 234-239 [doi]