Abstract is missing.
- On the robustness of DCT-based compression algorithms for space applicationsSerhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Görschwin Fey, J.-G. Mess, R. Schmidt. 1-2 [doi]
- Analytic models for crossbar read operationAdedotun Adeyemo, Xiaohan Yang, Anu Bala, Jimson Mathew, Abusaleh M. Jabir. 3-4 [doi]
- A fault-tolerant sequential circuit design for SAFs and PDFs soft errorsAnzhela Matrosova, Sergey Ostanin, Irina Kirienko, Ekaterina Nikolaeva. 5-6 [doi]
- ACM: Accurate crosstalk modeling to predict channel delay in Network-on-ChipsZeinab Mahdavi, Zahra Shirmohammadi, Seyed Ghassem Miremadi. 7-8 [doi]
- An on-line test solution for addressing interconnect shorts in on-chip networksBiswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas. 9-12 [doi]
- An soft error propagation analysis considering logical masking effect on re-convergent pathShuhei Yoshida, Go Matsukawa, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto. 13-16 [doi]
- Analysis of BTI aging of level shiftersJiajing Cai, Basel Halak, Daniele Rossi. 17-18 [doi]
- Cache-aware reliability evaluation through LLVM-based analysis and fault injectionMaha Kooli, Giorgio Di Natale, Alberto Bosio. 19-22 [doi]
- Comparison of RTL fault models for the robustness evaluation of aerospace FPGA devicesRomain Champon, Vincent Beroulle, Athanasios Papadimitriou, David Hély, Gilles Genevrier, Frederic Cezilly. 23-24 [doi]
- Efficient fault tolerant parallel matrix-vector multiplicationsZhen Gao, Pedro Reviriego, Juan Antonio Maestro. 25-26 [doi]
- Resilient random modulo cache memories for probabilistically-analyzable real-time systemsDavid Trilla, Carles Hernández, Jaume Abella, Francisco J. Cazorla. 27-32 [doi]
- Statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operationManish Rana, Ramon Canal, Esteve Amat, Antonio Rubio. 33-38 [doi]
- Variations-tolerant 9T SRAM circuit with robust and low leakage SLEEP modeHailong Jiao, Yongmin Qiu, Volkan Kursun. 39-42 [doi]
- Hot-carrier and BTI damage distinction for high performance digital application in 28nm FDSOI and 28nm LP CMOS nodesA. Bravaix, M. Saliva, Florian Cacho, X. Federspiel, C. Ndiaye, S. Mhira, E. Kussener, E. Pauly, Vincent Huard. 43-46 [doi]
- Activity profiling: Review of different solutions to develop reliable and performant designFlorian Cacho, Ahmed Benhassain, S. Mhira, Ajith Sivadasan, Vincent Huard, P. Cathelin, V. Knopik, A. Jain, C. R. Parthasarathy, Lorena Anghel. 47-50 [doi]
- Fine-grain analysis of the parameters involved in aging of digital circuitsBoukary Ouattara, Olivier Héron, Chiara Sandionigi. 51-53 [doi]
- Evaluating application-aware soft error effects in digital circuits without fault injections or probabilistic computationsK. Chibani, Michele Portolan, Régis Leveugle. 54-59 [doi]
- Modeling RTL fault models behavior to increase the confidence on TSIM-based fault injectionJaime Espinosa, Carles Hernández, Jaume Abella. 60-65 [doi]
- Revisiting software-based soft error mitigation techniques via accurate error generation and propagation modelsMojtaba Ebrahimi, Maryam Rashvand, Firas Kaddachi, Mehdi Baradaran Tahoori, Giorgio Di Natale. 66-71 [doi]
- ISA-independent post-silicon validation for the address translation mechanisms of modern microprocessorsGeorge Papadimitriou, Athanasios Chatzidimitriou, Dimitris Gizopoulos, Ronny Morad. 72-77 [doi]
- Flexible in-silicon checking of run-time programmable assertionsYumin Zhou, Oliver Bringmann, Wolfgang Rosenstiel. 78-83 [doi]
- Hardware-simulation correlation of timing error detection performance of software-based error detection mechanismsYutaka Masuda, Masanori Hashimoto, Takao Onoye. 84-89 [doi]
- On-line write margin estimator to monitor performance degradation in SRAM coresBartomeu Alorda, C. Carmona, Gabriel Torrens, Sebastiàn A. Bota. 90-95 [doi]
- Recovery of performance degradation in defective branch target buffersFilippos Filippou, Georgios Keramidas, Michail Mavropoulos, Dimitris Nikolos. 96-102 [doi]
- NBTI aging evaluation of PUF-based differential architecturesMohd Syafiq Mispan, Basel Halak, Mark Zwolinski. 103-108 [doi]
- REMO: Redundant execution with minimum area, power, performance overhead fault tolerant architectureShoba Gopalakrishnan, Virendra Singh. 109-114 [doi]
- Susceptible workload driven selective fault tolerance using a probabilistic fault modelMauricio D. Gutierrez, Vasileios Tenentes, Tom J. Kazmierski. 115-120 [doi]
- Temperature- and aging-resistant inverter for robust and reliable time to digital circuit designs in a 65nm bulk CMOS processKonstantin Tscherkaschin, Theodor Hillebrand, Maike Taddiken, Steffen Paul, Dagmar Peters-Drolshagen. 121-125 [doi]
- Leakage mitigation for low power microcontroller design in 40nm for Internet-of-Things (IoT)Ajay Kapoor, Nur Engin, Johan Verdaasdonk. 126-129 [doi]
- Advanced double-sampling architecturesMichael Nicolaidis, Michael G. Dimopoulos. 130-132 [doi]
- Pushing the limits: How fault tolerance extends the scope of approximate computingHans-Joachim Wunderlich, Claus Braun, Alexander Scholl. 133-136 [doi]
- Tackling long duration transients in sequential logicErol Koser, Walter Stechele. 137-142 [doi]
- HLS-based sensitivity-inductive soft error mitigation for satellite communication systemsXiang Chen, Wenhui Yang, Ming Zhao, Jing Wang 0001. 143-148 [doi]
- An efficient LDPC encoder architecture for space applicationsDimitris Theodoropoulos, Nektarios Kranitis, Antonios Paschalis. 149-154 [doi]
- Scalable FPGA graph model to detect routing faultsLuca Sterpone, Gianpiero Cabodi, S. F. Finocchiaro, Carmelo Loiacono, F. Savarese, Boyang Du. 155-160 [doi]
- Concurrent error detection and tolerance in Kalman filters using encoded state and statistical covariance checksSujay Pandey, Suvadeep Banerjee, Abhijit Chatterjee. 161-166 [doi]
- Automatic generation of stimuli for fault diagnosis in IEEE 1687 networksRiccardo Cantoro, Mehrdad Montazeri, Matteo Sonza Reorda, Farrokh Ghani Zadegan, Erik Larsson. 167-172 [doi]
- RIIF-2: Toward the next generation reliability information interchange formatAlessandro Savino, S. Di Carlo, Alessandro Vallero, Gianfranco Politano, Dimitris Gizopoulos, Adrian Evans. 173-178 [doi]
- STT-MTJ-based TRNG with on-the-fly temperature/current variation compensationElena Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto. 179-184 [doi]
- SET response of a SEL protection switch for 130 and 250 nm CMOS technologiesMarko S. Andjelkovic, Aleksandar Ilic, Vladimir Petrovic, Miljana Nenadovic, Zoran Stamenkovic, Goran S. Ristic. 185-190 [doi]
- Reusing logic masking to facilitate path-delay-based hardware Trojan detectionArash Nejat, David Hély, Vincent Beroulle. 191-192 [doi]
- Evaluation of machine learning algorithms for image quality assessmentGhislain Takam Tchendjou, Rshdee Alhakim, Emmanuel Simeu, Fritz Lebowsky. 193-194 [doi]
- An odd-even scheme to prevent a packet from being corrupted and dropped in fault tolerant NoCsBiswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka. 195-198 [doi]
- Feasibility of software-based repair for program memoriesPatryk Skoncej, Felix Mühlbauer, Felix Kubicek, Lukas Schroder, Mario Schölzel. 199-202 [doi]
- Hardware Trojans classification for gate-level netlists based on machine learningKento Hasegawa, Masaru Oya, Masao Yanagisawa, Nozomu Togawa. 203-206 [doi]
- On the influence of compiler optimizations in the fault tolerance of embedded systemsAlejandro Serrano-Cases, Jose Isaza-Gonzalez, Sergio Cuenca-Asensi, Antonio Martínez-Álvarez. 207-208 [doi]
- Online monitoring of NBTI and HCD in beta-multiplier circuitsTheodor Hillebrand, Maike Taddiken, Konstantin Tscherkaschin, Steffen Paul, Dagmar Peters-Drolshagen. 209-210 [doi]
- Online monitoring of the maximum angle error in AMR sensorsAndreina Zambrano, Hans G. Kerkhoff. 211-212 [doi]
- Online time interference detection in mixed-criticality applications on multicore architectures using performance countersStefano Esposito, Massimo Violante, Marco Sozzi, Marco Terrone, Massimo Traversone. 213-214 [doi]
- Power-side-channel analysis of carbon nanotube FET based designChandra K. H. Suresh, Bodhisatwa Mazumdar, Sk Subidh Ali, Ozgur Sinanoglu. 215-218 [doi]
- Redesign for untrusted gate-level netlistsMasaru Oya, Masao Yanagisawa, Nozomu Togawa. 219-220 [doi]
- Single-event performance of differential flip-flop designs and hardening implicationR. M. Chen, E. X. Zhang, B. L. Bhuva. 221-226 [doi]
- Conditional soft-edge flip-flop for SET mitigationPanagiotis Sismanoglou, Dimitris Nikolos. 227-232 [doi]
- A high performance scan flip-flop design for serial and mixed mode scan testSatyadev Ahlawat, Jaynarayan T. Tudu, Anzhela Matrosova, Virendra Singh. 233-238 [doi]
- Binary decision diagram to design balanced secure logic stylesHyunmin Kim, Seokhie Hong, Bart Preneel, Ingrid Verbauwhede. 239-244 [doi]
- A hybrid self-diagnosis mechanism with defective nodes locating and attack detection for parallel computing systemsLake Bu, Mark G. Karpovsky. 245-250 [doi]
- Hardware enlightening: No where to hide your Hardware Trojans!Mohammad Saleh Samimi, Ehsan Aerabi, Zahra Kazemi, Mahdi Fazeli, Ahmad Patooghy. 251-256 [doi]