Abstract is missing.
- Array Processor with Multiple BroadcastingViktor K. Prasanna, Cauligi S. Raghavendra. 2-10
- Matrix Multiplication in an Interleaved Array Processing ArchitectureG. Wolf, J. Robert Jump. 11-17
- PIPE: A VLSI Decoupled ArchitectureJames R. Goodman, Jian-tu Hsieh, Koujuch Liou, Andrew R. Pleszkun, P. B. Schechter, Honesty C. Young. 20-27
- TIDBITS: Speedup Via Time-Delay Bit-Slicing in ALU Design for VLSI TechnologyPeter Y.-T. Hsu, Joseph T. Rahmeh, Edward S. Davidson, Jacob A. Abraham. 28-35
- Implementation of Precise Interrupts in Pipelined ProcessorsJames E. Smith, Andrew R. Pleszkun. 36-44
- High-Speed Top-of-Stack Scheme for VLSI Processor: a Management Algorithm and Its AnalysisMakoto Hasegawa, Yoshiharu Shigei. 48-54
- Analyzing Multiple Register SetsCharles Y. Hitchcock III, Brinkley Sprunt. 55-63
- Cache Evaluation and the Impact of Workload ChoiceAlan Jay Smith. 64-73
- Architecture of the Symbolics 3600David A. Moon. 76-83
- Parallel Garbage Collection Without Synchronization OverheadAshwin Ram, Janak H. Patel. 84-90
- An Efficient LISP-Execution Architecture with a New Representation for List StructuresGurindar S. Sohi, Edward S. Davidson, Janak H. Patel. 91-98
- (SM)²-II: A New Version of the Sparse Matrix Solving MachineHideharu Amano, Taisuke Boku, Tomohiro Kudoh, Hideo Aiso. 100-107
- Models for Use in the Design of Macro-Pipelined Parallel ProcessorsBradley Warren Smith, Howard Jay Siegel. 116-123
- Issues Related to MIMD Shared-memory Computers: The NYU Ultracomputer ApproachJan Edler, Allan Gottlieb, Clyde P. Kruskal, Kevin P. McAuliffe, Larry Rudolph, Marc Snir, Patricia J. Teller, James Wilson. 126-135
- MU6V: A Parallel Vector Processing SystemRoland N. Ibbett, P. C. Capon, Nigel P. Topham. 136-144
- A Decentralized Control, Highly Concurrent MultiprocessorStephen F. Lundstrom. 145-151
- An Object Oriented ArchitectureWilliam J. Dally, James T. Kajiya. 154-161
- Tagged Architecture: How Compelling Are its Advantages?Edward F. Gehringer, James Leslie Keedy. 162-170
- Performance Studies of a Prolog Machine ArchitectureTep P. Dobry, Alvin M. Despain, Yale N. Patt. 180-190
- Design of a High-speed Prolog Machine (HPM)Ryosei Nakazaki, Akihiko Konagaya, Shinichi Habata, Hideo Shimazu, Mamoru Umemura, Masahiro Yamamoto, Minoru Yokota, Takashi Chikayama. 191-197
- A Hardware Unification Unit: Design and AnalysisNam Sung Woo. 198-205
- The Synapse N+1 System: Architectural Characteristics and Performance Data of a Tightly-Coupled Multiprocessor SystemElliot Nestle, Armond Inselberg. 233-239
- An Architecture for High Volume Transaction ProcessingRobert W. Horst, Timothy C. K. Chou. 240-245
- A Hardware Pipeline Algorithm for Relational Database Operation and Its Implementation Using Dedicated HardwareShigeo Kamiya, Kazuhide Iwata, Hiroshi Sakai, Susumu Matsuda, Shigeki Shibayama, Kunio Murakami. 250-257
- A Distributed Multiple-Response Resolver for Value-Ordered RetrievalDik Lun Lee. 258-265
- Dynamic, Distributed Resource Configuration on SW-BanyansJohn Feo, Roy M. Jenevein, James C. Browne. 268-275
- Implementing A Cache Consistency ProtocolRandy H. Katz, Susan J. Eggers, David A. Wood, C. L. Perkins, R. G. Sheldon. 276-283
- A Technique for Reducing Synchronization Overhead in Large Scale MultiprocessorsZhiyuan Li, Walid A. Abu-Sufah. 284-291
- The TransputerColin Whitby-Strevens. 292-300
- A Systolic Multiplier Unit and Its VLSI DesignAli R. Hurson, Behrooz Shirazi. 302-309
- A Language for the Simulation of Systolic ArchitecturesRami G. Melhem. 310-314
- A Versatile Systolic Array for Matrix ComputationsHenry Y. H. Chuang, Guo He. 315-322
- The Hughes Data Flow Multiprocessor: Architecture for Efficient Signal and Data ProcessingRex W. Vedder, Dennis Finn. 324-332
- An Abstract Parallel Graph Reduction MachineKenneth R. Traub. 333-341
- Data Flow on a Queue MachineBruno R. Preiss, V. Carl Hamacher. 342-351
- Methods for Handling Structures in Data-Flow SystemsJean-Luc Gaudiot. 352-358
- The de Bruijn Multiprocessor Network: A Versatile Sorting NetworkMaheswara R. Samatham, Dhiraj K. Pradhan. 360-367
- Fault-Tolerant Scheme for Multistage Interconnection NetworksNian-Feng Tzeng, Pen-Chung Yew, Chuan-Qi Zhu. 368-375
- Design and Analysis of Fault-Tolerant Multistage Interconnection Networks With Low Link ComplexityVijay P. Kumar, Sudhakar M. Reddy. 376-386
- The Performance Analysis of Partitioned Circuit Switched Multistage Interconnection NetworksNathaniel J. Davis IV, Howard Jay Siegel. 387-394
- The Influence of Parallel Decomposition Strategies on the Performance of Multiprocessor SystemsDalibor F. Vrsalovic, Edward F. Gehringer, Zary Segall, Daniel P. Siewiorek. 396-405
- Performance Prediction Tools for Cedar: A Multiprocessor SupercomputerWalid A. Abu-Sufah, Alex Y. Kwok. 406-413
- Analysis and Simulation of Multiplexed Single-Bus Networks With and Without BufferingJosé M. Llabería, Mateo Valero, Enrique Herrada Lillo, Jesús Labarta. 414-421
- Performance of a Message-Based MultiprocessorJohn Sanguinetti, B. Kumar. 424-425