Table of Contents

• Critical Issues in Mapping Neural Networks on Message-Passing MulticomputersJoydeep Ghosh, Kai Hwang. 3-11
• Multinomial Conjunctoid Statistical Learning MachinesYoshiyasu Takefuji, Robert J. Jannarone, Yong B. Cho, Tatung Chen. 12-17
• A Bit-Plane Architecture for Optical Computing with Two-Dimensional Symbolic SubstitutionAhmed Louri, Kai Hwang. 18-27
• The Reconfigurable Arithmetic ProcessorStuart Fiske, William J. Dally. 30-36
• The Performance Potential of Multiple Functional Unit ProcessorsAndrew R. Pleszkun, Gurindar S. Sohi. 37-44
• Exploiting Parallel Microprocessor Microarchitectures With a Compiler Code GeneratorWen-mei W. Hwu, Pohua P. Chang. 45-53
• Analysis of Memory Referencing Behavior For Design of Local MemoriesGeoffrey D. McNiven, Edward S. Davidson. 56-63
• Performance Evaluation of On-Chip Register and Cache OrganizationsRichard J. Eickemeyer, Janak H. Patel. 64-72
• On the Inclusion Properties for Multi-Level Cache HierarchiesJean-Loup Baer, Wen-Hann Wang. 73-80
• A Simulation Study of Two-Level CachesRobert T. Short, Henry M. Levy. 81-88
• Hyperswitch Network for the Hypercube ComputerE. Chow, H. Madan, J. Peterson, Dirk Grunwald, Daniel A. Reed. 90-99
• Analysis of Bus Hierarchies for MultiprocessorsDonald C. Winsor, Trevor N. Mudge. 100-107
• Extra Group Network: A Cost-Effective Fault-Tolerant Multistage Interconnection NetworkSizheng Wei, Gyungho Lee. 108-115
• A Partial-Multiple-Bus Computer Structure with Improved Cost-EffectivenessHong Jiang, Kenneth C. Smith. 116-122
• Flagship: A Parallel Architecture for Declarative ProgrammingIan Watson, Viv Woods, Paul Watson, Richard Banach, Mark Greenberg, John Sargeant. 124-130
• Toward a Dataflow/von Neumann Hybrid ArchitectureRobert A. Iannucci. 131-140
• Resource Requirements of Dataflow ProgramsDavid E. Culler, Arvind. 141-150
• Priority-Driven, Preemptive I/O Controllers for Real-Time SystemsBrinkley Sprunt, David Kirk, Lui Sha. 152-159
• A Kernel-independent, Pipelined Architecture for Real-Time 2-D ConvolutionShridhar B. Shukla, Dharma P. Agrawal. 160-166
• Exploiting Bit Level Concurrency in Real-Time Geometric Feature ExtractionsWentai Liu, Tong-Fei Yeh, William E. Batchelor, Ralph K. Cavin III. 167-174
• Measuring VAX 8800 Performance with a Histogram Hardware MonitorDouglas W. Clark, Peter J. Bannon, James B. Keller. 176-185
• Multiprocessor Cache Analysis Using ATUMRichard L. Sites, Anant Agarwal. 186-195
• Trade-offs Between Devices and Paths in Achieving Disk InterleavingSpencer W. Ng, Dorothy Lang, Robert Selinger. 196-201
• Design of a Concurrent Computer for Solving Systems of Linear EquationsK. Jainandunsing, Ed F. Deprettere. 204-211
• The White Dwarf: A High-Performance Application-Specific ProcessorAndrew Wolfe, Mauricio Breternitz Jr., Chriss Stephens, A. L. Ting, D. B. Kirk, Ronald P. Bianchini Jr., John Paul Shen. 212-222
• Solving Partial Differential Equations in a Data-Driven Multiprocessor EnvironmentJean-Luc Gaudiot, C. M. Lin, M. Hosseiniyar. 223-230
• Scrambled Storage for Parallel Memory SystemsDe-Lei Lee. 232-239
• The Architecture of a Linda CoprocessorVenkatesh Krishnaswamy, Sudhir Ahuja, Nicholas Carriero, David Gelernter. 240-249
• Deadlock Avoidance for Systolic CommunicationH. T. Kung. 252-260
• Cache Performance of Vector ProcessorsKimming So, Vittorio Zecca. 261-268
• Distributed Round-Robin and First-Come First-Serve Protocols and Their Application to Multiprocessor Bus ArbitrationMary K. Vernon, Udi Manber. 269-277
• An Evaluation of Directory Schemes for Cache CoherenceAnant Agarwal, Richard Simoni, John L. Hennessy, Mark Horowitz. 280-289
• Performance Tradeoffs in Cache DesignSteven A. Przybylski, Mark Horowitz, John L. Hennessy. 290-298
• A Cache Coherence Scheme With Fast Selective InvalidationHoichi Cheong, Alexander V. Veidenbaum. 299-307
• An Accurate and Efficient Performance Analysis Technique for Multiprocessor Snooping Cache-Consistency ProtocolsMary K. Vernon, Edward D. Lazowska, John Zahorjan. 308-315
• Destination Tag Routing Techniques Based on a State Model for the IADM NetworkDarwen Rau, José A. B. Fortes, Howard Jay Siegel. 318-324
• Regular CC-Banyan NetworksDoug W. Kim, G. Jack Lipovski, Alfred C. Hartmann, Roy M. Jenevein. 325-332
• High-Performance Multi-Queue Buffers for VLSI Communication SwitchesYuval Tamir, Gregory L. Frazier. 343-354
• A Cache-based Message Passing Scheme for a Shared-bus MultiprocessorBruno R. Preiss, V. Carl Hamacher. 358-364
• IMPULSE: A High Performance Processing Unit for Multiprocessors for Scientific CalculationTaisuke Boku, Shigehiro Nomura, Hideharu Amano. 365-372
• A Characterization of Sharing in Parallel Programs and Its Application to Coherency Protocol EvaluationSusan J. Eggers, Randy H. Katz. 373-382
• A Fetch-And-Op Implementation for Parallel ComputersG. Jack Lipovski, Paul Vaughan. 384-392
• Synchronizing Processors Through Memory Requests in a Tightly Coupled MultiprocessorAndré Seznec, Yvon Jégou. 393-400
• Design and Performance of Special Purpose Hardware for Time WarpRichard Fujimoto, Jya-Jang Tsai, Ganesh Gopalakrishnan. 401-408
• The VMP Multiprocessor: Initial Experience, Refinements and Performance EvlauationDavid R. Cheriton, Anoop Gupta, Patrick D. Boyle, Hendrik A. Goosen. 410-421
• The Wisconsin Multicube: A New Large-Scale Cache-Coherent MultiprocessorJames R. Goodman, Philip J. Woest. 422-431
• MASA: A Multithreaded Processor Architecture for Parallel Symbolic ComputingRobert H. Halstead Jr., Tetsuya Fujita. 443-451
• Parallel Architecture for OPS5Philip L. Butler, J. D. Allen Jr., Donald W. Bouldin. 452-457