Abstract is missing.
- Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context SwitchesMarius Evers, Po-Yung Chang, Yale N. Patt. 3-11 [doi]
- Cliff Young, J. Bradley Chen, Michael D. Smith: An Analysis of Dynamic Branch Prediction Schemes on System WorkloadsNicholas C. Gloy. 12-21 [doi]
- Correlation and Aliasing in Dynamic Branch PredictorsStuart Sechrest, Chih-Chieh Lee, Trevor N. Mudge. 22-32 [doi]
- Decoupled Hardware Support for Distributed Shared MemorySteven K. Reinhardt, Robert W. Pfile, David A. Wood. 34-43 [doi]
- MGS: A Multigrain Shared Memory SystemDonald Yeung, John Kubiatowicz, Anant Agarwal. 44-55 [doi]
- COMA: An Opportunity for Building Fault-Tolerant Scalable Shared Memory MultiprocessorsChristine Morin, Alain Gefflaut, Michel Banâtre, Anne-Marie Kermarrec. 56-65 [doi]
- Evaluation of Design Alternatives for a Multiprocessor MicroprocessorBasem A. Nayfeh, Lance Hammond, Kunle Olukotun. 67-77 [doi]
- Memory Bandwidth Limitations of Future MicroprocessorsDoug Burger, James R. Goodman, Alain Kägi. 78-89 [doi]
- Missing the Memory Wall: The Case for Processor/Memory IntegrationAshley Saulsbury, Fong Pong, Andreas Nowatzyk. 90-101 [doi]
- Don t Use the Page Number, But a Pointer To ItAndré Seznec. 104-113 [doi]
- The Difference-bit CacheToni Juan, Tomás Lang, Juan J. Navarro. 114-120 [doi]
- Understanding Application Performance on Shared Virtual Memory SystemsLiviu Iftode, Jaswinder Pal Singh, Kai Li. 122-133 [doi]
- Application and Architectural Bottlenecks in Large Scale Distributed Shared Memory MachinesChris Holt, Jaswinder Pal Singh, John L. Hennessy. 134-145 [doi]
- Increasing Cache Port Efficiency for Dynamic Superscalar MicroprocessorsKenneth M. Wilson, Kunle Olukotun, Mendel Rosenblum. 147-157 [doi]
- DCD - Disk Caching Disk: A New Approach for Boosting I/O PerformanceYiming Hu, Qing Yang. 169-178 [doi]
- Polling Watchdog: Combining Polling and Interrupts for Efficient Message HandlingOlivier Maquelin, Guang R. Gao, Herbert H. J. Hum, Kevin B. Theobald, Xinmin Tian. 179-188 [doi]
- Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading ProcessorDean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm. 191-202 [doi]
- Evaluation of Multithreaded Uniprocessors for Commercial Application EnvironmentsRichard J. Eickemeyer, Ross E. Johnson, Steven R. Kunkel, Mark S. Squillante, Shiafun Liu. 203-212 [doi]
- Performance Comparison of ILP Machines with Cycle Time EvaluationTetsuya Hara, Hideki Ando, Chikako Nakanishi, Masao Nakaya. 213-224 [doi]
- Rotating Combined Queueing (RCQ): Bandwidth and Latency Guarantees in Low-Cost, High-Performance NetworksJae H. Kim, Andrew A. Chien. 226-236 [doi]
- A Router Architecture for Real-Time Point-to-Point NetworksJennifer Rexford, John Hall, Kang G. Shin. 237-246 [doi]
- Coherent Network Interfaces for Fine-Grain CommunicationShubhendu S. Mukherjee, Babak Falsafi, Mark D. Hill, David A. Wood. 247-258 [doi]
- Informing Memory Operations: Providing Memory Performance Feedback in Modern ProcessorsMark Horowitz, Margaret Martonosi, Todd C. Mowry, Michael D. Smith. 260-270 [doi]
- Instruction Prefetching of Systems Codes with Layout Optimized for Reduced Cache MissesChun Xia, Josep Torrellas. 271-282 [doi]
- Compiler and Hardware Support for Cache Coherence in Large-Scale Multiprocessors: Design Considerations and Performance StudyLynn Choi, Pen-Chung Yew. 283-294 [doi]
- Early Experience with Message-Passing on the SHRIMP MulticomputerEdward W. Felten, Richard Alpert, Angelos Bilas, Matthias A. Blumrich, Douglas W. Clark, Stefanos N. Damianakis, Cezary Dubnicki, Liviu Iftode, Kai Li. 296-307 [doi]
- STiNG: A CC-NUMA Computer System for the Commercial MarketplaceTom Lovett, Russell M. Clapp. 308-317 [doi]