Table of Contents

• Architecture for Protecting Critical Secrets in MicroprocessorsRuby B. Lee, Peter C. S. Kwan, John Patrick McGregor, Jeffrey S. Dwoskin, Zhenghong Wang. 2-13 [doi]
• High Efficiency Counter Mode Security Architecture via Prediction and PrecomputationWeidong Shi, Hsien-Hsin S. Lee, Mrinmoy Ghosh, Chenghuai Lu, Alexandra Boldyreva. 14-24 [doi]
• Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random FunctionsG. Edward Suh, Charles W. O Donnell, Ishan Sachdev, Srinivas Devadas. 25-36 [doi]
• Disk Drive Roadmap from the Thermal Perspective: A Case for Dynamic Thermal ManagementSudhanva Gurumurthi, Anand Sivasubramaniam, Vivek K. Natarajan. 38-49 [doi]
• Direct Cache Access for High Bandwidth Network I/ORam Huggahalli, Ravi R. Iyer, Scott Tetrick. 50-59 [doi]
• Deconstructing Commodity Storage ClustersHaryadi S. Gunawi, Nitin Agrawal, Andrea C. Arpaci-Dusseau, Remzi H. Arpaci-Dusseau, Jiri Schindler. 60-71 [doi]
• A Robust Main-Memory Compression SchemeMagnus Ekman, Per Stenström. 74-85 [doi]
• Continuous OptimizationBrian Fahs, Todd M. Rafacz, Sanjay J. Patel, Steven S. Lumetta. 86-97 [doi]
• RENO - A Rename-Based Instruction OptimizerVlad Petric, Tingting Sha, Amir Roth. 98-109 [doi]
• A High Throughput String Matching Architecture for Intrusion Detection and PreventionLin Tan, Timothy Sherwood. 112-122 [doi]
• A Tree Based Router Search Engine Architecture with Single Port MemoriesFlorin Baboescu, Dean M. Tullsen, Grigore Rosu, Sumeet Singh. 123-133 [doi]
• An Integrated Memory Array Processor Architecture for Embedded Image Recognition SystemsShorin Kyo, Shin ichiro Okazaki, Tamio Arai. 134-145 [doi]
• Design and Evaluation of Hybrid Fault-Detection SystemsGeorge A. Reis, Jonathan Chang, Neil Vachharajani, Ram Rangan, David I. August, Shubhendu S. Mukherjee. 148-159 [doi]
• Rescue: A Microarchitecture for Testability and Defect ToleranceEthan Schuchman, T. N. Vijaykumar. 160-171 [doi]
• Opportunistic Transient-Fault DetectionMohamed A. Gomaa, T. N. Vijaykumar. 172-183 [doi]
• An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-ArchitecturesSteven Balensiefer, Lucas Kreger-Stickles, Mark Oskin. 186-196 [doi]
• Energy Optimization of Subthreshold-Voltage Sensor Network ProcessorsLeyla Nazhandali, Bo Zhai, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Sanjay Pant, Todd M. Austin, David Blaauw. 197-207 [doi]
• An Ultra Low Power System Architecture for Sensor Network ApplicationsMark Hempstead, Nikhil Tripathi, Patrick Mauro, Gu-Yeon Wei, David Brooks. 208-219 [doi]
• Temporal Streaming of Shared MemoryThomas F. Wenisch, Stephen Somogyi, Nikolaos Hardavellas, Jangwoo Kim, Anastassia Ailamaki, Babak Falsafi. 222-233 [doi]
• RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based CoherenceAndreas Moshovos. 234-245 [doi]
• Improving Multiprocessor Performance with Coarse-Grain Coherence TrackingJason F. Cantin, Mikko H. Lipasti, James E. Smith. 246-257 [doi]
• Improving Program Efficiency by Packing Instructions into RegistersStephen Hines, Joshua Green, Gary S. Tyson, David B. Whalley. 260-271 [doi]
• An Architecture Framework for Transparent Instruction Set Customization in Embedded ProcessorsNathan Clark, Jason A. Blome, Michael L. Chu, Scott A. Mahlke, Stuart Biles, Krisztián Flautner. 272-283 [doi]
• BugNet: Continuously Recording Program Execution for Deterministic Replay DebuggingSatish Narayanasamy, Gilles Pokam, Brad Calder. 284-295 [doi]
• Mitigating Amdahl s Law through EPI ThrottlingMurali Annavaram, Ed Grochowski, John Paul Shen. 298-309 [doi]
• Increased Scalability and Power Efficiency by Using Multiple Speed PipelinesEmil Talpes, Diana Marculescu. 310-321 [doi]
• Energy-Effectiveness of Pre-Execution and Energy-Aware P-Thread SelectionVlad Petric, Amir Roth. 322-333 [doi]
• Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip MultiprocessorsMichael Zhang, Krste Asanovic. 336-345 [doi]
• Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip MultiprocessorsEvan Speight, Hazim Shafi, Lixin Zhang, Ramakrishnan Rajamony. 346-356 [doi]
• Optimizing Replication, Communication, and Capacity Allocation in CMPsZeshan Chishti, Michael D. Powell, T. N. Vijaykumar. 357-368 [doi]
• Techniques for Efficient Processing in Runahead Execution EnginesOnur Mutlu, Hyesoon Kim, Yale N. Patt. 370-381 [doi]
• Piecewise Linear Branch PredictionDaniel A. Jiménez. 382-393 [doi]
• Analysis of the O-GEometric History Length Branch PredictorAndré Seznec. 394-405 [doi]
• Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and ScalingRakesh Kumar, Victor V. Zyuban, Dean M. Tullsen. 408-419 [doi]
• Microarchitecture of a High-Radix RouterJohn Kim, William J. Dally, Brian Towles, Amit K. Gupta. 420-431 [doi]
• Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh NetworksDaeho Seo, Akif Ali, Won-Taek Lim, Nauman Rafique, Mithuna Thottethodi. 432-443 [doi]
• Scalable Load and Store Processing in Latency Tolerant ProcessorsAmit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan, Konrad K. Lai. 446-457 [doi]
• Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load OptimizationAmir Roth. 458-468 [doi]
• Store Buffer Design in First-Level Multibanked Data CachesEnrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería. 469-480 [doi]
• Dynamic Verification of Sequential ConsistencyAlbert Meixner, Daniel J. Sorin. 482-493 [doi]
• Virtualizing Transactional MemoryRavi Rajwar, Maurice Herlihy, Konrad K. Lai. 494-505 [doi]
• The Impact of Performance Asymmetry in Emerging Multicore ArchitecturesSaisanthosh Balakrishnan, Ravi Rajwar, Michael Upton, Konrad K. Lai. 506-517 [doi]
• Exploiting Structural Duplication for Lifetime Reliability EnhancementJayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers. 520-531 [doi]
• Computing Architectural Vulnerability Factors for Address-Based StructuresArijit Biswas, Paul Racunas, Razvan Cheveresan, Joel S. Emer, Shubhendu S. Mukherjee, Ram Rangan. 532-543 [doi]
• The V-Way Cache: Demand Based Associativity via Global ReplacementMoinuddin K. Qureshi, David Thompson, Yale N. Patt. 544-555 [doi]