Abstract is missing.
- Message from the Program Chair [doi]
- SIGARCH Guidelines [doi]
- Message from the General Chair [doi]
- Reviewers [doi]
- Computer Architecture Research and Future Microprocessors: Where Do We Go from Here?Yale N. Patt. 2 [doi]
- A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip NetworksJongman Kim, Chrysostomos Nicopoulos, Dongkook Park. 4-15 [doi]
- The BlackWidow High-Radix Clos NetworkSteve Scott, Dennis Abts, John Kim, William J. Dally. 16-28 [doi]
- Memory Model = Instruction Reordering + Store AtomicityArvind, Jan-Willem Maessen. 29-40 [doi]
- Conditional Memory OrderingChristoph von Praun, Harold W. Cain, Jong-Deok Choi, Kyung Dong Ryu. 41-52 [doi]
- Architectural Semantics for Practical Transactional MemoryAusten McDonald, JaeWoong Chung, Brian D. Carlstrom, Chi Cao Minh, Hassan Chafi, Christos Kozyrakis, Kunle Olukotun. 53-65 [doi]
- Ensemble-level Power Management for Dense Blade ServersParthasarathy Ranganathan, Phil Leech, David E. Irwin, Jeffrey S. Chase. 66-77 [doi]
- Techniques for Multicore Thermal Management: Classification and New ExplorationJames Donald, Margaret Martonosi. 78-88 [doi]
- SODA: A Low-power Architecture For Software RadioYuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner. 89-101 [doi]
- An Integrated Framework for Dependable and Revivable Architectures Using Multicore ProcessorsWeidong Shi, Hsien-Hsin S. Lee, Laura Falk, Mrinmoy Ghosh. 102-113 [doi]
- Multiple Instruction Stream ProcessorRichard A. Hankins, Gautham N. Chinya, Jamison D. Collins, Perry H. Wang, Ryan Rakvic, Hong Wang 0003, John Paul Shen. 114-127 [doi]
- The End of Scaling? Revolutions in Technology and Microarchitecture as We Pass the 90 Nanometer NodePhilip G. Emma. 128 [doi]
- Design and Management of 3D Chip Multiprocessors Using Network-in-MemoryFeihui Li, Chrysostomos Nicopoulos, Thomas D. Richardson, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir. 130-141 [doi]
- Slackened Memory Dependence Enforcement: Combining Opportunistic Forwarding with Decoupled VerificationAlok Garg, M. Wasiur Rashid, Michael C. Huang. 142-154 [doi]
- Balanced Cache: Reducing Conflict Misses of Direct-Mapped CachesChuanjun Zhang. 155-166 [doi]
- A Case for MLP-Aware Cache ReplacementMoinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, Yale N. Patt. 167-178 [doi]
- Improving Cost, Performance, and Security of Memory Encryption and AuthenticationChenyu Yan, Daniel Englender, Milos Prvulovic, Brian Rogers, Yan Solihin. 179-190 [doi]
- A Scalable Architecture For High-Throughput Regular-Expression Pattern MatchingBenjamin C. Brodie, David E. Taylor, Ron K. Cytron. 191-202 [doi]
- Chisel: A Storage-efficient, Collision-free Hash-based Network Processing ArchitectureJahangir Hasan, Srihari Cadambi, Venkata Jakkula, Srimat T. Chakradhar. 203-215 [doi]
- Tolerating Dependences Between Large Speculative Threads Via Sub-ThreadsChristopher B. Colohan, Anastassia Ailamaki, J. Gregory Steffan, Todd C. Mowry. 216-226 [doi]
- Bulk Disambiguation of Speculative Threads in MultiprocessorsLuis Ceze, James Tuck, Josep Torrellas, Calin Cascaval. 227-238 [doi]
- Learning-Based SMT Processor Resource Distribution via Hill-ClimbingSeungryul Choi, Donald Yeung. 239-251 [doi]
- Spatial Memory StreamingStephen Somogyi, Thomas F. Wenisch, Anastassia Ailamaki, Babak Falsafi, Andreas Moshovos. 252-263 [doi]
- Cooperative Caching for Chip MultiprocessorsJichuan Chang, Gurindar S. Sohi. 264-276 [doi]
- Reducing Startup Time in Co-Designed Virtual MachinesShiliang Hu, James E. Smith. 277-288 [doi]
- TRAP-Array: A Disk Array Architecture Providing Timely Recovery to Any Point-in-timeQing Yang, Weijun Xiao, Jin Ren. 289-301 [doi]
- Program Demultiplexing: Data-flow based Speculative Parallelization of Methods in Sequential ProgramsSaisanthosh Balakrishnan, Gurindar S. Sohi. 302-313 [doi]
- Area-Performance Trade-offs in Tiled Dataflow ArchitecturesSteven Swanson, Andrew Putnam, Martha Mercaldi, Ken Michelson, Andrew Petersen, Andrew Schwerin, Mark Oskin, Susan J. Eggers. 314-326 [doi]
- Flexible Snooping: Adaptive Forwarding and Filtering of Snoops in Embedded-Ring MultiprocessorsKarin Strauss, Xiaowei Shen, Josep Torrellas. 327-338 [doi]
- Interconnect-Aware Coherence Protocols for Chip MultiprocessorsLiqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, John B. Carter. 339-351 [doi]
- The Future of Virtualization TechnologySteve Herrod. 352 [doi]
- Distributed Arithmetic on a Quantum MulticomputerRodney Van Meter, Kae Nemoto, W. J. Munro, Kohei M. Itoh. 354-365 [doi]
- Interconnection Networks for Scalable Quantum ComputersNemanja Isailovic, Yatish Patel, Mark Whitney, John Kubiatowicz. 366-377 [doi]
- Quantum Memory Hierarchies: Efficient Designs to Match Available Parallelism in Quantum ComputingDarshan D. Thaker, Tzvetan S. Metodi, Andrew W. Cross, Isaac L. Chuang, Frederic T. Chong. 378-390 [doi]