Table of Contents

• Achieving Out-of-Order Performance with Almost In-Order ComplexityFrancis Tseng, Yale N. Patt. 3-12 [doi]
• Fetch-Criticality Reduction through Control IndependenceMayank Agarwal, Nitin Navale, Kshitiz Malik, Matthew I. Frank. 13-24 [doi]
• A Two-Level Load/Store Queue Based on Execution LocalityMiquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Ruden González, Alexander V. Veidenbaum, Daniel A. Jiménez, Mateo Valero. 25-36 [doi]
• Self-Optimizing Memory Controllers: A Reinforcement Learning ApproachEngin Ipek, Onur Mutlu, José F. Martínez, Rich Caruana. 39-50 [doi]
• A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory HierarchiesShyamkumar Thoziyoor, Jung Ho Ahn, Matteo Monchiero, Jay B. Brockman, Norman P. Jouppi. 51-62 [doi]
• Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM SystemsOnur Mutlu, Thomas Moscibroda. 63-74 [doi]
• Technology-Driven, Highly-Scalable Dragonfly TopologyJohn Kim, William J. Dally, Steve Scott, Dennis Abts. 77-88 [doi]
• Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip NetworksJae W. Lee, Man Cheuk Ng, Krste Asanovic. 89-100 [doi]
• Polymorphic On-Chip NetworksMartha Mercaldi Kim, John D. Davis, Mark Oskin, Todd M. Austin. 101-112 [doi]
• Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional MemoryLee Baugh, Naveen Neelakantam, Craig B. Zilles. 115-126 [doi]
• TokenTM: Efficient Execution of Large Transactions with Hardware Transactional MemoryJayaram Bobba, Neelam Goyal, Mark D. Hill, Michael M. Swift, David A. Wood. 127-138 [doi]
• Flexible Decoupled Transactional Memory SupportArrvindh Shriraman, Sandhya Dwarkadas, Michael L. Scott. 139-150 [doi]
• Corona: System Implications of Emerging Nanophotonic TechnologyDana Vantrease, Robert Schreiber, Matteo Monchiero, Moray McLaren, Norman P. Jouppi, Marco Fiorentino, Al Davis, Nathan L. Binkert, Raymond G. Beausoleil, Jung Ho Ahn. 153-164 [doi]
• Microcoded Architectures for Ion-Tap Quantum ComputersLucas Kreger-Stickles, Mark Oskin. 165-176 [doi]
• Running a Quantum Circuit at the Speed of DataNemanja Isailovic, Mark Whitney, Yatish Patel, John Kubiatowicz. 177-188 [doi]
• ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable LatencyXiaoyao Liang, Gu-Yeon Wei, David Brooks. 191-202 [doi]
• Trading off Cache Capacity for Reliability to Enable Low Voltage OperationChris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad Khellah, Shih-Lien Lu. 203-214 [doi]
• Counting Dependence PredictorsFranziska Roesner, Doug Burger, Stephen W. Keckler. 215-226 [doi]
• Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast SupportNatalie D. Enright Jerger, Li-Shiuan Peh, Mikko H. Lipasti. 229-240 [doi]
• iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) ArchitecturesAvinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri. 241-250 [doi]
• MIRA: A Multi-layered On-Chip Interconnect Router ArchitectureDongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das. 251-261 [doi]
• Rerun: Exploiting Episodes for Lightweight Memory Race RecordingDerek Hower, Mark D. Hill. 265-276 [doi]
• Atom-Aid: Detecting and Surviving Atomicity ViolationsBrandon Lucia, Joseph Devietti, Karin Strauss, Luis Ceze. 277-288 [doi]
• DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution EffcientlyPablo Montesinos, Luis Ceze, Josep Torrellas. 289-300 [doi]
• Intra-disk Parallelism: An Idea Whose Time Has ComeSriram Sankar, Sudhanva Gurumurthi, Mircea R. Stan. 303-314 [doi]
• Understanding and Designing New Server Architectures for Emerging Warehouse-Computing EnvironmentsKevin T. Lim, Parthasarathy Ranganathan, Jichuan Chang, Chandrakant D. Patel, Trevor N. Mudge, Steven K. Reinhardt. 315-326 [doi]
• Improving NAND Flash Based Disk CachesTaeho Kgil, David Roberts, Trevor N. Mudge. 327-338 [doi]
• Online Estimation of Architectural Vulnerability Factor for Soft ErrorsXiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers. 341-352 [doi]
• A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM LifetimeJeonghee Shin, Victor V. Zyuban, Pradip Bose, Timothy Mark Pinkston. 353-362 [doi]
• Variation-Aware Application Scheduling and Power Management for Chip MultiprocessorsRadu Teodorescu, Josep Torrellas. 363-374 [doi]
• Flexible Hardware Acceleration for Instruction-Grain Program MonitoringShimin Chen, Michael Kozuch, Theodoros Strigkos, Babak Falsafi, Phillip B. Gibbons, Todd C. Mowry, Vijaya Ramachandran, Olatunji Ruwase, Michael Ryan, Evangelos Vlachos. 377-388 [doi]
• VEAL: Virtualized Execution Accelerator for LoopsNathan Clark, Amir Hormati, Scott A. Mahlke. 389-400 [doi]
• From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative HardwareHaibo Chen, Xi Wu, Liwei Yuan, Binyu Zang, Pen-Chung Yew, Frederic T. Chong. 401-412 [doi]
• Software-Controlled Priority Characterization of POWER5 ProcessorCarlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Chen-Yong Cher, Mateo Valero. 415-426 [doi]
• Learning and Leveraging the Relationship between Architecture-Level Measurements and Individual User SatisfactionAlex Shye, Berkin Özisikyilmaz, Arindam Mallik, Gokhan Memik, Peter A. Dinda, Robert P. Dick, Alok N. Choudhary. 427-438 [doi]
• Atomic Vector Operations on Chip MultiprocessorsSanjeev Kumar, Daehyun Kim, Mikhail Smelyanskiy, Yen-Kuang Chen, Jatin Chhugani, Christopher J. Hughes, Changkyu Kim, Victor W. Lee, Anthony D. Nguyen. 441-452 [doi]
• 3D-Stacked Memory Architectures for Multi-core ProcessorsGabriel H. Loh. 453-464 [doi]