Table of Contents

• Size, Power, and SpeedMaurice V. Wilkes. 2-4
• Towards a Taxonomy of Computer Architecture Based on the Machine Data Type ViewWolfgang K. Giloi. 6-15
• Frameworks for a Taxonomy of Fault-Tolerance Attributes in Computer SystemsAlgirdas Avizienis. 16-21
• Caddie - An Interactive Design EnvironmentBjörn Pehrson, Joachim Parrow. 24-31
• On the Verification of Computer Architectures Using an Architecture Description LanguageSubrata Dasgupta. 32-38
• Research on Synthesis of Concurrent Computing SystemsRichard M. King. 39-46
• Architecture of the PSC: A Programmable Systolic ChipAllan L. Fisher, H. T. Kung, Louis Monier, Yasunori Dohi. 48-53
• Synchronizing Large VLSI Processor ArraysAllan L. Fisher, H. T. Kung. 54-58
• The Boolean Vector Machine [BVM]Robert A. Wagner. 59-66
• A VLSI Tree Machine for Relational Data BasesMaurizio A. Bonuccelli, Elena Lodi, Fabrizio Luccio, Piero Maestrini, Linda Pagli. 67-73
• Implementing Streams on a Data Flow Computer System With Paged MemoryL. J. Caluwaerts, J. Debacker, J. A. Peperstraete. 76-83
• The Piecewise Data Flow Architecture Control Flow and Register ManagementJoseph E. Requa. 84-89
• On the Working Set Concept for Data-Flow MachinesMario Tokoro, J. R. Jagannathan, Hideki Sunahara. 90-97
• A Data Driven System Based on a Microprogrammed Processor ModuleR. W. Marczynski, J. Milewski. 98-106
• Architecture of a VLSI Instruction Cache for a RISCDavid A. Patterson, Phil Garrison, Mark D. Hill, Dimitris Lioupis, Chris Nyberg, Tim Sippel, Korbin Van Dyke. 108-116
• Performance of Shared Cache for Parallel-Pipelined Computer SystemsPhil C. C. Yeh, Janak H. Patel, Edward S. Davidson. 117-123
• Using Cache Memory to Reduce Processor-Memory TrafficJames R. Goodman. 124-131
• A Study of Instruction Cache Organizations and Replacement PoliciesJames E. Smith, James R. Goodman. 132-137
• Very Long Instruction Word Architectures and the ELI-512Joseph A. Fisher. 140-150
• A User-Microprogrammable, Local Host Computer With Low-Level ParallelismShinji Tomita, Kiyoshi Shibayama, Toshiaki Kitamura, Toshiyuki Nakata, Hiroshi Hagiwara. 151-157
• Combining Tags With Error CodesRichard H. Gumpertz. 160-165
• Fault Diagnosis of Bit-Slice ProcessorYoung Gil Park, Jung Wan Cho. 166-172
• Line Digraph Iterations and the (d,k) Problem for Directed GraphsMiguel Angel Fiol, Ignacio Alegre, J. Luis A. Yebra. 174-177
• Resource Allocation in Rectangular CC-BanyansEli Opper, Miroslaw Malek, G. Jack Lipovski. 178-184
• Uniform Theory of the Shuffle-Exchange Type Permutation NetworksFrantisek Sovis. 185-191
• Analysis of Cray-1S ArchitectureVason P. Srini, Jorge F. Asenjo. 194-206
• Performance Measurements on HEP - A Pipelined MIMD ComputerHarry F. Jordan. 207-212
• (SM)2: Sparse Matrix Solving MachineHideharu Amano, Takaichi Yoshida, Hideo Aiso. 213-220
• An Experimental System for Computer Science InstructionR. Kalyana Krishnan, A. K. Rajasekar, C. S. Moghe. 222-227
• Execution Control and Memory Management of a Data Flow Signal ProcessorKlaus Kronlof. 230-235
• DDDP: A Distributed Data Driven ProcessorMasasuke Kishi, Hiroshi Yasuhara, Yasusuke Kawamura. 236-242
• A Data Flow Processor Array System: Design and AnalysisNaohisa Takahashi, Makoto Amamiya. 243-250
• A Retrospective on the Dorado, A High-Performance Personal ComputerKenneth A. Pier. 252-269
• System/370 Extended Architecture: A Program View of the Channel SubsystemRobert J. Dugan. 270-276
• Adaptive Interpretation as a Means of Exploiting Complex Instruction SetsRichard L. Norton, Jacob A. Abraham. 277-282
• Switching Strategies in a Class of Packet Switching NetworksManoj Kumar, Daniel M. Dias, J. Robert Jump. 284-300
• A Comparative Study of Distributed Resource Sharing on MultiprocessorsBenjamin W. Wah. 301-308
• Concurrent Error Detection in VLSI Interconnection NetworksW. Kent Fuchs, Jacob A. Abraham, Kuang-Hua Huang. 309-315
• Hierarchical Function Distribution - A Design Principle for Advanced Multicomputer ArchitecturesWolfgang K. Giloi, Peter M. Behr. 318-325
• EMMA: An Industrial Experience on Large Multiprocessing ArchitecturesLuigi Stringa. 326-333
• A Communication Structure for a Multiprocessor Computer with Distributed Global MemoryLars Philipson, Bo Nilsson, Bjorn Breidegard. 334-340
• ALPHA: A High-Performance LISP Machine Equipped with a New Stack Structure and Garbage Collection SystemHiromu Hayashi, Akira Hattori, Haruo Akimoto. 342-348
• A Parallel Execution Model of Logic ProgramsShinji Umeyama, Koichiro Tamura. 349-355
• A System Architecture for the Concurrent Evaluation of Applicative Program ExpressionsClaudia Schmittgen, Werner E. Kluge. 356-362
• A Performance Evaluation of a Lisp-Based Data-Driven Machine (EM-3)Yoshinori Yamaguchi, Kenji Toda, Toshitsugu Yuba. 363-369
• A Pyramidal Approach to Parallel ProcessingSteven L. Tanimoto. 372-378
• The Design of a Parallel Processor for Image Processing On-Board Satellites: An Application Oriented ApproachGerard Gaillat. 372-386
• LINKS-1: A Parallel Pipelined Multimicrocomputer System for Image CreationHitoshi Nishimura, Hiroshi Ohno, Toru Kawata, Isao Shirakawa, Koichi Omura. 387-394
• LIPP-A SIMD Multiprocessor Architecture for Image ProcessingT. Ericsson, Per-Erik Danielsson. 395-400
• The New Generation of Computer ArchitecturePhilip C. Treleaven. 402-409
• Inference Machine: From Sequential to ParalleShunichi Uchida. 410-416
• Overview to the Fifth Generation Computer System ProjectTohru Moto-Oka. 417-422
• A Relational Data Base Machine: First Step to Knowledge Base MachineKunio Murakami, Takeo Kakuta, Nobuyoshi Miyazaki, Shigeki Shibayama, Haruo Yokota. 423-425
• A Critique of Multiprocessing von Neumann StyleArvind, Robert A. Iannucci. 426-436