Table of Contents

• Safe IP Integration Using Container ModulesRolf Drechsler, Ulrich Kühne. 1-4 [doi]
• A Novel GNR Interconnect Model to Reduce Crosstalk DelaySandip Bhattacharya, Debaprasad Das, Hafizur Rahaman. 5-9 [doi]
• PSDSE: Particle Swarm Driven Design Space Exploration of Architecture and Unrolling Factors for Nested Loops in High Level SynthesisVipul Kumar Mishra, Anirban Sengupta. 10-14 [doi]
• The Design of Ultra Low Power CMOS CGLNA in Nanometer TechnologyP. Kavyashree, Siva Sankar Yellampalli. 15-19 [doi]
• Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM SystemsS. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan. 20-24 [doi]
• Plasmonic Lens Based on Elliptically Tapered Metallic Nano SlitsU. Aparna, H. S. Mruthyunjaya, M. Sathish Kumar. 25-28 [doi]
• GSM and GUI Based Remote Data Logging SystemSadeque Reza Khan, Rajsekhar Kr. Nath, M. S. Bhat. 29-32 [doi]
• Inductive Tuned High Isolation RF MEMS Capacitive Shunt SwitchesE. S. Shajahan, M. S. Bhat, B. Chenna Reddy. 33-37 [doi]
• A Novel Temperature Stable Current Mode Bandgap for Wide Range of Supply Voltage VariationSovan Ghosh. 38-43 [doi]
• Design and Development of FPGA and FPAA Based Remote Terminal Units for Nuclear Power PlantsAditya Gour, Ramesh Sanga, R. P. Behera, P. Sahoo, Nagarajan Murali, Sav Satyamurty. 44-48 [doi]
• Pratham: A Low-Cost Wireless Node with Programmable Radio Range and Over-the-Air Programming Capability for Resource-Constrained ApplicationsVijay Rao, P. P. Priyesh, Subrat Kar. 49-53 [doi]
• Low Energy and Area Efficient Nonbinary Capacitor Array Based SAR ADCD. N. Jagadish, M. S. Bhat. 54-57 [doi]
• A Low Voltage Inverter Based Differential Amplifier for Low Power Switched Capacitor ApplicationsD. N. Jagadish, M. S. Bhat. 58-62 [doi]
• Tunable Active Biquad Filter in ±0.9V 32 Nm CNFETShailendra Kumar Tripathi, Mohd. Samar Ansari. 63-67 [doi]
• Design of a Low Complexity and Fast Hardware Architecture for Digital Image Watermarking in FWHT Domain on FPGASudip Ghosh 0001, Arijit Biswas, Santi P. Maity, Hafizur Rahaman. 68-72 [doi]
• Multilevel Homogeneous Detection Analyzer for Medical Diagnostic Application in Digital Microfluidic BiochipsPranab Roy, Tamosa Chakraborty, Hafizur Rahaman, Parthasarathi Dasgupta. 73-78 [doi]
• Low Voltage CMOS Active Inductor with Bandwidth and Linearity ImprovementPriya Meharde, Vandana Niranjan, Ashwani Kumar. 79-83 [doi]
• Efficient Dual Band RF Energy Harvesting Front End for Ultra Low Power Sensitive Passive Wearable DevicesPramod Kaddi, Nagaveni Vamsi, Anil Appala, Ashudeb Dutta, Shiv Govind Singh, Nagarjuna Nallam. 84-88 [doi]
• Diagnosis of SMGF in ESOP Based Reversible Logic CircuitBappaditya Mondal, Chandan Bandyopadhyay, Dipak Kumar Kole, Jimson Mathew, Hafizur Rahaman. 89-93 [doi]
• Impact of Line Resistance Variations on Crosstalk Delay and Noise in Multilayer Graphene Nano Ribbon InterconnectsManodipan Sahoo, Hafizur Rahaman. 94-98 [doi]
• Joint Estimation of States and Parameters of a Reentry Ballistic Target Using Adaptive UKFManasi Das, Aritro Dey, Smita Sadhu, Tapan Kumar Ghoshal. 99-103 [doi]
• A Multiple Input Multiple Output Switched Capacitor DC-DC Converter with Reduced Switch CountChikku Abraham, R. Rakhee, Babita Roslind Jose. 104-108 [doi]
• MATLAB-Based GUI Development for Stochastic Noise Analysis of Tri-Axial GyroscopesA. Divya Rao, Piyush Kumar, Neha Nain, V. K. Agrawal. 109-114 [doi]
• A New Dynamic Library Based IC Design Automation Methodology Using Functional Symmetry with NPN Class Representation Approach to Reduce NRE Costs and Time-to-MarketSrinivas Sabbavarapu, Basireddy Karunakar Reddy, Amit Acharyya. 115-119 [doi]
• A Low Complexity Architecture for Online On-chip Detection and Identification of f-QRS Feature for Remote Personalized Health Care ApplicationsNaresh Vemishetty, Arpit Jain, Aashish Amber, Amit Acharyya. 120-124 [doi]
• A Low-Complexity Onchip Real-Time Automated ECG Frame Identification Methodology Targeting Remote Health CareKrishna Bharadwaj Chivukula, Naresh Vemishetty, Agathya Jagirdar, Amit Acharyya. 125-129 [doi]
• Integration of LwIP Stack over Intel(R) DPDK for High Throughput Packet Delivery to ApplicationsR. Rajesh, Kannan Babu Ramia, Muralidhar Kulkarni. 130-134 [doi]
• Effect of Constant One and Zero, Shared and Non-decomposed Nodes on Runtime and Graph Size of the Shannon Factor Graph (SFG)Basireddy Karunakar Reddy, Srinivas Sabbavarapu, Amit Acharyya. 135-139 [doi]
• System Architecture for Smart Ubiquitous Health Monitoring System with Area Optimization in Multiple On-chip Radios ScenarioM. P. R. Sai Kiran, Y. Siva Krishna, P. Rajalakshmi, Amit Acharyya. 140-144 [doi]
• A Resolution Independent 2-Bits-per-Cycle SAR ADCAnish Morakhia, Sridhar Gunnam, Preejit Prakash, Sneha Kudli, Tonse Laxminidhi. 145-149 [doi]
• An Improved Multi-band Speech Enhancement Utilizing Masking Properties of Human Hearing SystemNAVNEET UPADHYAY. 150-155 [doi]
• Power-Aware Automated Pipelining of Combinational CircuitsPriyankar Talukdar. 156-160 [doi]
• CA Based Scalable Protocol Processor for Chip MultiprocessorsMamata Dalui, Biplab K. Sikdar. 161-165 [doi]
• Design of Fault Tolerant Universal Logic in QCABibhash Sen, Rijoy Mukherjee, Rajdeep Kumar Nath, Biplab K. Sikdar. 166-170 [doi]
• Hardware Implementation and Testing of Log-MAPP Decoder Based on Novel Un-grouped Sliding-Window TechniqueRahul Shrestha, Roy Paily. 171-175 [doi]
• Power Aware Fault Tolerance in Wireless Networks with Heterogeneous NodesShrutika Joshi, A. Srinivas. 176-181 [doi]
• Synthesis of Symmetric Boolean Functions Using a Three-Stage NetworkArighna Deb, Debesh K. Das, Bhargab B. Bhattacharya. 182-186 [doi]
• VLSI Implementation of Low Power Multiple Single Input Change (MSIC) Test Pattern Generation for BIST SchemeC. Vasanthanayaki, A. Azhagu Jaisudhan Pazhani, Jincy Johnson. 187-191 [doi]
• Impact of Channel Doping and Gate Length on Small Signal Behaviour of Gate Electrode Workfunction Engineered Silicon Nanowire MOSFET at THz FrequencyNeha Gupta 0003, Ajay Kumar 0004, Rishu Chaujar. 192-196 [doi]
• Design of Mechanical Sensing System Based on Nano BaTiO3 Embedded in Biopolymer ElectretS. Murugan, D. Karthikesan, S. Sellathurai, E. Praveen, K. Jayakumar. 199-202 [doi]
• Automated Physical Verification of I/O Pads in Full-Custom EnvironmentRajesh Mangalore Anand, Soujanya Ravula, M. A. Kalpashree, Soumya Satavisa. 203-205 [doi]
• Electronically Tunable Resistor-less Universal Filter in ±0.5V 32nm CNFETJyoti Sharma, Mohd. Samar Ansari, Jankiballabh Sharma. 206-207 [doi]
• FPGA Implementation of Pipelined Blowfish AlgorithmSwagata Roy Chatterjee, Soham Majumder, Bodhisatta Pramanik, Mohuya Chakraborty. 208-209 [doi]
• Method to Determine Contrariety between Architectures Containing Stratified Memory Mapped Register SetsVasant Easwaran, Nagendra Gulur, Sushaanth Srirangapathi, Mihir Mody, Rahul Gulati, Prashant Karandikar, Prithvi Shankar. 210-214 [doi]
• A Survey - Super Resolution Techniques for Multiple, Single, and Stereo ImagesChandra Shaker Balure, M. Ramesh Kini. 215-216 [doi]
• Emotion Recognition through Speech Signal for Human-Computer InteractionS. Lalitha, Sahruday Patnaik, T. H. Arvind, Vivek Madhusudhan, Shikha Tripathi. 217-218 [doi]
• A Low Power 8-Bit Asynchronous SAR ADC Design Using Charge Scaling DACAnush Bekal, Manish Goswami, B. R. Singh, Dipankar Pal. 219-223 [doi]
• A New Design of an N-Bit Reversible Arithmetic Logic UnitSubhankar Pal, Chetan Vudadha, Sai Phaneendra P., Sreehari Veeramachaneni, Srinivas Mandalika. 224-225 [doi]
• Implementation of Area Efficient Hybrid MBIST for Memory Clusters in Asynchronous SoCYasha Jyothi M. Shirur, H. R. Lakshmi, Veena S. Chakravarthi. 226-227 [doi]
• Fixed Range Block Segmentation and Classification for Fractal Image Compression of Satellite ImageriesS. V. VeenaDevi, A. G. Ananth. 228-231 [doi]