Table of Contents

• VATML: Towards On Device Ventricular Arrhythmia Detection Using TinyMLVipin Gautam, Sharad Sinha, Shitala Prasad. 1-6 [doi]
• You Only Look Once in Dark: An Analytical Approach for Low Light Object DetectionSutapa Sen, Rapti Chaudhuri, Tanudeep Ganguly, Partha Pratim Das 0004, Suman Deb. 7-12 [doi]
• Word Level Sign Language Recognition Using MediaPipe and LSTM-GRU NetworkKumar Navendu, Vineet Sahula. 13-18 [doi]
• Optimized Transfer Learning with CNNs for Superior COVID-19 Detection in Chest X-Ray ImagingNivedita Madhukar Tawade, Mohan Bansal, Ramesh Saha. 19-24 [doi]
• Development of an AI based Edge Computing System for Malayalam Vowel ClassificationSuja Markose, Raghu C. V. 25-29 [doi]
• Mender-FPGA: An Open Source Framework for FPGA Remote Update for ML ApplicationsNikita Rathor, Sharad Sinha. 30-35 [doi]
• Fortified-SoC: A Novel Approach Towards Trojan Resilient System-on-Chip DesignBurra Subbarao, Chella Amala, Banee Bandana Das, Saswat Kumar Ram, Saraju P. Mohanty. 36-39 [doi]
• Proximity Detection Based Low-Cost and Handheld IoT Device for Tracking Lost ObjectsKanishk Kumar Sachan, Anisha Natarajan. 40-43 [doi]
• Variation of Sensitivity of AlGaN/GaN High Electron Mobility Transistor(HEMT) Based Hydrogen Gas Sensor on Thickness of AlGaN and Mole Fraction of AluminiumJ. Rahul, Renuka Kumaran, Lintu Rajan. 44-48 [doi]
• A 1024-Input Multi-Stage Voltage-Mode WTA Circuit for Selective Attention Based Processing in Massive Parallel Sensing ApplicationsP. K. Pandey, B. Bhuvan. 49-53 [doi]
• Magnetic Skyrmions Based One-Bit ComparatorShivangi Shringi, Srinivasu Bodapati, Srikant Srinivasan. 54-59 [doi]
• Temperature Sensing Readout Circuits with 4H-SiC TechnologyMd Asif Khan, Pydi Ganga Bahubalindruni, Alexander May 0004, Chiara Rossi, Mathias Rommel. 60-63 [doi]
• FPGA Implementation of an Efficient FIR Filter Using Double MAC UnitAnish M. George, Shajimon K. John, Kala S. 64-68 [doi]
• Low IF CMOS Receiver with 3-Stage LNA for Sub-GHz CommunicationShivam Kumar Jha, Apsana Khatoon, Priyanka Tiwari, Dipti, Kavindra Kandpal, Manish Goswami, Prasanna Kumar Misra. 69-74 [doi]
• Power Conscious Asynchronous FIFO for Forest Event SurveillanceSubhadeep Nag, Suman Kalyan Porel, Dyuti Sengupta, Aniruddha Chandra, Hemanta Kumar Mondal. 75-80 [doi]
• SleepTrackSoC: Design and Implementation of Power and Cost Efficient Cortex-M0 based Sleep Tracking SoCIshan Malhotra, Sarthak Grover, Deepank Grover, Tarun Sharma, Keshav Goel, Sujay Deb. 81-86 [doi]
• Towards Harnessing the Potential of Compression and Encoding to Enhance NVM LifespanArijit Nath, Jitendra Meena. 87-92 [doi]
• Machine Learning Based Algorithm for Shockley-Read-Hall Recombination and Augur Recombination PredictionsVibhu, Shivang Bhargav, Vivek Kumar, Sparsh Mittal. 93-98 [doi]
• Power Reduction of a Level Triggered D Flip-Flop using Clock Gating and Power Gating TechniquesYamana Ashok Kumar, Nithin Kumar Y. B, Vasantha M. H., Siddharth R. K.. 99-103 [doi]
• A Reconfigurable Floating-Point Compliant Hardware Architecture for Neural Network ImplementationAbhishek Yadav, Ayush Dixit, Utsav Jana, Binod Kumar 0001. 104-109 [doi]
• HLS Based Hardware Watermarking Using IP Seller's Superimposed Facial Anthropometric FeaturesAnirban Sengupta, Aditya Anshul, Vishal Chourasia. 110-115 [doi]
• SWIFT: Swarm Intelligence Driven ESL Synthesis for Functional Trojan FortificationAnirban Sengupta, Rahul Chaurasia. 116-121 [doi]
• Secure Accelerated Computing: High-Level Synthesis Based Hardware Accelerator Design for CNN ApplicationsRahul Chaurasia, Anirban Sengupta. 122-127 [doi]
• Gen-Sign: HLS Based Watermarking Using IP Vendor's Feistel Cipher Encrypted Genomic Signature for Protecting CNN and Image Processing Filter Cores Against PiracyAnirban Sengupta, Vishal Chourasia, Ayush Kumar Singh. 128-133 [doi]
• HLS driven Hybrid GA-PSO for Design Space Exploration of Optimal Palmprint Biometric based IP Watermark and Loop Unrolling FactorAnirban Sengupta, Vishal Chourasia, Nitish Kumar. 134-139 [doi]
• A Stacking Ensemble Technique to Predict Speed and Distance in 4G and 5G Communication DatasetsDivya Aggarwal, R. Sai Chandra Teja, Sparsh Mittal. 146-151 [doi]
• SPEEDNet: Salient Pyramidal Enhancement Encoder-Decoder Network for Colonoscopy ImagesTushir Sahu, Vidhi Bhatt, Sparsh Mittal, R. Sai Chandra Teja, Nagesh Kumar S. 152-157 [doi]
• Highly Reliable, Feed-Forward and Multi-Arbiter based Physical Unclonable Function for IoT securityNitish Kumar, Sneha Chaudhary, Kavindra Kandpal, Manish Goswami. 158-163 [doi]
• A GUI Based Digital IC TesterAbbas Murtaza, Khagendra Joshi, Sana Ali Naqvi, Vivek Ashok Bohara. 164-167 [doi]
• Integrating Traditional Culinary Techniques with Modern Technology: Power TandoorAjay Kumar, Alok Nikhil Jha. 168-172 [doi]
• Open Source SoC Design for Low-Cost Micro Weather StationNamit Gupta, Pravar Pathania, Keshav Goel, Tarun Sharma, Sujay Deb. 173-176 [doi]
• Design and Development of VariScan: A Continuous Heart Rate Variability MonitorAman Ranjan, Megha Megha, Sujay Deb. 177-180 [doi]
• Anomaly Detection from CCTV Camera FeedAakash, Lakshay Chauhan, Shubham Sharma, Sujay Deb. 181-184 [doi]
• A Hardware-Software Co-Design Approach to Implement PUFs and TRNGs on FPGAsAditya Mathuriya, Deepank Grover, Sujay Deb. 185-188 [doi]
• VLSI Implementation of Edge Detection Chip: A Prospective DesignHarsh Raj Thakur, Prabir Saha. 189-194 [doi]
• Exploring the Application of Variable Frequency Clock as the Constituent of OCTPriyanka J, Pritam Bhattacharjee, Alak Majumder. 195-199 [doi]
• 0.6 to 1.2V Wide Voltage Range Bandgap Reference Generator in 18nm UTBB-FD-SOI TechnologyTanisha Gupta, Shubham Jain, Anuj Grover. 199-203 [doi]
• VLSI Architecture for the Phase Unwrapping Module in Contactless Vibration Sensing for Biomedical ApplicationsMujeev Khan, Ashi Singhal, Mohd Wajid, Abhishek Srivastava 0002. 204-209 [doi]
• Offline Power Estimation in CMOS VLSI Circuits Using Machine Learning ModelDipti Sakshi Srivastava, Soumili Kundu, Aritra Senapati, Hemanta Kumar Mondal. 210-213 [doi]
• An Algorithmic Approach of Generating a VFC of Low Average Frequency RampPriyanka J, Ankita Deb, Pritam Bhattacharjee, Alak Majumder. 220-223 [doi]
• Design of an Operational Transconductance Amplifier-Based Charge Pump for Phase-Locked Loop ApplicationsPayali Das, Alak Majumder. 230-234 [doi]
• Efficient Framework with Sparse Acquisition in CMOS Image Sensors for Low-Power Edge DevicesWilfred Kisku, Amandeep Kaur 0005, Deepak Mishra 0003. 235-239 [doi]
• A Fully Digital Rail-to-Rail Low Power Dynamic Comparator for Smart DevicesBibhudutta Stapathy, Utkarsh Srivastava, Amandeep Kaur. 240-245 [doi]
• LSTM Based Model Predictive Control Approach for Energy Management System in PV-Battery Integrated Microgrid NetworkPreetha Roselyn J, Prabha Sundaravadivel, V. Vignesh Babu, C. Nithya, D. Devaraj. 246-250 [doi]
• A Method of Variable Frequency Clock GenerationVipin Kumar Singh, Vijay Pratap Yadav, Tika Ram Pokhrel, Pritam Bhattacharjee, Alak Majumder. 251-254 [doi]
• HLS Based Rapid Pareto Front Search of Watermarked Convolutional Layer IP DesignAnirban Sengupta, Vishal Chourasia. 255-260 [doi]
• Power, Performance, and Area Optimisation of the RISC-V ProcessorAnushka Ganguly, Arindam Chakraborty, Akash Arun Ambekar, Hemanta Kumar Mondal. 271-274 [doi]
• A 72 mW, 50 MHz Bandwidth Low-IF CMOS Receiver Front End with Improved Linearity and Dynamic RangeApsana Khatoon, Prasanna Kumar Misra. 275-278 [doi]
• Efficient Motion Estimation for Video Compression Using Approximate Arithmetic in Sum of Absolute Difference ComputationR. Nandagopal, Sumit K. Chatterjee. 279-283 [doi]
• Modular Implementation of Directory-Based Cache Coherence for Multicore ProcessingUllas Pai, Naorem Akshaykumar, Deepank Grover, Sujay Deb. 284-287 [doi]
• Event-Based Vision for Real-Time Speed Detection: A Low Resource Utilization Hardware-Software Co-Design ApproachSohan Pagar, Samhita Patil, Tarun Sharma, Sujay Deb. 288-292 [doi]
• Plant Disease Detection in Smart Agriculture: A Power-aware Edge-AI Implementation on Cortex-A53Tamonash Bhattacharyya, Anurag Mohan Roy, Suddhabrato Ghosh, Prasun Ghosal. 293-298 [doi]
• Harnessing Knowledge-Distillation for Lightweight AI-Implementation on Resource-Constrained DeviceAbhishek Yadav, Vyom Kumar Gupta, Binod Kumar 0001. 299-302 [doi]
• A Hybrid CNN-BiLSTM Neural Network Architecture for Early Prediction of Parkinson's DiseaseMrityunjay Kumar Chauhan, Prasun Ghosal. 303-308 [doi]
• Stress Detection and Monitoring: A Systematic ReviewSerina Nandan, Satota Mandal, Prasun Ghosal. 309-314 [doi]
• iGLU 4.1: An Intelligent Framework of Diabetes Prediction using Glucose-Insulin Values and Physiological ParametersPrateek Jain 0006, Amit M. Joshi 0001, Saraju P. Mohanty. 315-320 [doi]
• Electrical Analysis of Stretchable Serpentine Interconnect for Flexible Electronic SystemGulafsha Bhatti, Yash Agrawal, Vinay Palaparthy. 321-325 [doi]
• Implementation and Analysis of Sparse DNN on GPUAparna Nair M. K, Nandhu Sam, Minu A Pillai, Nalesh S 0001, Kala S. 332-337 [doi]
• rA*: Re-Planned A* Technique for Point-to-Point Robot Navigation in Dynamic EnvironmentsTanudeep Ganguly, Rapti Chaudhuri, Suman Deb. 338-343 [doi]
• A Novel Monocular Camera-based Modular Reference Generation for Autonomous VehiclesSachin Thomas, Aparna Sharma, Ritika Pandey, L. Umanand. 344-349 [doi]
• Deep Learning-Based Multiuser Classification for Malicious User Detection in 5G and Beyond Cooperative Sensing SystemsRam S. Iyer, Shivam Raj, Vaibhav Mishra, Shivanshu Shrivastava. 350-353 [doi]
• Side Channel Attack on 8051 MicrocontrollerManda Yuktha, Pragati Patel, Vasantha M. H.. 354-359 [doi]
• Kalman Filter: A Crucial Step Towards the Development of NavICAvinash Sharma, Abhishek Dutta, Sujay Deb. 360-363 [doi]
• Deep Learning for Brain Tumor Detection with FPGA PathwayAniruddha Mallick, Hriya Prasad, Prasenjit Maji, Subhabrata Banerjee, Hemanta Kumar Mondal. 364-367 [doi]
• Power, Performance and Area Optimization of Asynchronous FIFOSuman Kalyan Porel, Subhadeep Nag, Aniruddha Chandra, Hemanta Kumar Mondal. 368-371 [doi]
• Design of a Portable and Non-Invasive Hemoglobin Measuring DeviceRiya Maiti, Srijita Saha, Kriti Shrivastava, Kousik Midya, Arnab Chattopadhyay, Ashis Kumar Dhara. 372-375 [doi]
• Consequence of Various Clock Parameters on Power / Timing Analysis for VLSI CircuitsSubhadeep Nag, Suman Kalyan Porel, Dyuti Sengupta, Aniruddha Chandra, Hemanta Kumar Mondal. 376-379 [doi]
• SecureHD: Designing Low-Cost Reliable and Security Aware Hardware Accelerators During High-Level Synthesis for Computationally Intensive Application FrameworksRahul Chaurasia, Anirban Sengupta. 380-383 [doi]