Abstract is missing.
- The CAD challenges of designing low power, high performance VLSI systemWalter Davis. 1 [doi]
- Clustered voltage scaling technique for low-power designKimiyoshi Usami, Mark Horowitz. 3-8 [doi]
- Variable voltage schedulingSalil Raje, Majid Sarrafzadeh. 9-14 [doi]
- Unifying carry-sum and signed-digital number representations for low powerChetana Nagendra, Robert Michael Owens, Mary Jane Irwin. 15-20 [doi]
- A multiple clocking scheme for low power RTL designChristos A. Papachristou, Mark Spining, Mehrdad Nourani. 27-32 [doi]
- Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programsJosé Monteiro, Srinivas Devadas. 33-38 [doi]
- Estimation of energy consumption in speed-independent control circuitsPeter A. Beerel, Cheng-Ta Hsieh, Suhrid A. Wadekar. 39-44 [doi]
- Energy optimization of multi-level processor cache architecturesUming Ko, Poras T. Balsara, Ashwini K. Nanda. 45-49 [doi]
- Transforming set data types to power optimal data structuresSven Wuytack, Francky Catthoor, Hugo De Man. 51-56 [doi]
- Reducing the frequency of tag compares for low power I-cache designRamesh Panwar, David A. Rennels. 57-62 [doi]
- Cache design trade-offs for power and performance optimization: a case studyChing-Long Su, Alvin M. Despain. 63-68 [doi]
- Simultaneous scheduling and binding for power minimization during microarchitecture synthesisAurobindo Dasgupta, Ramesh Karri. 69-74 [doi]
- Information theoretic measures of energy consumption at register transfer levelDiana Marculescu, Radu Marculescu, Massoud Pedram. 81-86 [doi]
- Towards a high-level power estimation capabilityFarid N. Najm. 87-92 [doi]
- Activity-sensitive architectural power analysis for the control pathPaul E. Landman, Jan M. Rabaey. 93-98 [doi]
- High-level synthesis techniques for reducing the activity of functional unitsEnric Musoll, Jordi Cortadella. 99-104 [doi]
- The design and implementation of PowerMillCharlie X. Huang, Bill Zhang, An-Chang Deng, Burkhard Swirski. 105-110 [doi]
- CMOS dynamic power estimation based on collapsible current source transistor modelingAbelardo Pardo, R. Iris Bahar, Srilatha Manne, Peter Feldmann, Gary D. Hachtel, Fabio Somenzi. 111-116 [doi]
- Logic design for low-voltage/low-power CMOS circuitsChristian Piguet, Jean-Marc Masgonty, V. von Kaenel, T. Schneider. 117-122 [doi]
- Analysis of glitch power dissipation in CMOS ICsMichele Favalli, Luca Benini. 123-128 [doi]
- Explicit evaluation of short circuit power dissipation for CMOS logic structuresS. Turgis, Nadine Azémard, Daniel Auvergne. 129-134 [doi]
- Techniques for fast circuit simulation applied to power estimation of CMOS circuitsPremal Buch, Shen Lin, Vijay Nagasamy, Ernest S. Kuh. 135-138 [doi]
- High-throughput and low-power DSP using clocked-CMOS circuitryManjit Borah, Robert Michael Owens, Mary Jane Irwin. 139-144 [doi]
- Low delay-power product CMOS design using one-hot residue codingWilliam A. Chren Jr.. 145-150 [doi]
- Low power and EMI, high frequency, crystal oscillatorRafael Fried, Reuven Holzer. 151-154 [doi]
- Power and area optimization by reorganizing CMOS complex gate circuitsM. Tachibana, S. Kurosawa, R. Nojima, Norman Kojima, Masaaki Yamada, Takashi Mitsuhashi, Nobuyuki Goto. 155-160 [doi]
- Transistor reordering for low power CMOS gates using an SP-BDD representationAlexey Glebov, David Blaauw, Larry G. Jones. 161-166 [doi]
- Transistor sizing for minimizing power consumption of CMOS circuits under delay constraintManjit Borah, Robert Michael Owens, Mary Jane Irwin. 167-172 [doi]
- Re-encoding for low power state assignment of FSMsVamshi Veeramachaneni, Akhilesh Tyagi, Suresh Rajgopal. 173-178 [doi]
- Optimization of power dissipation and skew sensitivity in clock buffer synthesisJae W. Chung, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin. 179-184 [doi]
- Charge recovery on a databusKei-Yong Khoo, Alan N. Willson Jr.. 185-189 [doi]
- 2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuitsAlan Kramer, John S. Denker, B. Flower, J. Moroney. 191-196 [doi]
- Electroid-oriented adiabatic switching circuitsDavid J. Frank, Paul M. Solomon. 197-202 [doi]
- Ultra-low-power analog associative memory core using flash-EEPROM-based programmable capacitorsAlan Kramer, Roberto Canegallo, Mauro Chinosi, D. Doise, Giovanni Gozzini, Pier Luigi Rolandi, M. Sabatini, P. Zabberoni. 203-208 [doi]
- Low voltage analog circuits using standard CMOS technologyPhillip E. Allen, Benjamin J. Blalock, Gabriel A. Rincon. 209-214 [doi]
- Determining accuracy bounds for simulation-based switching activity estimationAnthony M. Hill, Sung-Mo Kang. 215-220 [doi]
- Guarded evaluation: pushing power management to logic synthesis/designVivek Tiwari, Sharad Malik, Pranav Ashar. 221-226 [doi]
- An estimation technique to guide low power resynthesis algorithmsChristopher K. Lennard, A. Richard Newton. 227-232 [doi]