Table of Contents

• Low power RF integrated circuits: principles and practiceA. A. Abidi, Houshang Darabi. 1-6 [doi]
• Algorithm and architecture of a 1V low power hearing instrument DSPFinn Müller, Nikolai Bisgaard, John Melanson. 7-11 [doi]
• A shared-bitline SRAM cell architecture for 1-V ultra low-power word-bit configurable macrocellsHiroki Morimura, Satoshi Shigematsu, Shinsuke Konaka. 12-17 [doi]
• Retractile clock-powered logicNestoras Tzartzanis, William C. Athas. 18-23 [doi]
• Energy-efficient dynamic circuit design in the presence of crosstalk noiseGanesh Balamurugan, Naresh R. Shanbhag. 24-29 [doi]
• Energy-efficient signal processing via algorithmic noise-toleranceRajamohana Hegde, Naresh R. Shanbhag. 30-35 [doi]
• Reducing power consumption of turbo code decoder using adaptive iteration with variable supply voltageOliver Yuk-Hang Leung, Chung-Wai Yue, Chi-Ying Tsui, Roger S. Cheng. 36-41 [doi]
• A low energy architecture for fast PN acquisitionChristopher Deng, Charles Chien. 42-47 [doi]
• Vibration-to-electric energy conversionScott Meninger, Jose Oscar Mur-Miranda, Rajeevan Amirtharajah, Anantha Chandrakasan, Jeffrey Lang. 48-53 [doi]
• Variable supply-voltage scheme with 95 -efficiency DC-DC converter for MPEG-4 codecFuyuki Ichiba, Kojiro Suzuki, Shinji Mita, Tadahiro Kuroda, Tohru Furuyama. 54-59 [doi]
• Circuit methods for the integration of low voltage (1.1-1.8V) analog functions on system-on-a-chip IC s in a single-poly CMOS processesVladimir Koifman, Yachin Afek, Joseph Shor. 60-63 [doi]
• Using dynamic cache management techniques to reduce energy in a high-performance processorNikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos. 64-69 [doi]
• Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentationKanad Ghose, Milind B. Kamble. 70-75 [doi]
• Energy efficient data transfer and storage organization for a MAP turbo decoder moduleCurt Schurgers, Francky Catthoor, Marc Engels. 76-81 [doi]
• Mixed-swing quadrail for low power dual-rail domino logicBharath Ramasubramanian, Herman Schmit, L. Richard Carley. 82-84 [doi]
• Databus charge recovery: practical considerationsBenjamin Bishop, Mary Jane Irwin. 85-87 [doi]
• Conforming inverted data store for low power memoryYou-Sung Chang, Bong-Il Park, Chong-Min Kyung. 91-93 [doi]
• Ultra-low power digital subthreshold logic circuitsHendrawan Soeleman, Kaushik Roy. 94-96 [doi]
• Single-phase source-coupled adiabatic logicSuhwan Kim, Marios C. Papaefthymiou. 97-99 [doi]
• Global register allocation for minimizing energy consumptionYumin Zhang, Xiaobo Hu, Danny Z. Chen. 100-102 [doi]
• Power macro-models for DSP blocks with application to high-level synthesisSubodh Gupta, Farid N. Najm. 103-105 [doi]
• A completey on-chip voltage regulation technique for low power digital circuitsL. Richard Carley, Akshay Aggarwal. 109-111 [doi]
• Comparison of class A amplifiers for low-power and low-voltage switched capacitor applicationsChristoph Schwoerer, Dominique Morche, Patrice Senn. 112-114 [doi]
• Lower and upper bounds on the switching activity in scheduled data flow graphsLars Kruse, Eike Schmidt, Gerd Jochens, Wolfgang Nebel. 115-120 [doi]
• Energy-per-cycle estimation at RTLSubodh Gupta, Farid N. Najm. 121-126 [doi]
• Efficient switching activity computation during high-level synthesis of control-dominated designsAlessandro Bogliolo, Luca Benini, Bruno Riccò, Giovanni De Micheli. 127-132 [doi]
• Non-stationary effects in trace-driven power analysisRadu Marculescu, Diana Marculescu, Massoud Pedram. 133-138 [doi]
• Low power synthesis of dual threshold voltage CMOS VLSI circuitsVijay Sundararajan, Keshab K. Parhi. 139-144 [doi]
• Clock distribution using multiple voltagesJatuchai Pangjun, Sachin S. Sapatnekar. 145-150 [doi]
• VIP - an input pattern generator for indentifying critical voltage drop for deep sub-micron designsYi-Min Jiang, Tak K. Young, Kwang-Ting Cheng. 156-161 [doi]
• Technology and design challenges for low power and high performanceVivek De, Shekhar Borkar. 163-168 [doi]
• Power scalable processing using distributed arithmeticRajeevan Amirtharajah, Thucydides Xanthopoulos, Anantha Chandrakasan. 170-175 [doi]
• Challenges in clockgating for a low power ASIC methodologyDavid Garrett, Mircea R. Stan, Alvar Dean. 176-181 [doi]
• Modeling and automating selection of guarding techniques for datapath elementsWilliam E. Dougherty, Donald E. Thomas. 182-187 [doi]
• The design of a low energy FPGAGeorge Varghese, Hui Zhang, Jan M. Rabaey. 188-193 [doi]
• Stochastic modeling of a power-managed system: construction and optimizationQinru Qiu, Qing Wu, Massoud Pedram. 194-199 [doi]
• The impact of battery capacity and memory bandwidth on CPU speed-setting: a case studyThomas L. Martin, Daniel P. Siewiorek. 200-205 [doi]
• Selective instruction compression for memory energy reduction in embedded systemsLuca Benini, Alberto Macii, Enrico Macii, Massimo Poncino. 206-211 [doi]
• Energy-efficient design of battery-powered embedded systemsTajana Simunic, Luca Benini, Giovanni De Micheli. 212-217 [doi]
• Hysteresis effect in floating-body partially-depleted SOI CMOS domino circuitsRuchir Puri, Ching-Te Chuang. 223-228 [doi]
• A 1.2V, 430MHz, 4dBm power amplifier and a 250muW front-end, using a standard digital CMOS processThierry Melly, Alain-Serge Porret, Christian C. Enz, M. Kayal, Eric A. Vittoz. 233-237 [doi]
• CMOS front-end LNA-mixer of micropower RF wireless systemsRazieh Rofougaran, Tsung-Hsien Lin, William J. Kaiser. 238-242 [doi]
• Differential PLL for wireless applications using differential CMOS LC-VCO and differential charge pumpAyman ElSayed, Akbar Ali, Mohamed I. Elmasry. 243-248 [doi]
• Passive precharge and rippled power logic (PPRPL)Samuel B. Schaevitz, Christopher Lin. 249-251 [doi]
• Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC sAli Keshavarzi, Siva Narendra, Shekhar Borkar, Charles F. Hawkins, Kaushik Roy, Vivek De. 252-254 [doi]
• An architectural solution for the inductive noise problem due to clock-gatingMondira Deb Pant, Pankaj Pant, D. Scott Wills, Vivek Tiwari. 255-257 [doi]
• An optimization technique for dual-output domino logicSumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm. 258-260 [doi]
• Statistically optimized asynchronous barrel shifters for variable length codecsPeter A. Beerel, Sangyun Kim, Pei-Chuan Yeh, Kyeounsoo Kim. 261-263 [doi]
• Inverse polarity techniques for high-speed/low-power multipliersPascal C. H. Meier, Rob A. Rutenbar, L. Richard Carley. 264-266 [doi]
• Instruction fetch energy reduction using loop caches for embedded applications with small tight loopsLea Hwang Lee, Bill Moyer, John Arends. 267-269 [doi]
• A methodology for power efficient partitioning of data-dominated algorithm specifications within performance constraintsKostas Masselos, Koen Danckaert, Francky Catthoor, Constantinos E. Goutis, Hugo De Man. 270-272 [doi]
• Way-predicting set-associative cache for high performance and low energy consumptionKoji Inoue, Tohru Ishihara, Kazuaki Murakami. 273-275 [doi]
• Designing power efficient hypermedia processorsChunho Lee, Johnson Kin, Miodrag Potkonjak, William H. Mangione-Smith. 276-278 [doi]
• Dynamic power estimation using the probabilistic contribution measure (PCM)HoonSang Jin, Myung-Soo Jang, Jin-Suk Song, Jin-Yong Lee, Taek-Soo Kim, Jeong-Taek Kong. 279-281 [doi]
• Circuit styles and strategies for CMOS VLSI design on SOIFari Assaderaghi. 282-287 [doi]
• System-level power optimization: techniques and toolsLuca Benini, Giovanni De Micheli. 288-293 [doi]