Table of Contents

• Low-voltage memories for power-aware systemsKiyoo Itoh. 1-6 [doi]
• Standby power management for a 0.18µm microprocessorLawrence T. Clark, Neil Deutscher, Shay Demmons, Franco Ricci. 7-12 [doi]
• Physical insight into fractional power dependence of saturation current on gate voltage in advanced short channel MOSFETS (alpha-power law model)Hyunsik Im. 13-18 [doi]
• Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOSSiva Narendra, Vivek De, Shekhar Borkar, Dimitri Antoniadis, Anantha Chandrakasan. 19-23 [doi]
• Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technologyKoichi Nose, Takayasu Sakurai. 24-29 [doi]
• ::::E:::2:::::::WFQ: an energy efficient fair scheduling policy for wireless systemsVijay Raghunathan, Saurabh Ganeriwal, Curt Schurgers, Mani B. Srivastava. 30-35 [doi]
• A framework for energy-scalable communication in high-density wireless networksRex Min, Anantha Chandrakasan. 36-41 [doi]
• Contents provider-assisted dynamic voltage scaling for low energy multimedia applicationsEui-Young Chung, Giovanni De Micheli, Luca Benini. 42-47 [doi]
• Low-leakage asymmetric-cell SRAMNavid Azizi, Andreas Moshovos, Farid N. Najm. 48-51 [doi]
• Managing leakage for transient data: decay and quasi-static 4T memory cellsZhigang Hu, Philo Juang, Phil Diodato, Stefanos Kaxiras, Kevin Skadron, Margaret Martonosi, Douglas W. Clark. 52-55 [doi]
• Conditional pre-charge techniques for power-efficient dual-edge clockingNikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija. 56-59 [doi]
• Circuit-level techniques to control gate leakage for sub-100nm CMOSFatih Hamzaoglu, Mircea R. Stan. 60-63 [doi]
• Modeling and analysis of leakage power considering within-die process variationsAshish Srivastava, Robert Bai, David Blaauw, Dennis Sylvester. 64-67 [doi]
• Low-power approach for decoding convolutional codes with adaptive viterbi algorithm approximationsRusell E. Henning, Chaitali Chakrabarti. 68-71 [doi]
• Power-aware source routing protocol for mobile ad hoc networksMorteza Maleki, Karthik Dantu, Massoud Pedram. 72-75 [doi]
• Analyzing energy friendly steady state phases of dynamic application execution in terms of sparse data structuresEdgar G. Daylight, Sven Wuytack, Chantal Ykman-Couvreur, Francky Catthoor. 76-79 [doi]
• Odd/even bus invert with two-phase transfer for buses with couplingYan Zhang, John Lach, Kevin Skadron, Mircea R. Stan. 80-83 [doi]
• An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow modelSunghyun Lee, Kiyoung Choi, Sungjoo Yoo. 84-87 [doi]
• Reducing access energy of on-chip data memory considering active data bitwidthTakanori Okuma, Yun Cao, Masanori Muroyama, Hiroto Yasuura. 88-91 [doi]
• Energy recovering static memoryJoohee Kim, Conrad H. Ziesler, Marios C. Papaefthymiou. 92-97 [doi]
• Low power integrated scan-retention mechanismVictor V. Zyuban, Stephen V. Kosonocky. 98-102 [doi]
• Closed-loop adaptive voltage scaling controller for standard-cell ASICsSandeep Dhar, Dragan Maksimovic, Bruno Kranzen. 103-107 [doi]
• Design of a branch-based 64-bit carry-select adder in 0.18 µm partially depleted SOI CMOSAmaury Nève, Denis Flandre, Helmut Schettler, Thomas Ludwig 0004, Gerhard Hellner. 108-111 [doi]
• Low-power color TFT LCD display for hand-held embedded systemsInseok Choi, Hojun Shim, Naehyuck Chang. 112-117 [doi]
• Discharge current steering for battery lifetime optimizationLuca Benini, Alberto Macii, Enrico Macii, Massimo Poncino. 118-123 [doi]
• Towards energy-aware software-based fault tolerance in real-time systemsOsman S. Unsal, Israel Koren, C. Mani Krishna. 124-129 [doi]
• Fine-grain CAM-tag cache resizing using miss tagsMichael Zhang, Krste Asanovic. 130-135 [doi]
• An adaptive serial-parallel CAM architecture for low-power cache blocksAristides Efthymiou, Jim D. Garside. 136-141 [doi]
• Reducing energy consumption of video memory by bit-width compressionVasily G. Moshnyaga, Koji Inoue, Mizuka Fukagawa. 142-147 [doi]
• A history-based I-cache for low-energy multimedia applicationsKoji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami. 148-153 [doi]
• Battery lifetime prediction for energy-aware computingDaler N. Rakhmatov, Sarma B. K. Vrudhula, Deborah A. Wallach. 154-159 [doi]
• Early evaluation techniques for low power bindingEren Kursun, Ankur Srivastava, Seda Ogrenci Memik, Majid Sarrafzadeh. 160-165 [doi]
• Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levelsVictor V. Zyuban, Philip N. Strenski. 166-171 [doi]
• Is nanoelectronics the future of microelectronics?Mark S. Lundstrom. 172-177 [doi]
• Saving energy with just in time instruction deliveryTejas Karkhanis, James E. Smith, Pradip Bose. 178-183 [doi]
• Tradeoffs in power-efficient issue queue designAlper Buyuktosunoglu, David H. Albonesi, Pradip Bose, Peter W. Cook, Stanley Schuster. 184-189 [doi]
• Reducing transitions on memory buses using sector-based encoding techniqueYazdan Aghaghiri, Massoud Pedram, Farzan Fallah. 190-195 [doi]
• Energy-efficient hybrid wakeup logicMichael C. Huang, Jose Renau, Josep Torrellas. 196-201 [doi]
• Automated selective multi-threshold design for ultra-low standby applicationsKimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa. 202-206 [doi]
• HA:::2:::TSD: hierarchical time slack distribution for ultra-low power CMOS VLSIKyu-won Choi, Abhijit Chatterjee. 207-212 [doi]
• Runtime mechanisms for leakage current reduction in CMOS VLSI circuits:::1, 2:::Afshin Abdollahi, Massoud Pedram, Farzan Fallah. 213-218 [doi]
• Future directions in clocking multi-ghz systemsVojin G. Oklobdzija, Jens Sparsø. 219 [doi]
• Compilers for power and energy managementUlrich Kremer. 220 [doi]
• Oversampled gain-boostingOmid Oliaei. 221-226 [doi]
• ±0.5V ±1.5V VHF CMOS LV/LP four-quadrant analog multiplier in modified bridged-triode schemeSimon C. Li, Jimmy C. Cha. 227-232 [doi]
• A power and resolution adaptive flash analog-to-digital converterJincheol Yoo, Daegyu Lee, Kyusun Choi, Jongsoo Kim. 233-236 [doi]
• Design techniques for low power high bandwidth upconversion in CMOSCarl De Ranter, Michiel Steyaert. 237-242 [doi]
• TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessorsMagnus Ekman, Per Stenström, Fredrik Dahlgren. 243-246 [doi]
• A preactivating mechanism for a VT-CMOS cache using address predictionRyo Fujioka, Kiyokazu Katayama, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada. 247-250 [doi]
• Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessorsChris H. Kim, Kaushik Roy. 251-254 [doi]
• Asymmetric-frequency clustering: a power-aware back-end for high-performance processorsAmirali Baniasadi, Andreas Moshovos. 255-258 [doi]
• Power analysis techniques for SoC with improved wiring modelsTakeshi Sakamoto, Takashi Yamada, Mamoru Mukuno, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura. 259-262 [doi]
• A microarchitectural-level step-power analysis toolWael El-Essawy, David H. Albonesi, Balaram Sinharoy. 263-266 [doi]
• Power estimation of sequential circuits using hierarchical colored hardware petri net modelingAshok K. Murugavel, N. Ranganathan. 267-270 [doi]
• High-level area estimationKavel M. Büyüksahin, Farid N. Najm. 271-274 [doi]
• Retiming-based logic synthesis for low-powerYu-Lung Hsu, Sying-Jyan Wang. 275-278 [doi]
• Activity-sensitive clock tree construction for low powerChunhong Chen, Changjun Kang, Majid Sarrafzadeh. 279-282 [doi]
• Designing SoC sTobias Noll, Heinrich Meyr. 283 [doi]
• Low-power VLSI decoder architectures for LDPC codesMohammad M. Mansour, Naresh R. Shanbhag. 284-289 [doi]
• A low power normalized-LMS decision feedback equalizer for a wireless packet modemDavid Garrett, Chris Nicol, Andrew J. Blanksby, Chris Howland. 290-294 [doi]
• High performance and low power FIR filter design based on sharing multiplicationJongsun Park, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy. 295-300 [doi]
• A low-power digital matched filter for spread-spectrum systemsShoji Goto, Takashi Yamada, Norihisa Takayama, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura. 301-306 [doi]
• Parametric timing and power macromodels for high level simulation of low-swing interconnectsDavide Bertozzi, Luca Benini, Bruno Riccò. 307-312 [doi]
• Compact models for estimating microprocessor frequency and powerWilliam C. Athas, Lynn Youngs, Andrew Reinhart. 313-318 [doi]
• Efficient estimation of signal transition activity in MAC architecturesAlberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner. 319-322 [doi]
• Novel modeling techniques for RTL power estimationMichael Eiermann, Walter Stechele. 323-328 [doi]