Abstract is missing.
- Innovation for Future Connected ComputeVida Ilderem. 1 [doi]
- Coordinating Communication, Technology and Design in the IOT EraRob Aitken. 2 [doi]
- Terahertz Technology and its Applications: Is it All Hype?Goutam Chattopadhyay. 3 [doi]
- Design and Implementation of a 4Kb STT-MRAM with Innovative 200nm Nano-ring Shaped MTJZheng Li, Xiuyuan Bi, Hai Helen Li, Yiran Chen, Jianying Qin, Peng Guo, Wenjie Kong, Wenshan Zhan, Xiufeng Han, Hong Zhang, Lingling Wang, Guanping Wu, HanMing Wu. 4-9 [doi]
- Ferroelectric Transistor based Non-Volatile Flip-FlopDanni Wang, Sumitha George, Ahmedullah Aziz, Suman Datta, Vijaykrishnan Narayanan, Sumeet Kumar Gupta. 10-15 [doi]
- Low Area, Low Power, Robust, Highly Sensitive Error Detecting Latch for Resilient ArchitecturesWeizhe Hua, Ramy N. Tadros, Peter A. Beerel. 16-21 [doi]
- Comprehensive Analysis, Modeling and Design for Hold-Timing Resiliency in Voltage Scalable DesignHuanyu Wang, Geng Xie, Jie Gu. 22-27 [doi]
- TeleProbe: Zero-power Contactless Probing for Implantable Medical DevicesWoo Suk Lee, Younghyun Kim, Vijay Raghunathan. 28-33 [doi]
- SocialHBC: Social Networking and Secure Authentication using Interference-Robust Human Body CommunicationShreyas Sen. 34-39 [doi]
- A Li-Ion Battery Charge Protocol with Optimal Aging-Quality of Service Trade-offYukai Chen, Alberto Bocca, Alberto Macii, Enrico Macii, Massimo Poncino. 40-45 [doi]
- An Energy-Efficient Computational Model for Uncertainty Management in Dynamically Changing Networked WearablesRamyar Saeedi, Ramin Fallahzadeh, Parastoo Alinia, Hassan Ghasemzadeh. 46-51 [doi]
- Energy-Efficient Adaptive Classifier Design for Mobile SystemsZafar Takhirov, Joseph Wang, Venkatesh Saligrama, Ajay Joshi. 52-57 [doi]
- Speeding up Convolutional Neural Network Training with Dynamic Precision Scaling and Flexible Multiplier-AccumulatorTaesik Na, Saibal Mukhopadhyay. 58-63 [doi]
- A Robust and Energy-Efficient Classifier Using Brain-Inspired Hyperdimensional ComputingAbbas Rahimi, Pentti Kanerva, Jan M. Rabaey. 64-69 [doi]
- Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit StudyKwang Min Kim, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim. 70-75 [doi]
- Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICsBon Woong Ku, Peter Debacker, Dragomir Milojevic, Praveen Raghavan, Diederik Verkest, Aaron Thean, Sung Kyu Lim. 76-81 [doi]
- Voltage Noise Induced DRAM Soft Error Reduction Technique for 3D-CPUsTiantao Lu, Caleb Serafy, Zhiyuan Yang, Ankur Srivastava. 82-87 [doi]
- Modeling and implementation of a fully-digital integrated per-core voltage regulation system in a 28nm high performance 64-bit processorRavinder Rachala, Miguel Rodriguez, Stephen Kosonocky, Milos Trajkovic. 88-93 [doi]
- Regenerative Breaking: Recovering Stored Energy from Inactive Voltage Domains for Energy-efficient Systems-on-ChipAli Najafi, Jacques C. Rudell, Visvesh Sathe. 94-99 [doi]
- Analysis and Design of Energy Efficient Time Domain Signal ProcessingZhengyu Chen, Jie Gu. 100-105 [doi]
- SATS: An Ultra-Low Power Time Synchronization for Solar Energy Harvesting WSNsTongda Wu, Yongpan Liu, Hehe Li, Chun Jason Xue, Hyung Gyu Lee, Huazhong Yang. 106-111 [doi]
- DeLight: Adding Energy Dimension To Deep Neural NetworksBita Darvish Rouhani, Azalia Mirhoseini, Farinaz Koushanfar. 112-117 [doi]
- A Light-powered, "Always-On", Smart Camera with Compressed Domain Gesture DetectionAmaravati Anvesha, Shaojie Xu, Ningyuan Cao, Justin Romberg, Arijit Raychowdhury. 118-123 [doi]
- Soft Response Generation and Thresholding Strategies for Linear and Feed-Forward MUX PUFsChen Zhou, Saroj Satapathy, Yingjie Lao, Keshab K. Parhi, Chris H. Kim. 124-129 [doi]
- Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption EnginesMonodeep Kar, Arvind Singh, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay. 130-135 [doi]
- Performance Impact of Magnetic and Thermal Attack on STTRAM and Low-Overhead Mitigation TechniquesJae-Won Jang, Swaroop Ghosh. 136-141 [doi]
- An Energy-Efficient PUF Design: Computing While RacingHongxiang Gu, Teng Xu 0001, Miodrag Potkonjak. 142-147 [doi]
- Extending the Moore's law by exploring new data center architecture: Invited PaperJian Ouyang, Wei Qi, Yong Wang. 148-149 [doi]
- Heterogeneous Computing and Infrastructure for Energy Efficiency in Microsoft Data Centers: Extended AbstractDerek Chiou. 150-151 [doi]
- Dissecting Xeon + FPGA: Why the integration of CPUs and FPGAs makes a power difference for the datacenter: Invited PaperHerman Schmit, Randy Huang. 152-153 [doi]
- Software Infrastructure for Enabling FPGA-Based Accelerations in Data Centers: Invited PaperJason Cong, Muhuan Huang, Peichen Pan, Di Wu, Peng Zhang. 154-155 [doi]
- On Effective and Efficient Quality Management for Approximate ComputingTing Wang, Qian Zhang, Nam Sung Kim, Qiang Xu. 156-161 [doi]
- ACAM: Approximate Computing Based on Adaptive Associative Memory with Online LearningMohsen Imani, Yeseong Kim, Abbas Rahimi, Tajana Rosing. 162-167 [doi]
- Dynamic Approximation with Feedback Control for Energy-Efficient Recurrent Neural Network HardwareJaeha Kung, Duckhwan Kim, Saibal Mukhopadhyay. 168-173 [doi]
- Unified Power Frequency Model FrameworkSriram Sundaram, Warren He, Sriram Sambamurthy, Aaron Grenat, Steven Liepe, Samuel Naffziger. 174-179 [doi]
- Scalable Auto-Tuning of Synthesis Parameters for Optimizing High-Performance ProcessorsMatthew M. Ziegler, Hung-Yi Liu, Luca P. Carloni. 180-185 [doi]
- Overview of IEEE1801-2015: Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems: Invited PaperSushma Honnavara Prasad. 186 [doi]
- Data-Driven Low-Cost On-Chip Memory with Adaptive Power-Quality Trade-off for Mobile Video StreamingDongliang Chen, Jonathon Edstrom, Xiaowei Chen, Wei Jin, Jinhui Wang, Na Gong. 188-193 [doi]
- An Energy-Aware Approach to Noise-Robust Moving Object Detection for Low-Power Wireless Image Sensor PlatformsJong Hwan Ko, Saibal Mukhopadhyay. 194-199 [doi]
- Bit Serializing a Microprocessor for Ultra-low-powerMatthew Tomei, Henry Duwe, Nam Sung Kim, Rakesh Kumar 0002. 200-205 [doi]
- A Programmable Analog-to-Information Converter for Agile BiosensingAosen Wang, Zhanpeng Jin, Wenyao Xu. 206-211 [doi]
- DynSleep: Fine-grained Power Management for a Latency-Critical Data Center ApplicationChih-Hsun Chou, Daniel Wong, Laxmi N. Bhuyan. 212-217 [doi]
- HiCAP: Hierarchical FSM-based Dynamic Integrated CPU-GPU Frequency Capping Governor for Energy-Efficient Mobile GamingJurn-Gyu Park, Nikil D. Dutt, Hoyeonjiki Kim, Sung-Soo Lim. 218-223 [doi]
- Prediction-Guided Performance-Energy Trade-off with Continuous Run-Time AdaptationTaejoon Song, Daniel Lo, G. Edward Suh. 224-229 [doi]
- Therma: Thermal-aware Run-time Thread Migration for Nanophotonic InterconnectsMajed Valad Beigi, Gokhan Memik. 230-235 [doi]
- Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level CachesFabian Oboril, Fazal Hameed, Rajendra Bishnoi, Ali Ahari, Helia Naeimi, Mehdi Baradaran Tahoori. 236-241 [doi]
- Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM CellsChang-Hung Yu, Pin Su, Ching-Te Chuang. 242-247 [doi]
- T-DVS: Temperature-aware DVS based on Temperature Inversion PhenomenonJinsoo Park, Hojung Cha. 248-253 [doi]
- Enhancing DRAM Self-Refresh for Idle Power ReductionByoungchan Oh, Nilmini Abeyratne, Jeongseob Ahn, Ronald G. Dreslinski, Trevor N. Mudge. 254-259 [doi]
- FVCAG: A framework for formal verification driven power modeling and verificationArun Joseph, Spandana Rachamalla, Rahul M. Rao, Anand Haridass, Pradeep Kumar Nalla. 260-265 [doi]
- STOCK: Stochastic Checkers for Low-overhead Approximate Error DetectionNeel Gala, Swagath Venkataramani, Anand Raghunathan, V. Kamakoti. 266-271 [doi]
- Maximizing Energy Efficiency in NTC by Variation-Aware Microprocessor Pipeline OptimizationAnteneh Gebregiorgis, Mohammad Saber Golanbari, Saman Kiamehr, Fabian Oboril, Mehdi Baradaran Tahoori. 272-277 [doi]
- A 386-μW, 15.2-bit Programmable-Gain Embedded Delta-Sigma ADC for Sensor ApplicationsJaehoon Jun, Cyuyeol Rhee, Suhwan Kim. 278-283 [doi]
- Measurement-Driven Methodology for Evaluating Processor Heterogeneity Options for Power-Performance EfficiencyWilliam J. Song, Alper Buyuktosunoglu, Chen-Yong Cher, Pradip Bose. 284-289 [doi]
- A Thermal-Aware Physical Space Allocation Strategy for 3D Flash Memory Storage SystemsYi Wang, Mingxu Zhang, Lisha Dong, Xuan Yang. 290-295 [doi]
- OS-based Resource Accounting for Asynchronous Resource Use in Mobile SystemsFarshad Ghanei, Pranav Tipnis, Kyle Marcus, Karthik Dantu, Steven Y. Ko, Lukasz Ziarek. 296-301 [doi]
- Dynamic Voltage Scaling Using Scene Change Detection for Video Playback on Mobile AMOLED DisplaysByung-Hoon Lee, Young-Jin Kim. 302-307 [doi]
- Can We Guarantee Performance Requirements under Workload and Process Variations?Dimitrios Stamoulis, Diana Marculescu. 308-313 [doi]
- A Low Power Current-Mode Flash ADC with Spin Hall Effect based Multi-Threshold ComparatorZhezhi He, Deliang Fan. 314-319 [doi]
- How to Cope with Slow Transistors in the Top-tier of Monolithic 3D ICs: Design Studies and CAD SolutionsSandeep Kumar Samal, Deepak Nayak, Motoi lchihashi, Srinivasa Banna, Sung Kyu Lim. 320-325 [doi]
- Energy-Efficient CNN Implementation on a Deeply Pipelined FPGA ClusterChen Zhang, Di Wu, Jiayu Sun, Guangyu Sun, Guojie Luo, Jason Cong. 326-331 [doi]
- Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-EfficiencyJinil Chung, Jongsun Park, Swaroop Ghosh. 332-337 [doi]
- Design and implementation of nonvolatile power-gating SRAM using SOTB technologyYusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara. 338-343 [doi]
- An Efficient Parallel Scheduling Scheme on Multi-partition PCM ArchitectureWen Zhou, Dan Feng, Yu Hua, Jingning Liu, Fangting Huang, Yu Chen. 344-349 [doi]
- In-place Repair for Resistive Memories Utilizing Complementary Resistive SwitchesAmirali Ghofrani, Miguel Angel Lastras-Montaño, Yuyang Wang, Kwang-Ting Cheng. 350-355 [doi]
- Reducing Power Consumption of GPGPUs Through Instruction ReorderingHoma Aghilinasab, Mohammad Sadrosadati, Mohammad Hossein Samavatian, Hamid Sarbazi-Azad. 356-361 [doi]
- A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating TechniquesIvan Ratkovic, Oscar Palomar, Milan Stanic, Osman S. Unsal, Adrián Cristal, Mateo Valero. 362-367 [doi]
- Power-Aware Performance Adaptation of Concurrent Applications in Heterogeneous Many-Core SystemsAli Aalsaud, Rishad A. Shafik, Ashur Rafiev, Fei Xia, Sheng Yang, Alex Yakovlev. 368-373 [doi]