Table of Contents

• An Automated Approximation Methodology for Arithmetic CircuitsSayandip De, Jos Huisken, Henk Corporaal. 1-6 [doi]
• K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAMJyotishman Saikia, Shihui Yin, Zhewei Jiang, Mingoo Seok, Jae-sun Seo. 1-6 [doi]
• Temperature-aware Adaptive VM Allocation in Heterogeneous Data CentersYoung-geun Kim, Jeong In Kim, Seung Hun Choi, Seon-Young Kim, Sung Woo Chung. 1-6 [doi]
• Towards a Complete Methodology for Synthesizing Bundled-Data Asynchronous Circuits on FPGAsKshitij Bhardwaj, Paolo Mantovani, Luca P. Carloni, Steven M. Nowick. 1-6 [doi]
• Non-Volatile Memory utilizing Reconfigurable Ferroelectric Transistors to enable Differential Read and Energy-Efficient In-Memory ComputationSandeep Krishna Thirumala, Shubham Jain, Anand Raghunathan, Sumeet Kumar Gupta. 1-6 [doi]
• Compressing Sparse Ternary Weight Convolutional Neural Networks for Efficient Hardware AccelerationHyeonwook Wi, Hyeonuk Kim, Seungkyu Choi, Lee-Sup Kim. 1-6 [doi]
• Automatic GDSII Generator for On-Chip Voltage Regulator for Easy Integration in Digital SoCsVenkata Chaitanya Krishna Chekuri, Nihar Dasari, Arvind Singh, Saibal Mukhopadhyay. 1-6 [doi]
• TIP: A Temperature Effect Inversion-Aware Ultra-Low Power System-on-Chip PlatformKyuseung Han, Sukho Lee, Jae-Jin Lee, Woojoo Lee, Massoud Pedram. 1-6 [doi]
• FPGA-based Acceleration of Binary Neural Network Training with Minimized Off-Chip Memory AccessPavan Kumar Chundi, Peiye Liu, Sangsu Park, Seho Lee, Mingoo Seok. 1-6 [doi]
• A 65nm switched source line sub-threshold ROM using data encoding, with 0.3V Vmin and 47fJ/b access energySupreet Jeloka, Pranay Prabhat, Graham Knight, James Myers. 1-6 [doi]
• Dynamic Spike Bundling for Energy-Efficient Spiking Neural NetworksSarada Krithivasan, Sanchari Sen, Swagath Venkataramani, Anand Raghunathan. 1-6 [doi]
• TEA-DNN: the Quest for Time-Energy-Accuracy Co-optimized Deep Neural NetworksLile Cai, Anne-Maelle Barneche, Arthur Herbout, Chuan-Sheng Foo, Jie Lin, Vijay Ramaseshan Chandrasekhar, Mohamed M. Sabry Aly. 1-6 [doi]
• ®-A MicroprocessorXiaoqing Xu, Mudit Bhargava, Steve Moore, Saurabh Sinha, Brian Cline. 1-6 [doi]
• An Energy-efficient On-chip Learning Architecture for STDP based Sparse CodingHeetak Kim, Hoyoung Tang, Jongsun Park 0001. 1-6 [doi]
• Addressing Temporal Variations in Qubit Quality Metrics for Parameterized Quantum CircuitsMahabubul Alam, Abdullah Ash-Saki, Swaroop Ghosh. 1-6 [doi]
• Battery-Aware Electric Truck Delivery Route PlannerDonkyu Baek, Yukai Chen, Enrico Macii, Massimo Poncino, Naehyuck Chang. 1-6 [doi]
• Robust Low Power Clock Synchronization for Multi-Die SystemsRagh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, Ioannis Savidis. 1-6 [doi]
• Comparative evaluation of Body Biasing and Voltage Scaling for Low-Power Design on 28nm UTBB FD-SOI TechnologyRicardo Gomez Gomez, Edwige Bano, Sylvain Clerc. 1-6 [doi]
• NCFET-Aware Voltage ScalingSami Salamin, Martin Rapp, Hussam Amrouch, Girish Pahwa, Yogesh Singh Chauhan, Jörg Henkel. 1-6 [doi]
• Local Learning in RRAM Neural Networks with Sparse Direct Feedback AlignmentBrian Crafton, Matt West, Padip Basnet, Eric Vogel, Arijit Raychowdhury. 1-6 [doi]
• RAPID: A ReRAM Processing in-Memory Architecture for DNA Sequence AlignmentSaransh Gupta, Mohsen Imani, Behnam Khaleghi, Venkatesh Kumar, Tajana Rosing. 1-6 [doi]
• 3DTUBE: A Design Framework for High-Variation Carbon Nanotube-based Transistor TechnologyAporva Amarnath, Javad Bagherzadeh, Jielun Tan, Ronald G. Dreslinski. 1-6 [doi]
• A Pulse-Width Modulated Cochlear Implant Interface Electronics with 513 µW Power ConsumptionHalil Andaç Yigit, Hasan Ulusan, Muhammed Berat Yuksel, Salar Chamanian, Berkay Çiftci, Aziz Koyuncuoglu, Ali Muhtaroglu, Haluk Külah. 1-5 [doi]
• A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural NetworksTaegeun Yoo, Hyunjoon Kim, Qian Chen, Tony Tae-Hyoung Kim, Bongjin Kim. 1-6 [doi]
• A Design Framework for Thermal-Aware Power Delivery Network in 3D MPSoCs with Integrated Flow Cell ArraysHalima Najibi, Alexandre Levisse, Marina Zapater. 1-6 [doi]
• MemGANs: Memory Management for Energy-Efficient Acceleration of Complex Computations in Hardware Architectures for Generative Adversarial NetworksMuhammad Abdullah Hanif, Muhammad Zuhaib Akbar, Rehan Ahmed, Semeen Rehman, Axel Jantsch, Muhammad Shafique 0001. 1-6 [doi]
• Balancing Memory Accesses for Energy-Efficient Graph Analytics AcceleratorsMingyu Yan, Xing Hu, Shuangchen Li, Itir Akgun, Han Li, Xin Ma, Lei Deng, Xiaochun Ye, Zhimin Zhang, Dongrui Fan, Yuan Xie 0001. 1-6 [doi]
• On Trade-off Between Static and Dynamic Power Consumption in NoC Power GatingDi Zhu 0002, Yunfan Li, Lizhong Chen. 1-6 [doi]
• A Compact Self-Capacitance Sensing Analog Front-End for a Touch Detection in Low-Power ModeJiheon Park, Young Ha Hwang, Jonghyun Oh, Yoonho Song, Jun-Eun Park, Deog Kyoon Jeong. 1-6 [doi]
• A Low-Energy Inductive Transceiver using Spike-Latency Encoding for Wireless 3D IntegrationBenjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak. 1-6 [doi]
• A Low-Power and Low-Noise 20: 1 Serializer with Two Calibration Loops in 55-nm CMOSYong-Un Jeong, Joo-Hyung Chae, Sungphil Choi, Jaekwang Yun, Shin-Hyun Jeong, Suhwan Kim. 1-6 [doi]
• Muffin: Minimally-Buffered Zero-Delay Power-Gating Technique in On-Chip RoutersHossein Farrokhbakht, Hadi Mardani Kamali, Natalie D. Enright Jerger. 1-6 [doi]
• CNN-Based Camera-less User Attention Detection for Smartphone Power ManagementDaniele Jahier Pagliari, Matteo Ansaldi, Enrico Macii, Massimo Poncino. 1-6 [doi]
• Tier Partitioning and Flip-flop Relocation Methods for Clock Trees in Monolithic 3D ICsDa Eun Shim, Sai Pentapati, Jeehyun Lee, Yun Seop Yu, Sung Kyu Lim. 1-6 [doi]
• BottleNet: A Deep Learning Architecture for Intelligent Mobile Cloud Computing ServicesAmir Erfan Eshratifar, Amirhossein Esmaili, Massoud Pedram. 1-6 [doi]
• MessageFusion: On-path Message Coalescing for Energy Efficient and Scalable Graph AnalyticsLeul Belayneh, Abraham Addisie, Valeria Bertacco. 1-6 [doi]
• CompHD: Efficient Hyperdimensional Computing Using Model CompressionJustin Morris, Mohsen Imani, Samuel Bosch, Anthony Thomas, Helen Shu, Tajana Rosing. 1-6 [doi]
• Improving Energy Efficiency by Memoizing Data Access InformationMichael Stokes, Ryan Baird, Zhaoxiang Jin, David B. Whalley, Soner Önder. 1-6 [doi]
• WMixNet: An Energy-Scalable and Computationally Lightweight Deep Learning AcceleratorSangwoo Jung, Seungsik Moon, Youngjoo Lee, Jaeha Kung. 1-6 [doi]
• Similarity-Based LSTM Architecture for Energy-Efficient Edge-Level Speech RecognitionJunseo Jo, Jaeha Kung, Sunggu Lee, Youngjoo Lee. 1-6 [doi]
• 3AM: A Heat Resilient Design for RRAM-based Neuromorphic ComputingXiao Liu, Mingxuan Zhou, Tajana S. Rosing, Jishen Zhao. 1-6 [doi]
• Autonomous I/O for Intermittent IoT SystemsYu-Chen Lin, Pi-Cheng Hsiu, Tei-Wei Kuo. 1-6 [doi]
• A Probabilistic Approach to Energy-Constrained Mixed-Criticality SystemsFederico Reghenzani, Giuseppe Massari, William Fornaciari. 1-6 [doi]
• SHINE: A Novel SHA-3 Implementation Using ReRAM-based In-Memory ComputingKarthikeyan Nagarajan, Sina Sayyah Ensan, Mohammad Nasim Imtiaz Khan, Swaroop Ghosh, Anupam Chattopadhyay. 1-6 [doi]
• A Sound Activity Detector Embedded Low-Power MEMS Microphone Readout Interface for Speech RecognitionYoungtae Yang, Jun Soo Cho, Byunggyu Lee, Suhwan Kim. 1-6 [doi]
• 2M: Approximate Algebraic Memory Using Polynomials RingsDong Kai Wang, Nam Sung Kim. 1-6 [doi]
• Exploring the Relation between Monolithic 3D L1 GPU Cache Capacity and Warp Scheduling EfficiencyCong Thuan Do, Young-Ho Gong, Cheol Hong Kim, Seon Wook Kim, Sung Woo Chung. 1-6 [doi]
• Power Delivery Resonant Virus: Concept and ApplicationsTianhao Shen, Di Gao, Yiyu Shi, Cheng Zhuo. 1-6 [doi]
• FLASH: Content-based Power-saving Design for Scrolling Operations in Browser Applications on Mobile OLED DevicesHao-Chun Chang, Yu Chieh Yang, Liang-Yan Yu, Chun-Han Lin. 1-6 [doi]
• SHRIMP: Efficient Instruction Delivery with Domain Wall MemoryJoonas Multanen, Pekka Jääskeläinen, Asif Ali Khan, Fazal Hameed, Jerónimo Castrillón. 1-6 [doi]
• Rethinking Last-level-cache Write-back Strategy for MLC STT-RAM Main Memory with Asymmetric Write EnergyYu-Pei Liang, Tseng-Yi Chen, Yuan-Hao Chang, Shuo-Han Chen, Pei-yu Chen, Wei Kuan Shih. 1-6 [doi]
• VCAM: Variation Compensation through Activation Matching for Analog Binarized Neural NetworksJaehyun Kim, Chaeun Lee, Jihun Kim, Yumin Kim, Cheol Seong Hwang, Kiyoung Choi. 1-6 [doi]
• SECO: A Scalable Accuracy Approximate Exponential Function Via Cross-Layer OptimizationDi Wu, Tianen Chen, Chienfu Chen, Oghenefego Ahia, Joshua San Miguel, Mikko Lipasti, Younghyun Kim. 1-6 [doi]
• Energy-Autonomous MCU Operating in sub-VT Regime with Tightly-Integrated Energy-Harvester : A SoC for IoT smart nodes containing a MCU with minimum-energy point of 2.9pJ/cycle and a harvester with output power range from sub-µW to 4.32mWJian Deng, Jean-Luc Nagel, Loïc Zahnd, Marc Pons, David Ruffieux, Claude Arm, Pascal Persechini, Stéphane Emery. 1-4 [doi]
• Modeling and Optimization of Chip Cooling with Two-Phase Vapor ChambersZihao Yuan, Geoffrey Vaartstra, Prachi Shukla, Sherief Reda, Evelyn Wang, Ayse K. Coskun. 1-6 [doi]
• Concurrent Multipoint-to-Multipoint Communication on Interposer ChannelsLejie Lu, Richard Afoakwa, Michael Huang, Hui Wu. 1-6 [doi]
• An Ultra-Efficient Memristor-Based DNN Framework with Structured Weight Pruning and Quantization Using ADMMGeng Yuan, Xiaolong Ma, Caiwen Ding, Sheng Lin, Tianyun Zhang, Zeinab S. Jalali, Yilong Zhao, Li Jiang, Sucheta Soundarajan, Yanzhi Wang. 1-6 [doi]