Table of Contents

• Equations in the Algebra of LogicSergiu Rudeanu. 2 [doi]
• Some Results on the Centralizers of Monoids in Clone TheoryHajime Machida, Masahiro Miyakawa, Ivo G. Rosenberg. 10-16 [doi]
• Partial Hyperclones on a Finite SetB. A. Romov. 17-22 [doi]
• On the Structures of Weak Interlaced BilatticeMichiro Kondo. 23 [doi]
• Improving the Characterization of p-Valued Threshold FunctionsClaudio Moraga. 28-34 [doi]
• A Conjunctive Canonical Expansion of Multiple-Valued FunctionsElena Dubrova, Petra Färm. 35-38 [doi]
• Sierpinski Gaskets for Logic Functions RepresentationDenis V. Popel, Anita Dani. 39-45 [doi]
• Logic for Static Hazard Detection of Multiple-Valued Logic Circuits with Tsum, Min, and LiteralsNoboru Takagi, Kyoichi Nakashima. 46 [doi]
• Multiple-Valued Data Recovery Techniques for Band-Limited Channels in VLSIYasushi Yuminaka, Tatsuya Morishita, Takafumi Aoki, Tatsuo Higuchi. 54-60 [doi]
• An Impact of Introducing Multi-Level Signals to a Bandpass Cascaded Delta-Sigma ModulatorTakao Waho, Shin-ya Kobayashi, Koji Matsuura. 61-66 [doi]
• Voltage Comparator Circuits for Multiple-Valued CMOS LogicYongjian Brandon Guo, K. Wayne Current. 67 [doi]
• Efficient Calculation of Fixed-Polarity Polynomial Expressions for Multiple-Valued Logic FunctionsDragan Jankovic, Radomir S. Stankovic. 76-82 [doi]
• Comparison of Different Features of Quaternary Reed-Muller Canonical Forms and Some New Statistical ResultsK. J. Adams, J. McGregor. 83-88 [doi]
• Design and Implementation of Error Detection and Correction Circuitry for Multilevel Memory ProtectionBoris Polianskikh, Zeljko Zilic. 89-95 [doi]
• Parallel Evolutionary Graph Synthesis on a PC Cluster and Its Application to Multiple-Valued Circuit SynthesisMasanori Natsui, Takafumi Aoki, Tatsuo Higuchi. 96 [doi]
• Consequence and Complexity in Infinite-Valued Logic: A SurveyVincenzo Marra, Daniele Mundici. 104 [doi]
• Some Remarks on Linear Transform of Variables in Representation of Adders by Word-Level Expressions and Spectral Transform Decision DiagramsRadomir S. Stankovic, Jaakko Astola. 116-122 [doi]
• Chrestenson Spectrum Computation Using Cayley Color GraphsMitchell A. Thornton, D. Michael Miller, Whitney J. Townsend. 123-129 [doi]
• The Role of Super-Fast Transforms in Speeding Up Quantum ComputationsZeljko Zilic, Katarzyna Radecka. 129-135 [doi]
• Multiple-Valued and Spectral Approach to Lossless Compression of Binary, Gray Scale and Color Biomedical ImagesBogdan J. Falkowski, Beata T. Olejnicka. 136 [doi]
• Design of Dynamic Reliability IndicesElena N. Zaitseva, Vitaly G. Levashenko. 144-148 [doi]
• PODEM Based on Static Testability Measures and Dynamic Testability Measures for Multiple-Valued Logic CircuitsNaotake Kamiura, Teijiro Isokawa, Nobuyuki Matsui. 149-155 [doi]
• Design of Ternary Schmitt Triggers Based on Its Sequential CharacteristicsYinshui Xia, Xunwei Wu, Penjung Wang. 156-160 [doi]
• Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge AdditionHiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama. 161 [doi]
• Optimization of Multi-Valued Multi-Level NetworksRobert K. Brayton, M. Gao, Jie-Hong Roland Jiang, Yunjian Jiang, Yinghua Li, Alan Mishchenko, Subarnarekha Sinha, Tiziano Villa. 168 [doi]
• de Morgan Bisemilattice of Fuzzy Truth ValueHiroaki Kikuchi, Noboru Takagi. 180-184 [doi]
• Independence of Each Axiom in a Set of Axioms and Complete Sets of Axioms of Boolean AlgebraTomoko Ninomiya, Masao Mukaidono. 185-191 [doi]
• On Functions Defined on Free Boolean AlgebrasIvo G. Rosenberg, Dan A. Simovici, Szymon Jaroszewicz. 192 [doi]
• The Word-Level Models for Efficient Computation of Multiple-Valued Functions. PART 1: LAR Based ModelSvetlana N. Yanushkevich, Piotr Dziurzanski, Vlad P. Shmerko. 202-208 [doi]
• The Word-Level Models for Efficient Computation of Multiple-Valued Functions. PART 2: LWL Based ModelAnna M. Tomaszewska, Svetlana N. Yanushkevich, Vlad P. Shmerko. 209-215 [doi]
• Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued LogicsIlia Polian, Piet Engelke, Bernd Becker. 216 [doi]
• Multiple-Valued-Digit Number Representations in Arithmetic Circuit AlgorithmsNaofumi Takagi. 224 [doi]
• Variable Selection Heuristics and Optimum Decision Trees - An Experimental StudyMasahiro Miyakawa, Nobuyuki Otsu, Ivo G. Rosenberg. 238-244 [doi]
• On the Construction of Multiple-Valued Decision DiagramsD. Michael Miller, Rolf Drechsler. 245-253 [doi]
• Evaluation of Static Variable Ordering Heuristics for MDD ConstructionRolf Drechsler. 254-260 [doi]
• Representations of Logic Functions Using QRMDDsShinobu Nagayama, Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura. 261 [doi]
• Fully Source-Coupled Logic Based Multiple-Valued VLSITsukasa Ike, Takahiro Hanyu, Michitaka Kameyama. 270-275 [doi]
• A Current-Mode Folding/Interpolating CMOS Analog to Quaternary Converter Using Binary to Quaternary Encoding BlockSung Il Han, Seung-Yong Park, Hyeon Kyeong Seong, Heung-Soo Kim. 276-281 [doi]
• Multi-Valued Flip-Flop with Neuron-CMOS NMIN CircuitsMotoi Inaba, Koichi Tanno, Okihiko Ishizuka. 282 [doi]