Abstract is missing.
- Hard vs. Soft: The Central Question of Pre-Fabricated SiliconJonathan Rose. 2-5 [doi]
- Multiple-Input Resonant-Tunneling Logic Gates for Flash A/D Converter ApplicationsYuki Tsuji, Takao Waho. 8-13 [doi]
- A Novel Multiple-Valued Logic Design Using Ballistic Carbon Nanotube FETsArijit Raychowdhury, Kaushik Roy. 14-19 [doi]
- Multiple-Valued Multiple-Rail Encoding Scheme for Low-Power Asynchronous CommunicationTomohiro Takahashi, Takahiro Hanyu. 20-25 [doi]
- Ultra-Fine-Grain Field-Programmable VLSI Using Multiple-Valued Source-Coupled LogicHaque Mohammad Munirul, Michitaka Kameyama. 26-30 [doi]
- Resolution-Based Decision Procedures for the Positive Theory of Some Finitely Generated Varieties of AlgebrasViorica Sofronie-Stokkermans. 32-37 [doi]
- Uniform Description of Calculi for All t-Norm LogicsStefano Aguzzoli. 38-43 [doi]
- Weakly Associative Functions on [0, 1] as Logical ConnectivesMayuka F. Kawaguchi, Masaaki Miyakoshi. 44-48 [doi]
- Automata over MV-AlgebraBrunella Gerla. 49-54 [doi]
- Quantum Communication Complexity: A SurveyGilles Brassard. 56 [doi]
- Ternary Galois Field Expansions for Reversible Logic and Kronecker Decision Diagrams for Ternary GFSOP MinimizationMozammel H. A. Khan, Marek A. Perkowski, Mujibur R. Khan. 58-67 [doi]
- On Universality of General Reversible Multiple-Valued Logic GatesPawel Kerntopf, Marek A. Perkowski, Mozammel H. A. Khan. 68-73 [doi]
- A Synthesis Method for MVL Reversible LogiD. Michael Miller, Gerhard W. Dueck, Dmitri Maslov. 74-80 [doi]
- Reversible Fast Permutation Transforms for Quantum Circuit SynthesiAnas N. Al-Rabadi. 81-86 [doi]
- Quantum Circuit Synthesis Using Classes of GF(3) Reversible Fast Spectral TransformsAnas Al-Rabadi. 87-93 [doi]
- On Partial Clones containing Maximal ClonesLucien Haddad, Dietlinde Lau. 96-101 [doi]
- Monoids whose Centralizer is the Least CloneHajime Machida, Ivo G. Rosenberg. 102-108 [doi]
- Algebraic Properties of Totally Irreducible Elements of Clone LatticesGrant Pogosyan, Ivo G. Rosenberg. 109-114 [doi]
- Minimal Partial Hyperclones on a Two-Element SetJovanka Pantovic, Gradimir Vojvodic. 115-119 [doi]
- Some Properties of Local Partial Clones on an Infinite SetB. A. Romov. 120-125 [doi]
- Signed Digit CMOS (SD-CMOS) Logic Circuits with Static OperationHideki Fukuda. 128-134 [doi]
- A Systolic Parallel Multiplier over GF(3m) Using Neuron-MOS DLCOmid Mirmotahari, Yngvar Berg. 135-138 [doi]
- Optimizing the Defuzzifier Timing for the Fuzzy Control of a ServodriveDan Mihai. 142-147 [doi]
- A Metasemantics to Refine Fuzzy If-Then RulesClaudio Moraga. 148-153 [doi]
- Evolutionary Strategy for Learning Multiple-Valued Logic FunctionsAlioune Ngom, Dan A. Simovici, Ivan Stojmenovic. 154-160 [doi]
- Fast Optimization of Fixed-Polarity Reed-Muller Expansions over GF(5)Bogdan J. Falkowski, Cicilia C. Lozano, Susanto Rahardja. 162-167 [doi]
- On the Optimisation of Reed-Muller ExpressionsK. J. Adams, J. McGregor. 168-176 [doi]
- Spectra Generation for Fixed-Polarity Reed-Muller Transform over GF(5)Bogdan J. Falkowski, Cicilia C. Lozano, Susanto Rahardja. 177-183 [doi]
- Derivatives for Multiple-Valued Functions Induced by Galois Field and Reed-Muller-Fourier ExpressionsRadomir S. Stankovic, Claudio Moraga, Jaakko Astola. 184-189 [doi]
- Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued EncodingAkira Mochizuki, Takashi Takeuchi, Takahiro Hanyu. 192-197 [doi]
- Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal CircuitSoo-Jin Park, Byoung Hee Yoon, Kwang Sub Yoon, Heung-Soo Kim. 198-203 [doi]
- A Self-Restored Current-Mode CMOS Multiple-Valued Logic Design Technique and its ApplicationsDaniel H. Y. Teng, Ronald J. Bolton. 204-209 [doi]
- A Novel D-Latch in Multiple-Valued Semi-Floating-Gate Recharged LogicOmid Mirmotahari, Yngvar Berg. 210-213 [doi]
- On the Minimization of Average Path Lengths for Heterogeneous MDDsShinobu Nagayama, Tsutomu Sasao. 216-222 [doi]
- Reduction of Sizes of Multi-Valued Decision Diagrams by Copy PropertieDragan Jankovic, Radomir S. Stankovic, Rolf Drechsler. 223-228 [doi]
- Edge-Valued Decision Diagrams for Multiple-Valued FunctionsRadomir S. Stankovic, Jaakko Astola. 229-234 [doi]
- Algorithms for Taylor Expansion DiagramsGörschwin Fey, Rolf Drechsler, Maciej J. Ciesielski. 235-240 [doi]
- Polynomial Functions on a Central RelationDietmar Schweigert. 242-244 [doi]
- A Graph-Theoretical Approach to Boolean Interpolation of Non-Boolean FunctionsSergiu Rudeanu, Dan A. Simovici. 245-250 [doi]
- The Interface between P and NP in Signed CNF FormulasCarlos Ansótegui, Ramón Béjar, Alba Cabiscol, Felip Manyà. 251-256 [doi]
- Characterization Theorem of Lattice Implication AlgebraMichiro Kondo. 257-260 [doi]
- A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode LogicKatsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi. 262-268 [doi]
- A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch FunctionsHiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi. 269-274 [doi]
- Three Dimensional Multiple Valued Circuits Design Based on Single-Electron LogicSvetlana N. Yanushkevich, Vlad P. Shmerko, L. Guy, D. C. Lu. 275-280 [doi]
- Non-Deterministic MatricesArnon Avron, Iddo Lev. 282-287 [doi]
- Controlling Uncertainty in Discretization of Continuous DataDenis V. Popel, Elena I. Popel. 288-293 [doi]
- Many Valued Probability TheoryCharles G. Morgan. 294-299 [doi]
- A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT CascadesYukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura. 302-308 [doi]
- A Polynomial Time Algorithm for Non-Disjoint Decomposition of Multiple-Valued FunctionsElena Dubrova. 309-314 [doi]
- Iterative-Based Minimization of Unary 4-Valued Functions for Current-Mode CMOS RealizationMostafa H. Abd-El-Barr, Louai Al-Awami. 315-320 [doi]
- On the Minimization of Multiple-Valued Input Binary-Valued Output FunctionsHafiz Md. Hasan Babu, Moinul Islam Zaber, Md. Rafiqul Islam, Md. Mazder Rahman. 321-326 [doi]
- Multiple-Valued Source-Coupled Logic VLSI Based on Adaptive Threshold Control and Its ApplicationsHaque Mohammad Munirul, Michitaka Kameyama. 328-333 [doi]
- Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITHKazuya Ishida, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi. 334-339 [doi]
- A Study of Multiple-Valued Magnetoresistive RAM (MRAM) Using Binary MTJ DevicesHiromitsu Kimura, Kostas Pagiamtzis, Ali Sheikholeslami, Takahiro Hanyu. 340-345 [doi]
- Basic Multiple-Valued Functions Using Recharge CMOS LogicYngvar Berg, Snorre Aunet, Øivind Næss, Omid Mirmotahari. 346-351 [doi]