Table of Contents

• A 60GHz defected ground power divider using SiGe BiCMOS technologyKaixue Ma, Shouxian Mou, Yang Lu, Kok Meng Lim, Kiat Seng Yeo. 1-4 [doi]
• Design consideration for 60 GHz SiGe power amplifier with ESD protectionKeping Wang, Kaixue Ma, Kiat Seng Yeo. 5-8 [doi]
• A DC to 14GHz fully differential amplifier for wideband low power applicationsBharatha Kumar Thangarasu, Kaixue Ma, Kiat Seng Yeo, Shouxian Mou, Mahalingam Nagarajan. 9-12 [doi]
• SiGe BiCMOS power amplifiers for 60GHz ISM band applicationsRenjing Pan, Jiangmin Gu, Kiat Seng Yeo, Wei Meng Lim, Kaixue Ma. 13-16 [doi]
• Wide center-tape balun for 60 GHz silicon RF ICsFanyi Meng, Kiat Seng Yeo, Shanshan Xu, Kaixue Ma, Chee Chong Lim. 17-19 [doi]
• A 60GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiverKenichi Okada. 20-23 [doi]
• Ultra-low power and low voltage circuit design for next-generation power-aware LSI applicationsTetsuya Hirose. 24-27 [doi]
• A 21 V output charge pump circuit with appropriate well-bias supply technique in 0.18 μm Si CMOSAtsushi Shirane, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu. 28-31 [doi]
• A ring-VCO-based injection-locked frequency multiplier using a new pulse generation technique in 65 nm CMOSNorifumi Kanemaru, Sho Ikeda, Tatsuya Kamimura, Sang-yeop Lee, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu. 32-35 [doi]
• Bandwidth enhancement for high speed amplifier utilizing mutually coupled on-chip inductorsAkira Tsuchiya, Takeshi Kuboki, Yusuke Ohtomo, Keiji Kishine, Shigekazu Miyawaki, Makoto Nakamura, Hidetoshi Onodera. 36-39 [doi]
• A selective-input non-binary LDPC decoder architectureYeong-Luh Ueng, Chung-Jay Yang, Shu-Wei Chen, Wei-Xuan Wu. 40-43 [doi]
• Memory efficient decoder design of nonbinary LDPC codesKai He, Jin Sha, Zhongfeng Wang. 44-47 [doi]
• Flexible and efficient FEC decoders supporting multiple transmission standardsYun Chen, Changsheng Zhou, Yuebin Huang, Shuangqu Huang, Xiaoyang Zeng. 48-53 [doi]
• A common flexible architecture for Turbo/LDPC codesYuebin Huang, Chen Chen 0011, Changsheng Zhou, Yun Chen, Xiaoyang Zeng. 54-57 [doi]
• Efficient Reed-Solomon based LDPC decodersChuan Zhang, Sang-Min Kim, Jin Sha. 58-61 [doi]
• A range-scaled 13b 100MS/s 0.13μm CMOS SHA-free ADC based on a single referenceDong-Hyun Hwang, Jung Eun Song, Sang-Pil Nam, Hyo-Jin Kim, Tai-Ji An, Kwang-Soo Kim, Seung-Hoon Lee. 62-65 [doi]
• A 7.5mW 101dB SNR low-power high-performance audio delta-sigma modulator utilizing opamp sharing techniqueDaisuke Kanemoto, Toru Ido, Kenji Taniguchi 0001. 66-69 [doi]
• Design of a 12-b asynchronous SAR CMOS ADCJinwoo Kim, Shin-Il Lim, Kwang Sub Yoon, Sangmin Lee. 70-72 [doi]
• A ΔΣ ADC using 4-bit SAR type quantizer for audio applicationsJin Seon Kim, Tae In Kwon, Gil-Cho Ahn, Yi-Gyeong Kim, Jong-Kee Kwon. 73-75 [doi]
• Hybrid loopfilter sigma-delta modulator with NTF zero compensationArshad Hussain, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins. 76-79 [doi]
• A fine-grained timing driven synthesis of arithmetic circuitsJoohan Kim, Taewhan Kim. 80-83 [doi]
• An efficient GPIO block design methodology using formalized SFR descriptionSik Kim, Kwang-Hyun Cho, Byeong Min. 84-87 [doi]
• Variation-aware aging analysis with non-Gaussian parametersJoonee Choung, Sangwoo Han, Byung-Su Kim, Juno Kim. 88-91 [doi]
• Fast design space exploration for mixed hardware-software embedded systemsYuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada. 92-95 [doi]
• Path search engine for fast optimal path search using efficient hardware architectureInhyuk Choi, Taewoo Han, Ilwoong Kim, Sungho Kang. 96-99 [doi]
• FPGA implementation of unified kernel structure for MDCT/IMDCT in audio coding schemesHi-Seok Kim, Sea-Ho Kim, Ki-Seok Chung. 100-103 [doi]
• Integrated Passive Device based RF circuit design for low-cost System-in-Package transceiversDa-Chiang Chang, Yuan-Chia Hsu, Ta-Yeh Lin, Ying-Zong Juang, Ibrahim Haroun. 104-107 [doi]
• Isolation performance of sub-harmonic Gilbert mixersHung-Ju Wei, Chinchun Meng, Yi-Chen Lin. 108-111 [doi]
• Low-noise amplifiers with robust ESD protection for RF SOCShawn S. H. Hsu, Ming-Hsien Tsai. 112-115 [doi]
• Design of millimeter-wave CMOS frequency triplerTzu-Chao Yan, Chien-Nan Kuo. 116-119 [doi]
• A low-power CMOS LNA using noise suppression and distortion cancellation techniques with inductive bandwidth extensionChin-Fu Li, Chang-Ming Lai, Ping-Chuan Chiang, Po-Chiun Huang. 120-123 [doi]
• Developing through-silicon stacking process using 3-D CMOS imager as a test vehicleDing-Ming Kwai, Ka-Yi Yeh. 124-126 [doi]
• TSV fault-tolerant mechanisms with application to 3D clock networksChiao-Ling Lung, Jui-Hung Chien, Yiyu Shi, Shih-Chieh Chang. 127-130 [doi]
• RSCE-aware ultra-low-voltage 40-nm CMOS circuitsJinn-Shyan Wang, Keng-Jui Chang, Shu-Yi Yang, Tsung-Han Hsieh, Chingwei Yeh. 131-134 [doi]
• TSV density-driven global placement for 3D stacked ICsDae-Hyun Kim, Rasit Onur Topaloglu, Sung Kyu Lim. 135-138 [doi]
• Physical hierarchy exploration of 3D processorsGuojie Luo. 139-141 [doi]
• Clock design techniques considering circuit reliabilityYongHwan Kim, Minseok Kang, Kyoung-Hwan Lim, Sangdo Park, Deokjin Joo, Taewhan Kim. 142-145 [doi]
• Analysis of jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurementsMasato Sakurai, Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Takahiro J. Yamaguchi, Haruo Kobayashi. 146-149 [doi]
• Stress-balance Flip-Flops for NBTI tolerant circuit based on Fine-Grain RedundancyTeruki Nakasato, Toru Nakura, Kunihiro Asada. 150-153 [doi]
• Aspect enhanced functional coverage driven verification in the SystemC HDVLChristoph Kuznik, Wolfgang Müller 0003. 154-157 [doi]
• Beyond UVM for practical SoC verificationYoung-Nam Yun, Jae-Beom Kim, Nam-Do Kim, Byeong Min. 158-162 [doi]
• Impacts of NBTI/PBTI on SRAM VMIN and design techniques for SRAM VMIN improvementTony Tae-Hyoung Kim, Zhi-Hui Kong. 163-166 [doi]
• Low power semi-static TSPC D-FFs using split-output latchTomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo. 167-170 [doi]
• Low-power non-coherent data and power recovery circuit for implantable biomedical devicesBenjamin P. Wilkerson, Tae-Ho Kim, Jin-Ku Kang. 171-174 [doi]
• Leakage current modeling for GPGPU systemsJungil Ahn, Jinwook Kim, Young-Hwan Kim. 175-178 [doi]
• SRAM read-assist scheme for high performanc low power applicationsAli Valaee, Asim J. Al-Khalili. 179-182 [doi]
• A 48-dB dynamic gain range/stage linear-in-dB low power Variable Gain Amplifier for direct-conversion receiversShang-Hsien Yang, Chua-Chin Wang. 182-1 [doi]
• Hardware multitasking in dynamically partially reconfigurable FPGA-based embedded systemsKrzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada. 183-186 [doi]
• Design consideration for reconfigurable processor DS-HIE - Trade-off between performance and chip areaKazuya Tanigawa, Tetsuo Hironaka. 187-190 [doi]
• Automated architecture exploration for low energy reconfigurable AGUIttetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai. 191-194 [doi]
• A vector coprocessor architecture for embedded systemsYi Ge, Yoshimasa Takebe, Masahiko Toichi, Makoto Mouri, Makiko Ito, Yoshio Hirose, Hiromasa Takahashi. 195-198 [doi]
• Research activities on reconfigurable systems in JapanTomonori Izumi. 199-202 [doi]
• A vertical-MOSFET-based digital core circuit for high-speed low-power vector matchingYitao Ma, Tetsuo Endoh, Tadashi Shibata. 203-206 [doi]
• Rethinking processor instruction fetch: Inefficiencies-cracking mechanismMochamad Asri, Naoki Fujieda, Kenji Kise. 207-210 [doi]
• A novel sequential tree algorithm based on the status of the processing nodes to reduce congestionKi-woong Eom, Won-young Chung, Yong-Surk Lee. 211-214 [doi]
• Division-less high-radix interleaved modular multiplication using a scaled modulusJinook Song, In-Cheol Park. 215-218 [doi]
• Design of timing-error-resilient systolic arrays for matrix multiplicationHsin-Chou Chi, Hsi-Che Tseng, Kun-Lin Tsai. 219-222 [doi]
• A 10.3Gbps translmpedance amplifier with mutually coupled inductors in 0.18-μm CMOSShigekazu Miyawaki, Makoto Nakamura, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera. 223-226 [doi]
• A study on wide-band frequency synthesizer for advanced wireless communicationNak Yoon Kim, Yong Moon. 227-230 [doi]
• A 5-Gb/s low-power transmitter with voltage-mode output driver in 90nm CMOS technologyJinsoo Rhim, Woo-Young Choi. 231-234 [doi]
• A 34 dBm IP0.1dB SOI SP3T switch with an integrated negative-bias switch controller at 2.4 GHzSunwoo Yoon, JuYoung Jung, Dong-Hyun Baek. 235-237 [doi]
• Design considerations for cognitive radio based CMOS TV white space transceiversJongsik Kim, Hyunchol Shin. 238-241 [doi]
• A double-quadrature down-conversion mixer in 0.18 μm SiGe BiCMOS processJinna Yan, Kok Meng Lim, Jiangmin Gu, Keping Wang, Wei Meng Lim, Kaixue Ma, Kiat Seng Yeo. 246-249 [doi]
• Triple module redundancy scheme on an optically reconfigure gate arrayYuki Torigai, Minoru Watanabe. 250-253 [doi]
• Ultra low power active 60 GHz Bi-CMOS down-conversion mixerKok Meng Lim, Jiangmin Gu, Jinna Yan, Wei Meng Lim, Yang Lu, Kiat Seng Yeo. 254-257 [doi]
• A 60GHz BiCMOS self-demodulator with injection locked oscillatorZhenghao Lu, Xiaopeng Yu, Kiat Seng Yeo, Wei Meng Lim, Jinna Yan, Renjing Pan. 258-261 [doi]
• Design of AdaBoost classifier circuit using Haar-like features for automobile applicationsSangkyun Park, Seonyoung Lee, Soojin Kim, Kyeongsoon Cho. 262-265 [doi]
• Image acquisition design of the AOTF imaging spectrometer based on SOPCXuan Cheng, Huijie Zhao, Yonglong Dai, Xiaokang Liu. 266-269 [doi]
• Efficient program control schemes for Motion Estimation specific processorSung Dae Kim, Myung Hoon Sunwoo. 270-273 [doi]
• Two-step local dimming for image quality preservation in LCD displaysSung In Cho, Hi-Seok Kim, Young-Hwan Kim. 274-277 [doi]
• A 166.7 Mhz 1920×1080 60fps H.264/SVC video decoderSeunghyun Cho, SeongMo Park, Nak-Woong Eum. 278-281 [doi]
• Effective readout pixel sensor circuit design for infrared focal plane array and three-dimension image MEMS VLSI systemYun Yang. 286-289 [doi]
• Time-interleaved sample clock generator for ultrasound beamformer applicationJae-Hwan Kim, Ji-Yong Um, Jae-Yoon Sim, Hong June Park. 290-293 [doi]
• Boosted gain programmable Opamp with embedded gain monitor for dependable SoCsJinbo Wan, Hans G. Kerkhoff. 294-297 [doi]
• CMOS low-noise signal conditioning with a novel differential "resistance to frequency" converter for resistive sensor applicationsPriyanka Kabara, Sanket Thakur, Gururaj Saileshwar, Maryam Shojaei Baghini, Dinesh Kumar Sharma. 298-301 [doi]
• Statistical modeling of capacitor mismatch effects for successive approximation register ADCsYoungjoo Lee, Jinook Song, In-Cheol Park. 302-305 [doi]
• Standard cell library establishment and simulation for scan D flip-flops based on 0.5 micron CMOS mixed-signal processChun Zhao, W. Zhang, C. Z. Zhao, Ka Lok Man, Taikyeong T. Jeong, J. K. Seon, Y. Lee. 306-309 [doi]
• A novel radio propagation and radiation model of the wireless capsule endoscopy in human gastro-intestine (GI) tractEng Gee Lim, Zhao Wang, Tammam Tillo, Tuck Seng Wong, Ka Lok Man, Khin Wee Lai. 310-312 [doi]
• Performance-effective compaction of standard cell library for edge-triggered latches utilizing 0.5 micron technologyChun Zhao, W. Pan, C. Z. Zhao, Ka Lok Man, J. Choi, J. Chang. 313-316 [doi]
• Design for testability in nano-CMOS analog integrated circuits using a new design analog checkerMouna Karmani, Ka Lok Man, Chiraz Khedhiri, Belgacem Hamdi. 317-320 [doi]
• Design, analysis, tools and applications for programmable high-speed and power-aware 4G processorsKa Lok Man, Jieming Ma, T. T. Jeong, Chi-Un Lei, Yanyan Wu, Sheng Uei Guan, J. K. Seon, Yunsik Lee. 321-324 [doi]
• A low-cost, ultra sensitive hand-held system for explosive detection using piezo-resistive micro-cantileversNeena A. Gilda, Sandeep Goud Surya, Sanjay Joshi, Viral Thaker, Maryam Shojaei Baghini, Dinesh Kumar Sharma, V. Ramgopal Rao. 325-328 [doi]
• A quick overview of carbon nanotubes and graphene applications for future electronicsDidier Pribat. 329-332 [doi]
• Symmetrical triple-threshold-voltage nine-transistor SRAM circuit with superior noise immunity and overall electrical qualityHong Zhu, Volkan Kursun. 333-336 [doi]
• Compact thermal models: Assessment and pitfallsJaeha Kung, Youngsoo Shin. 337-340 [doi]
• A power grid optimization algorithm considering timing degradation by NBTIMasahiro Fukui, Yoriaki Nagata, Shuji Tsukiyama. 341-344 [doi]
• Design time stamp hardware unit supporting IEEE 1588 standardJae-Won Park, Jin-Ha Hwang, Won-young Chung, Seung Woo Lee, Yong-Surk Lee. 345-348 [doi]
• A scalable multi-ASIP architecture for standard compliant trellis decodingChristian Brehm, Thomas Ilnseher, Norbert Wehn. 349-352 [doi]
• 3D network-on-chip with wireless links through inductive couplingJinho Lee, Mingyang Zhu, Kiyoung Choi, Jung Ho Ahn, Rohit Sharma. 353-356 [doi]
• 10G/1G dual-rate EPON OLT LSI with dual encryption modes alternated using DBA-information-based algorithm controlSadayuki Yasuda, Takahiro Hatano, Hiroki Suto, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata. 357-360 [doi]
• A host-accelerator communication architecture design for efficient binary accelerationYangsu Kim, Kyuseung Han, Kiyoung Choi. 361-364 [doi]
• Low area and high speed SHA-1 implementationEun-Gu Jung, Daewan Han, Jeong-Gun Lee. 365-367 [doi]
• An efficient design of split-radix FFT pruning for OFDM based Cognitive Radio systemYihu Xu, Myoung-Seob Lim. 368-372 [doi]
• A novel charge sharing charge pump for energy harvesting applicationJiemin Zhou, Mengshu Huang, Yimeng Zhang, Hao Zhang, Tsutomu Yoshihara. 373-376 [doi]
• Minimizing MOSFET power losses in near-field electromagnetic energy-harnessing ICsOrlando Lazaro, Gabriel Alfonso Rincón-Mora. 377-380 [doi]
• An energy-optimal algorithm for temperature-aware idle time distribution considering mode transition overheadSangdo Park, Taewhan Kim. 381-384 [doi]
• Extracting the frequency response of switching DC-DC converters in CCM and DCM from time-domain simulationsSuhwan Kim, Gabriel A. Rincón-Mora, Dongwon Kwon. 385-388 [doi]
• A high efficiency piezoelectric energy harvesting systemXuan-Dien Do, Chang-Jin Jeong, Huy-Hieu Nguyen, Seok-Kyun Han, Sang-Gug Lee. 389-392 [doi]
• Ultra low-power high-speed flexible Probabilistic Adder for Error-Tolerant ApplicationsNing Zhu, Wang Ling Goh, Kiat Seng Yeo. 393-396 [doi]
• Enhancing circuits and systems supply noise sensitivity characterization using on-package droop inducersOmer Vikinski, Ram Ben-Ezra, Jimmy Huat Since Huang. 397-400 [doi]
• Design of low-power receiver front-end IC for low-frequency wireless time signal broadcast systemHo-Hsin Yeh, Ji-Chen Huang, Yu-Chen Kuo, Klaus Y. J. Hsu. 401-404 [doi]
• A 12-bit 100-MS/s pipelined ADC in 45-nm CMOSJae-Won Nam, Young-Deuk Jeon, Seok-Ju Yun, Tae Moon Roh, Jong-Kee Kwon. 405-407 [doi]
• An on-chip hot pixel identification and correction approach in CMOS imagersYuan Cao, Xiangyu Zhang. 408-411 [doi]
• Analysis of SRAM hierarchical bitlines for optimal performance and variation toleranceQi Li, Tony T. Kim. 412-415 [doi]
• Design of asynchronous 2-phase ternary encoding protocol using multiple-valued logicMyeong-Hoon Oh, Sung Nam Kim, Sungwoon Kim. 416-419 [doi]
• Noise reduction scheme of temporal and spatial filter for 3D video real-time processingHun Ho Ham, Jong-Hak Kim, Chan-Oh Park, Yong-Han Kim, Jun Dong Cho. 420-423 [doi]
• MTJ based non-volatile flip-flop in deep submicron technologyYoungdon Jung, Jisu Kim, Kyungho Ryu, Seong-Ook Jung, Jung Pill Kim, Seung-Hyuk Kang. 424-427 [doi]
• Design of TETRA Release 2 turbo decoder with low-complexity hardware interleaverJi-Hoon Kim. 428-431 [doi]
• Low-complexity filter and interpolator design for ATSC DTV systemsYong-Kyu Kim, Chang-Seok Choi, Hanho Lee, Jin-Gyun Chung. 432-435 [doi]
• Application specific processor for multi-standard video decodingJae-Jin Lee, Nak-Woong Eum. 436-439 [doi]
• Analysis of time dependent dielectric breakdown in nanoscale CMOS circuitsHo-Joon Lee, Kyung Ki Kim. 440-443 [doi]
• 77 GHz signal generator with CMOS technology for automotive radar applicationJoonhong Park, Hyuk Ryu, Donghyun Baek. 444-445 [doi]
• A design approach of a Parametric Measurement Unit on to a 600MHz DCLEdward Collins, In-Seok Jung, Yong-Bin Kim, Kyung Ki Kim. 446-449 [doi]
• Prototyping circuit design for Dielectric Electroactive Polymers energy harvestingPeiwen He, Wei Wang 0029, Ken Choi, Jonghyun Lee, Soohyun Kim. 450-453 [doi]
• Wide center-tape balun for 60 GHz silicon RF ICsFanyi Meng, Kiat Seng Yeo, Shanshan Xu, Kaixue Ma, Chee Chong Lim. 454-456 [doi]