Abstract is missing.
- Session details: Lifetime Achievement Award Tribute to Professor Alberto Sangiovanni-VicentelliPierluigi Nuzzo. [doi]
- Session details: New Advances in PlacementStephen Yang. [doi]
- Session details: Routing in All FormsPatrick Madden. [doi]
- Session details: Detailed Routing Contest ResultsDavid Chinnery. [doi]
- Session details: KeynoteNoel Menezes. [doi]
- Session details: KeynoteIsmail Bustany. [doi]
- Session details: Patterning and Machine LearningEvangeline Young. [doi]
- Session details: FPGA Special Session: Advances in Adaptable Heterogeneous Computing and Acceleration for Big DataMahesh Iyer. [doi]
- Session details: Cyber-Physical SystemsPatrick Groeneveld. [doi]
- Session details: Physical Design - Where are we going?C. K. Cheng. [doi]
- Fusion: The Dawn of the Hyperconvergence Era in EDAShankar Krishnamoorthy. 1 [doi]
- How Deep Learning Can Drive Physical Synthesis Towards More Predictable LegalizationRenan Netto, Sheiny Fabre, Tiago Augusto Fontana, Vinicius S. Livramento, Laércio Lima Pilla, José Luís Güntzel. 3-10 [doi]
- Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing BalancingYa-chu Chang, Tung-Wei Lin, Iris Hui-Ru Jiang, Gi-Joon Nam. 11-18 [doi]
- Device Layer-Aware Analytical Placement for Analog CircuitsBiying Xu, Shaolan Li, Chak-Wa Pui, Derong Liu 0002, Linxiao Shen, Yibo Lin, Nan Sun, David Z. Pan. 19-26 [doi]
- Analytical Mixed-Cell-Height Legalization Considering Average and Maximum Movement MinimizationXingquan Li, Jianli Chen, Wenxing Zhu, Yao-Wen Chang. 27-34 [doi]
- FPGA-based Computing in the Era of AI and Big DataEriko Nurvitadhi. 35 [doi]
- Advances in Adaptable ComputingAmit Gupta. 37-38 [doi]
- Improving Programmability and Efficiency of Large-Scale Graph Analytics for FPGA PlatformsMuhammet Mustafa Ozdal. 39 [doi]
- Pin Access-Driven Design Rule Clean and DFM Optimized Routing of Standard Cells under Boolean ConstraintsNikolay Ryzhenko, Steven Burns, Anton Sorokin, Mikhail Talalay. 41-47 [doi]
- PSION: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCsAlexandre Truppel, Tsun-Ming Tseng, Davide Bertozzi, José Carlos Alves, Ulf Schlichtmann. 49-56 [doi]
- Construction of All Multilayer Monolithic Rectilinear Steiner Minimum Trees on the 3D Hanan Grid for Monolithic 3D IC RoutingSheng-En David Lin, Dae-Hyun Kim. 57-64 [doi]
- ROAD: Routability Analysis and Diagnosis Framework Based on SAT TechniquesDongwon Park, Ilgweon Kang, Yeseong Kim, Sicun Gao, Bill Lin, Chung-Kuan Cheng. 65-72 [doi]
- A Perspective on Security and Trust Requirements for the FutureKenneth Plaks. 73 [doi]
- Declarative Language for Geometric Pattern Matching in VLSI Process Rule ModelingGyuszi Suto, Geoff S. Greenleaf, Phanindra Bhagavatula, Heinrich R. Fischer, Sanjay K. Soni, Brian H. Miller, Renato Fernandes Hentschke. 75-82 [doi]
- Electromigration-Aware Interconnect DesignSachin S. Sapatnekar. 83-90 [doi]
- Toward Intelligent Physical Design: Deep Learning and GPU AccelerationHaoxing Ren. 91-92 [doi]
- Multiple Patterning Layout Compliance with Minimizing Topology Disturbance and Polygon DisplacementHua-Yu Chang, Iris Hui-Ru Jiang. 93-100 [doi]
- From Electronic Design Automation to Automotive Design AutomationChung-Wei Lin. 101 [doi]
- Enterprise-wide AI-enabled Digital TransformationMehdi Maasoumy. 103 [doi]
- Secure and Trustworthy Cyber-Physical System Design: A Cross-Layer PerspectivePierluigi Nuzzo. 105 [doi]
- The Slow Start of Fast Spice: A Brief History of TimingJacob K. White. 107-108 [doi]
- Basic and Advanced Researches in Logic Synthesis and their Industrial ContributionsMasahiro Fujita. 109-116 [doi]
- From Electronic Design Automation to Cyber-Physical System Design Automation: A Tale of Platforms and ContractsPierluigi Nuzzo. 117-121 [doi]
- My 50-Year Journey from Punched Cards to Swarm SystemsAlberto Sangiovanni Vincentelli. 123-125 [doi]
- Freedom From Choice and the Power of Models: in Honor of Alberto Sangiovanni-VincentelliEdward A. Lee. 126 [doi]
- Analog Layout Synthesis: Are We There Yet?Prasanth Mangalagiri. 127 [doi]
- Lagrangian Relaxation Based Gate Sizing With Clock Skew Scheduling - A Fast and Effective ApproachAnkur Sharma, David Chinnery, Chris Chu. 129-137 [doi]
- Adaptive Clustering and Sampling for High-Dimensional and Multi-Failure-Region SRAM Yield AnalysisXiao Shi, Hao Yan, Jinxin Wang, Xiaofen Xu, Fengyuan Liu, Longxing Shi, Lei He. 139-146 [doi]
- ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing RulesWen-Hao Liu, Stefanus Mantik, Wing-Kai Chow, Yixiao Ding, Amin Farshidi, Gracieli Posser. 147-151 [doi]