Abstract is missing.
- Steering/Advisory Committee [doi]
- Welcome Notes [doi]
- Conference at a Glance [doi]
- Organizing Committee [doi]
- Technical Subcommittees [doi]
- Tutorial 1: Emerging Technologies for VLSI DesignRajiv V. Joshi, Kaustav Banerjee, André DeHon. 4 [doi]
- Tutorial II: Variability and Its Impact on DesignKeith A. Bowman, Michael Orshansky, Sachin S. Sapatnekar. 5 [doi]
- Session EP1: Power Management and Optimization Challenges for Sub 90nm CMOS Designs- What is the Real Cost of Long Battery Life?Michael Santarini, Pallab K. Chatterjee. 7 [doi]
- Modular service-oriented platform architecture - a key enabler to SoC design qualityRisto Suoranta. 11-13 [doi]
- Deep sub-100 nm Design ChallengesT. Furuyama. 13-14 [doi]
- Successful IP Business ModelsDi Ma. 15-18 [doi]
- Variational Interconnect Delay Metrics for Statistical Timing AnalysisPraveen Ghanta, Sarma B. K. Vrudhula. 19-24 [doi]
- Statistically Aware SRAM Memory Array DesignEvelyn Grossar, Michele Stucchi, Karen Maex, Wim Dehaene. 25-30 [doi]
- Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold VoltagesZhiyu Liu, Volkan Kursun. 31-36 [doi]
- Constructing Current-Based Gate Models Based on Existing Timing LibraryAndrew B. Kahng, Bao Liu, Xu Xu. 37-42 [doi]
- Efficient Model Update for General Link-Insertion NetworksZhuo Feng, Peng Li, Jiang Hu. 43-50 [doi]
- Using Abstraction for Efficient Formal Verification of Pipelined Processors with Value PredictionMiroslav N. Velev. 51-56 [doi]
- EFSM Manipulation to Increase High-Level ATPG EffectivenessGiuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli. 57-62 [doi]
- A Technique for Estimating the Difficulty of a Formal Verification ProblemIndradeep Ghosh, Mukul R. Prasad. 63-70 [doi]
- A Formal Verification Method of Scheduling in High-level SynthesisChandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade. 71-78 [doi]
- Fast Incremental Link Insertion in Clock Networks for Skew Variability ReductionAnand Rajaram, David Z. Pan. 79-84 [doi]
- Clock Distribution Architectures: A Comparative StudyChao-Yang Yeh, Gustavo R. Wilke, Hongyu Chen, Subodh M. Reddy, Hoa-van Nguyen, Takashi Miyoshi, William W. Walker, Rajeev Murgai. 85-91 [doi]
- Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise OptimizationNarender Hanchate, Nagarajan Ranganathan. 92-97 [doi]
- Interconnect and Thermal-aware Floorplanning for 3D MicroprocessorsWei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin. 98-104 [doi]
- Simplicity and Executability: Cornerstones of QualityMichael Keating. 105 [doi]
- A Compact DC and AC Model for Circuit Simulation of High Voltage VDMOS TransistorYogesh Singh Chauhan, C. Anghel, Francois Krummenacher, Renaud Gillon, A. Baguenier. 109-114 [doi]
- A Complete Carrier-Based Non-Charge-Sheet Analytic Theory for Nano-Scale Undoped Surrounding-Gate MOSFETsJin He, Xing Zhang, Ganggang Zhang, Mansun Chan, Yangyuan Wang. 115-120 [doi]
- METS: A Metric for Electro-Thermal Sensitivity, and Its Application To FinFETsBrian Swahn, Soha Hassoun. 121-126 [doi]
- A Carrier-Based Analytic Model for Undoped (Lightly Doped) Ultra-Thin-Body Silicon-on-Insulator (UTB-SOI) MOSFETsJin He, Xing Zhang, Ganggang Zhang, Yangyuan Wang. 127-132 [doi]
- Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO)Chong Zhao, Sujit Dey. 133-140 [doi]
- Probabilistic Delay Budgeting for Soft Realtime ApplicationsSoheil Ghiasi, Po-Kuan Huang. 141-146 [doi]
- TBNM - Transistor-Level Boundary Model for Fast Gate-Level Noise Analysis of Macro BlocksJindrich Zejda, Li Ding 0002. 147-152 [doi]
- Fast Sequential Cell Noise Immunity Characterization Using Meta-stable Point of Feedback LoopNahmsuk Oh, Li Ding 0002, Alireza Kasnavi. 153-159 [doi]
- Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold TimesEmre Salman, Eby G. Friedman, Ali Dasdan, Feroze Taraporevala, Kayhan Küçükçakar. 159-164 [doi]
- Power Islands: A High-Level Technique for Counteracting Leakage in Deep Sub-MicronDeniz Dal, Adrian Nunez, Nazanin Mansouri. 165-170 [doi]
- Simultaneous Statistical Delay and Slew Optimization for Interconnect PipelinesAndrew Havlir, David Z. Pan. 171-178 [doi]
- System-Level SRAM Yield EnhancementFadi J. Kurdahi, Ahmed M. Eltawil, Young-Hwan Park, Rouwaida Kanj, Sani R. Nassif. 179-184 [doi]
- Sensing Margin Analysis of MLC Flash Memories Using a Novel Unified Statistical ModelYoung-Gu Kim, Sang-Hoon Lee, Dae-Han Kim, Jae-Woo Im, Sung-Eun Yu, Dae-Wook Kim, Young-Kwan Park, Jeong-Taek Kong. 185-189 [doi]
- The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and StabilityR. Venkatraman, R. Castagnetti, S. Ramesh. 190-195 [doi]
- A Simulation-Based Soft Error Estimation Methodology for Computer SystemsMakoto Sugihara, Tohru Ishihara, Masanori Muroyama, Koji Hashimoto. 196-203 [doi]
- SRAM Local Bit Line Access Failure AnalysesPraveen Elakkumanan, Jente B. Kuang, Kevin J. Nowka, Ramalingam Sridhar, Rouwaida Kanj, Sani R. Nassif. 204-209 [doi]
- Impact of NBTI on SRAM Read Stability and Design for ReliabilitySanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar. 210-218 [doi]
- Minimizing FPGA Reconfiguration Data at Logic LevelKrishna Prasad Raghuraman, Haibo Wang, Spyros Tragoudas. 219-224 [doi]
- Structure Synthesis of Analog and Mixed-Signal Circuits using Partition TechniquesKaiping Zeng, Sorin A. Huss. 225-230 [doi]
- Language-Based High Level Transaction Extraction on On-chip BusesYi-Le Huang, Chun-Yao Wang, Richard Yeh, Shih-Chieh Chang, Yung-Chih Chen. 231-236 [doi]
- Clock Skew Scheduling Under Process VariationsXinjie Wei, Yici Cai, Xianlong Hong. 237-242 [doi]
- A CMOS Thermal Sensor and Its Applications in Temperature Adaptive DesignQikai Chen, Mesut Meterelliyoz, Kaushik Roy. 243-248 [doi]
- Monte Carlo-Alternative Probabilistic Simulations for Analog SystemsRasit Onur Topaloglu. 249-253 [doi]
- Critical Path Analysis Considering Temperature, Power Supply Variations and Temperature Induced LeakagePeng Li. 254-259 [doi]
- Process Window and Device Variations Evaluation using Array-Based Characterization CircuitsC. Tabery, M. Craig, G. Burbach, B. Wagner, S. McGowan, P. Etter, S. Roling, C. Haidinyak, E. Ehrichs. 260-265 [doi]
- Novel Decoupling Capacitor Designs for sub- 90nm CMOS TechnologyXiongfei Meng, Resve A. Saleh, Karim Arabi. 266-271 [doi]
- Localized On-Chip Power Delivery Network Optimization via Sequence of Linear ProgrammingJeffrey Fan, I-Fan Liao, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong. 272-277 [doi]
- Non-Physical Pseudo-Wave-Based Modal Decoupling Technique of Multi- Coupled Co-Planar Transmission Lines with Homogeneous Dielectric MediaSeongkyun Shin, Yungseon Eo. 278-283 [doi]
- Enhancement of Signal Integrity and Power Integrity with Embedded Capacitors in High-Speed PackagesKrishna Srinivasan, P. Muthana, Rohan Mandrekar, Ege Engin, J. Choi, Madhavan Swaminathan. 284-291 [doi]
- An Improved AMG-based Method for Fast Power Grid AnalysisCheng Zhuo, Jiang Hu, Kangsheng Chen. 290-295 [doi]
- Formal Verification of Pipelined Microprocessors with Delayed BranchesMiroslav N. Velev. 296-299 [doi]
- Power-Aware Test Pattern Generation for Improved Concurrency at the Core LevelArkan Abdulrahman, Spyros Tragoudas. 300-305 [doi]
- Advances in Computation of the Maximum of a Set of Random VariablesDebjit Sinha, Hai Zhou, Narendra V. Shenoy. 306-311 [doi]
- A Low-Leakage High-Speed Monotonic Static CMOS 64b Adder in a Dual Gate Oxide 65-nm CMOS TechnologyAli Bastani, Charles A. Zukowski. 312-317 [doi]
- Leakage Biased Sleep Switch Domino LogicZhiyu Liu, Volkan Kursun. 318-323 [doi]
- Improvements to CBCM (Charge-Based Capacitance Measurement) for Deep Submicron CMOS TechnologyRandy Bach, Bob Davis, Rich Laubhan. 324-329 [doi]
- Design of a Single Event Upset (SEU) Mitigation Technique for Programmable DevicesSajid Baloch, Tughrul Arslan, Adrian Stoica. 330-345 [doi]
- Area Efficient Temporal Coding Schemes for Reducing Crosstalk EffectsJean-Marc Philippe, Sébastien Pillement, Olivier Sentieys. 334-339 [doi]
- Processing Rate Optimization by Sequential System FloorplanningJia Wang, Hai Zhou, Ping-Chih Wu. 340-345 [doi]
- Fast Boolean Matching with Don t CaresZile Wei, Donald Chai, A. Richard Newton, Andreas Kuehlmann. 346-351 [doi]
- A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip ArchitecturesKrishnan Srinivasan, Karam S. Chatha. 352-357 [doi]
- Core Network Interface Architecture and Latency Constrained On-Chip CommunicationPraveen Bhojwani, Rabi N. Mahapatra. 358-363 [doi]
- Design Space Exploration of RTL Datapaths Using Rent Parameter based Stochastic Wirelength EstimationVyas Krishnan, Srinivas Katkoori. 364-369 [doi]
- Equivalence Checking of C Programs by Locally Performing Symbolic Simulation on Dependence GraphsTakeshi Matsumoto, Hiroshi Saito, Masahiro Fujita. 370-375 [doi]
- System-level process variability compensation on memory organizations of dynamic applications: a case studyConcepción Sanz, Manuel Prieto, Antonis Papanikolaou, Miguel Miranda, Francky Catthoor. 376-382 [doi]
- A low input, low-power dissipation CMOS ADCBiye Wang, Lili He, Morris Jones. 383-386 [doi]
- Constant Impedance Scaling Paradigm for Scaling LC transmission linesJ. Balachandran, Steven Brebels, G. Carchon, Walter De Raedt, Eric Beyne, M. Kuijk, Bart Nauwelaers. 387-392 [doi]
- Quasi-One-Step Gauss-Jacobi Method for Large-Scale Interconnect Analysis via RLCG-MNA FormulationYuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai. 393-400 [doi]
- Analysis of Pulse Signaling for Low-Power On-Chip Global Bus DesignMin Chen, Yu Cao. 401-406 [doi]
- Information Theoretic Capacity of Long On-chip Interconnects in the Presence of CrosstalkRohit Singhal, Gwan S. Choi, Rabi N. Mahapatra. 407-412 [doi]
- Compact Reduced Order Modeling for Multiple-Port InterconnectsPu Liu, Sheldon X.-D. Tan, Bruce McGaughy, Lifeng Wu. 413-418 [doi]
- Efficient Signal Integrity Verification Method of Multi-Coupled RLC Interconnect Lines with Asynchronous Circuit SwitchingTaeyong Je, Yungseon Eo. 419-424 [doi]
- Reducing the Data Switching Activity on Serial Link BusesMaged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De. 425-432 [doi]
- Efficient Multiphase Test Set Embedding for Scan-based TestingEmmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos. 433-438 [doi]
- Evaluation of Collapsing Methods for Fault DiagnosisRajsekhar Adapa, Spyros Tragoudas, Maria K. Michael. 439-444 [doi]
- On N-Detect Pattern Set OptimizationYu Huang. 445-450 [doi]
- On Optimizing Scan Testing Power and Routing Cost in Scan Chain DesignLi-Chung Hsu, Hung-Ming Chen. 451-456 [doi]
- An Improved Method for Identifying Linear Dependencies in Path Delay FaultsEdward Flanigan, Themistoklis Haniotakis, Spyros Tragoudas. 457-462 [doi]
- Delay Fault Diagnosis for Non-Robust TestVishal J. Mehta, Malgorzata Marek-Sadowska, Zhiyuan Wang, Kun-Han Tsai, Janusz Rajski. 463-472 [doi]
- Yield Improvement by Local Wiring RedundancyJeanne Bickford, Jason Hibbeler, Markus Bühler, Jürgen Koehl, Dirk Muller, Sven Peyer, Christian Schulte 0002. 473-478 [doi]
- Via Distribution Model for Yield EstimationTakumi Uezono, Kenichi Okada, Kazuya Masu. 479-484 [doi]
- The Use of the Manufacturing Sensitivity Model Forms to Comprehend Layout Manufacturing Robustness For Use During Device DesignLawrence S. Melvin III, Daniel N. Zhang, Kirk J. Strozewski, Skye Wolfer. 485-490 [doi]
- DFM Metrics for Standard CellsRobert C. Aitken. 491-496 [doi]
- Yield Enhancement Methodology for CMOS Standard CellsArnaud Epinat, N. Vijayaraghavan, Matthieu Sautier, Olivier Callen, Sebastien Fabre, Ryan Ross, Paul Simon, Robin Wilson. 497-502 [doi]
- Dummy-Gate Structure to Improve ESD Robustness in a Fully-Salicided 130-nm CMOS Technology without Using Extra Salicide-Blocking MaskHsin-Chyh Hsu, Ming-Dou Ker. 503-506 [doi]
- Who is really responsible for quality throughout the design process?Ron Wilson, David Overhauser. 507 [doi]
- Adding Manufacturability to the Quality of ResultsRaul Camposano. 511 [doi]
- Future Memory Technology Trends and ChallengesChanghyun Kim. 513 [doi]
- Device and Technology Challenges for Nanoscale CMOSH.-S. Philip Wong. 515-518 [doi]
- A Totally Self-Checking S-box Architecture for the Advanced Encryption StandardAdam Matthews. 519-524 [doi]
- Jitter Decomposition by Time Lag CorrelationQingqi Dou, Jacob A. Abraham. 525-530 [doi]
- Design ofWindow Comparators for Integrator-Based Capacitor Array Testing CircuitsAmit Laknaur, Haibo Wang. 531-536 [doi]
- Analysis and experimental results of an FPGA-based strategy for fast production test of high resolution ADCsDaniela De Venuto, Leonardo Reyneri. 537-542 [doi]
- Exploring the Ability of Oscillation Based Test for Testing Continuous -Time Ladder FiltersJosé Luis Catalano, Gabriela Peretti, Eduardo Romero, Carlos A. Marqués. 543-550 [doi]
- Data Replication in Banked DRAMs for Reducing Energy ConsumptionOzcan Ozturk, Mahmut T. Kandemir. 551-556 [doi]
- Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage CalibrationMinh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson. 557-563 [doi]
- Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative PerspectiveSaraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos. 564-569 [doi]
- Compiler-Directed Power Density Reduction in NoC-Based Multi-Core DesignsSri Hari Krishna Narayanan, Mahmut T. Kandemir, Ozcan Ozturk. 570-575 [doi]
- Shared Scratch-Pad Memory Space ManagementOzcan Ozturk, Mahmut T. Kandemir, Ibrahim Kolcu. 576-584 [doi]
- New Generation of Predictive Technology Model for Sub-45nm Design ExplorationWei Zhao, Yu Cao. 585-590 [doi]
- A Non-Volatile Embedded Memory for High Temperature Automotive and High-Retention ApplicationsM. Thomas, J. Pathak, J. Payne, F. Leisenberger, E. Wachmann, G. Schatzberger, A. Wiesner, M. Schrems. 591-596 [doi]
- Method to Evaluate Cable Discharge Event (CDE) Reliability of Integrated Circuits in CMOS TechnologyTai-Xiang Lai, Ming-Dou Ker. 597-602 [doi]
- Analysis of Process Variation s Effect on SRAM s Read StabilityChung-Kuan Tsai, Malgorzata Marek-Sadowska. 603-610 [doi]
- Logic SER Reduction through Flipflop RedesignVivek Joshi, Rajeev R. Rao, David Blaauw, Dennis Sylvester. 611-616 [doi]
- Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational LogicPraveen Elakkumanan, Kishan Prasad, Ramalingam Sridhar. 617-624 [doi]
- Thermal Trends in Emerging TechnologiesGreg M. Link, Narayanan Vijaykrishnan. 625-632 [doi]
- Power Gating with Multiple Sleep ModesKanak Agarwal, Kevin J. Nowka, Harmander Deogun, Dennis Sylvester. 633-637 [doi]
- SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment MatchingAndrew B. Kahng, Bao Liu, Sheldon X.-D. Tan. 638-643 [doi]
- Accurate Thermal Analysis Considering Nonlinear Thermal ConductivityAnand Ramalingam, David Z. Pan, Frank Liu, Sani R. Nassif. 644-649 [doi]
- Minimizing Ohmic Loss in Future Processor IR EventsMark M. Budnik, Kaushik Roy. 650-658 [doi]
- mTest: An Industry-Wide Database of VLSI Layouts for Quality ControlAnand P. Kulkarni, Thomas J. Grebinski. 659-664 [doi]
- ConvexSmooth: A simultaneous convex fitting and smoothing algorithm for convex optimization problemsSanghamitra Roy, Charlie Chung-Ping Chen. 665-670 [doi]
- A Watermarking System for IP Protection by Buffer Insertion TechniqueGuangyu Sun, Zhiqiang Gao, Yi Xu. 671-675 [doi]
- Partial Selective Encryption: An Improved System for Protecting VLSI Design Data in the OASIS formatAnand P. Kulkarni, Thomas J. Grebinski. 676-681 [doi]
- Transistor-Level Optimization of SupergatesDimitri Kagaris, Themistoklis Haniotakis. 682-690 [doi]
- Study of Floating Fill Impact on Interconnect CapacitanceAndrew B. Kahng, Kambiz Samadi, Puneet Sharma. 691-696 [doi]
- The Challenges and Impact of Parasitic Extraction at 65 nmKaren Chow. 697-702 [doi]
- Pre-Layout Inductive Corners for Advanced Digital Design Interconnect: Modeling and Silicon ValidationLaureline David, Stephane Martin, Corinne Cregut, Eric Balossier, Frederic Nyer, Fabrice Huret. 703-708 [doi]
- A Mixed Boundary Element Method for Extracting Frequency- Inductances of 3D InterconnectsChanghao Yan, Wenjian Yu, Zeyi Wang. 709-716 [doi]
- LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designsSarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula. 717-722 [doi]
- Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage OptimizationYu Wang, Hai Lin, Huazhong Yang, Rong Luo, Hui Wang. 723-728 [doi]
- Low-leakage SRAM Design with Dual V_t TransistorsBehnam Amelifard, Massoud Pedram, Farzan Fallah. 729-734 [doi]
- Dual-Vt Design of FPGAs for Subthreshold Leakage ToleranceAkhilesh Kumar, Mohab Anis. 735-740 [doi]
- Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances in MTCMOS DesignsChanseok Hwang, Chang Woo Kang, Massoud Pedram. 741-746 [doi]
- Impact of Gate-Length Biasing on Threshold-Voltage SelectionAndrew B. Kahng, Swamy Muddu, Puneet Sharma. 747-754 [doi]
- FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based DesignsBin Zhang, Wei-Shen Wang, Michael Orshansky. 755-760 [doi]
- Diagnosis and Design for Diagnosability for Internet RoutersLee Barford. 761-768 [doi]
- Enabling Quality and Schedule Predictability in SoC Design using HandoffQCBhaskar J. Karmakar, V. Kalyana Chakravarty, R. Venkatraman, Jagdish C. Rao. 769-774 [doi]
- Transaction Level Error Susceptibility Model for Bus Based SoC ArchitecturesIng-Chao Lin, Suresh Srinivasan, Narayanan Vijaykrishnan, Nagu R. Dhanwada. 775-780 [doi]
- System-Level Design Methodology with Direct Execution For Multiprocessors on SoPCRiad Ben Mouhoub, Omar Hammami. 781-788 [doi]
- Question: DRC or DfM ? Answer: FMEA and ROIArtur Balasinski. 789-794 [doi]
- Statistical Analysis of Capacitance Coupling Effects on Delay and NoiseUsha Narasimha, Binu Abraham, N. S. Nagaraj. 795-800 [doi]
- Bringing Manufacturing into Design via Process-Dependent SPICE ModelsS. Tirumala, Y. Mahotin, Xiao Lin, Victor Moroz, L. Smith, S. Krishnamurthy, L. Bomholt, Dipu Pramanik. 801-806 [doi]
- Stress-Aware Design MethodologyVictor Moroz, Lee Smith, Xi-Wei Lin, Dipu Pramanik, Greg Rollins. 807-812 [doi]
- A DFM Methodology to Evaluate the Impact of Lithography Conditions on the Speed of Critical Paths in a VLSI CircuitPeter Wright, Minghui Fan. 813-817 [doi]