Abstract is missing.
- Small embeddable NBTI sensors (SENS) for tracking on-chip performance decayAdam C. Cabe, Zhenyu Qi, Stuart N. Wooters, Travis N. Blalock, Mircea R. Stan. 1-6 [doi]
- A unified FinFET reliability model including high K gate stack dynamic threshold voltage, hot carrier injection, and negative bias temperature instabilityChenyue Ma, Bo Li, Lining Zhang, Jin He, Xing Zhang, Xinnan Lin, Mansun Chan. 7-12 [doi]
- NBTI-aware statistical circuit delay assessmentBalaji Vaidyanathan, Anthony S. Oates, Yuan Xie, Yu Wang. 13-18 [doi]
- On the efficacy of input Vector Control to mitigate NBTI effects and leakage powerYu Wang, Xiaoming Chen, Wenping Wang, Varsha Balakrishnan, Yu Cao, Yuan Xie, Huazhong Yang. 19-26 [doi]
- Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC designR. Venkatraman, R. Castagnetti, Andres Teene, Benjamin Mbouombouo, S. Ramesh. 27-32 [doi]
- On-chip dynamic worst-case crosstalk pattern detection and elimination for bus-based macro-cell designsHariharan Sankaran, Srinivas Katkoori. 33-39 [doi]
- Worst case timing jitter and amplitude noise in differential signalingWei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti, Yu Hu. 40-46 [doi]
- A PVT aware accurate statistical logic library for high- metal-gate nano-CMOSDhruva Ghai, Saraju P. Mohanty, Elias Kougianos, Priyadarsan Patra. 47-54 [doi]
- A general piece-wise nonlinear library modeling format and size reduction technique for gate-level timing, SI, power, and variation analysisXin Wang, Alireza Kasnavi, Harold Levy. 55-61 [doi]
- Leakage optimization using transistor-level dual threshold voltage cell libraryChandra S. Nagarajan, Lin Yuan, Gang Qu, Barbara G. Stamps. 62-67 [doi]
- Accurate closed-form parameterized block-based statistical timing analysis applying skew-normal distributionChun-Yu Chuang, Wai-Kei Mak. 68-73 [doi]
- Characterization of sequential cells for constraint sensitivitiesSavithri Sundareswaran, Rajendran Panda, Jacob A. Abraham, Yun Zhang, Amit Mittal. 74-79 [doi]
- PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devicesCharles Augustine, Arijit Raychowdhury, Yunfei Gao, Mark S. Lundstrom, Kaushik Roy. 80-85 [doi]
- Architecture design exploration of three-dimensional (3D) integrated DRAMRakesh Anigundi, Hongbin Sun, Jian-Qiang Lu, Kenneth Rose, Tong Zhang. 86-90 [doi]
- Accurate buffer modeling with slew propagation in subthreshold circuitsJeremy R. Tolbert, Saibal Mukhopadhyay. 91-96 [doi]
- Robust differential asynchronous nanoelectronic circuitsBao Liu. 97-102 [doi]
- An enhanced topology for reliability of a high performance 3.3V I/O buffer in a single-well bulk CMOS 1.8v-oxide low voltage processKarthik Rajagopal, Aatmesh, Vinod Menezes. 103-106 [doi]
- The design of a low-power high-speed current comparator in 0.35-m CMOS technologySoheil Ziabakhsh, Hosein Alavi-Rad, Mohammad Alavi-Rad, Mohammad Mortazavi. 107-111 [doi]
- Comparison of supply noise and substrate noise reduction in SiGe BiCMOS and FDSOI processesWai Leng Cheong, Brian Owens, Hui En Pham, Christopher Hanken, Jim Le, Terri S. Fiez, Kartikeya Mayaram. 112-115 [doi]
- An effective staggered-phase damping technique for suppressing power-gating resonance noise during mode transitionCharbel J. Akl, Rafic A. Ayoubi, Magdy A. Bayoumi. 116-119 [doi]
- Design and application of multimodal power gating structuresEhsan Pakbaznia, Massoud Pedram. 120-126 [doi]
- Revisiting the linear programming framework for leakage power vs. performance optimizationKwangok Jeong, Andrew B. Kahng, Hailong Yao. 127-134 [doi]
- Parameter tuning in SVM-based power macro-modelingAntónio Gusmão, L. Miguel Silveira, José C. Monteiro. 135-140 [doi]
- Performance-energy tradeoffs in reliable NoCsYing-Cherng Lan, Michael C. Chen, Wei-De. Chen, Sao-Jie Chen, Yu Hen Hu. 141-146 [doi]
- 3D-GCP: An analytical model for the impact of process variations on the critical path delay distribution of 3D ICsSiddharth Garg, Diana Marculescu. 147-155 [doi]
- Control of design specific variation in etch-assisted via pattern transfer by means of full-chip simulationValeriy Sukharev, Ara Markosian, Armen Kteyan, Levon Manukyan, Nikolay Khachatryan, Jun-Ho Choy, Hasmik Lazaryan, Henrik Hovsepyan, Seiji Onoue, Takuo Kikuchi, Tetsuya Kamigaki. 156-161 [doi]
- New subthreshold concepts in 65nm CMOS technologyFarshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Ali Peiravi, Snorre Aunet, Tuan Vu Cao. 162-166 [doi]
- On-chip transistor characterization arrays with digital interfaces for variability characterizationSimeon Realov, William McLaughlin, Kenneth L. Shepard. 167-171 [doi]
- Variability-aware optimization of nano-CMOS Active Pixel Sensors using design and analysis of Monte Carlo experimentsDhruva Ghai, Saraju P. Mohanty, Elias Kougianos. 172-178 [doi]
- Yield evaluation of analog placement with arbitrary capacitor ratioJwu-E Chen, Pei-Wen Luo, Chin-Long Wey. 179-184 [doi]
- Analysis of performance and reliability trade-off in dummy pattern design for 32-nm technologyAditya P. Karmarkar, Xiaopeng Xu, Victor Moroz, Greg Rollins, Xiao Lin. 185-189 [doi]
- Statistical yield analysis of silicon-on-insulator embedded DRAMRouwaida Kanj, Rajiv V. Joshi, Jente B. Kuang, J. Kim, Mesut Meterelliyoz, W. Reohr, Sani R. Nassif, Kevin J. Nowka. 190-194 [doi]
- Erect of regularity-enhanced layout on printability and circuit performance of standard cellsHiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera. 195-200 [doi]
- Trading off higher execution latency for increased reliability in tile-based massive multi-core architecturesEnric Musoll. 201-207 [doi]
- A Simulation-based strategy used in electrical design for reliabilityYan Liu, Scott Hareland, Donald Hall, Bill Wold, Roger Hubing, Robert Mehregan, Ronen Malka, Manish Sharma, Tom Lane. 208-212 [doi]
- Estimation and optimization of reliability of noisy digital circuitsSatish Sivaswamy, Kia Bazargan, Marc D. Riedel. 213-219 [doi]
- Combinational logic SER estimation with the presence of re-convergenceBiwei Liu, Shuming Chen, Yi Xu. 220-225 [doi]
- Effect of NDD dosage on hot-carrier reliability in DMOS transistorsJone F. Chen, Kuen-Shiuan Tian, Shiang-Yu Chen, Kuo-Ming Wu, C. M. Liu. 226-229 [doi]
- Side channel aware leakage management in nanoscale Cryptosystem-on-Chip (CoC)Amir Khatib Zadeh, Catherine H. Gebotys. 230-235 [doi]
- An effective approach to detect logic soft errors in digital circuits based on GRAALHai Yu, Michael Nicolaidis, Lorena Anghel. 236-240 [doi]
- An efficient approach to sip design integrationMeng-Syue Chan, Chun-Yao Wang, Yung-Chih Chen. 241-247 [doi]
- A new low power test pattern generator using a variable-length ring counterBin Zhou, Yizheng Ye, Zhao-lin Li, Xin-chun Wu, Rui Ke. 248-252 [doi]
- A case study on logic diagnosis for System-on-ChipYoussef Benabboud, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute. 253-259 [doi]
- Proactive management of X s in scan chains for compressionAnshuman Chandra, Yasunari Kanzawa, Rohit Kapur. 260-265 [doi]
- A Built-in self-calibration scheme for pipelined ADCsHsiu-Ming Chang, Kuan-Yu Lin, Chin-Hsuan Chen, Kwang-Ting Cheng. 266-271 [doi]
- A geometric approach to register transfer level satisfiabilityHéctor Navarro, Saeid Nooshabadi, Juan A. Montiel-Nelson, Victor Navarro-Botello, J. Sosa, José C. García. 272-275 [doi]
- Efficient diagnosis algorithms for drowsy SRAMsBing-Wei Huang, Jin-Fu Li. 276-279 [doi]
- Incremental power optimization for multiple supply voltage designYuchun Ma, Xiang Qiu, Xiangqing He, Xianlong Hong. 280-286 [doi]
- IP protection platform based on watermarking techniqueYun Du, Yangshuo Ding, Yujie Chen, Zhiqiang Gao. 287-290 [doi]
- Statistical static performance analysis of asynchronous circuits considering process variationMohsen Raji, Behnam Ghavami, Hossein Pedram. 291-296 [doi]
- A software pipelining algorithm in high-level synthesis for FPGA architecturesLei Gao, David Zaretsky, Gaurav Mittal, Dan Schonfeld, Prith Banerjee. 297-302 [doi]
- Phenomenological model for gate length bias dependent inverter delay change with emphasis on library characterizationQian Ying Tang, Qiang Chen, Niloy Chatterjee, Vedank Tripathi, Natarajan Nandagopalan, Sridhar Tirumala. 303-308 [doi]
- Statistical decoupling capacitance allocation by efficient numerical quadrature methodThom Jefferson A. Eguia, Ning Mi, Sheldon X.-D. Tan. 309-316 [doi]
- A novel ACO-based pattern generation for peak power estimation in VLSI circuitsYi-Ling Liu, Chun-Yao Wang, Yung-Chih Chen, Ya-Hsin Chang. 317-323 [doi]
- Switch level optimization of digital CMOS gate networksLeomar S. da Rosa Jr., Felipe Ribeiro Schneider, Renato P. Ribas, André Inácio Reis. 324-329 [doi]
- hArtes design flow for heterogeneous platformsMuhammad Rashid, Fabrizio Ferrandi, Koen Bertels. 330-338 [doi]
- An efficient reliability evaluation approach for system-level design of embedded systemsAdeel Israr, Abdulhadi Shoufan, Sorin A. Huss. 339-344 [doi]
- A case study on system-level modeling by aspect-oriented programmingFeng Liu, Otmane Aït Mohamed, Xiaoyu Song, Qingping Tan. 345-349 [doi]
- Performance evaluation of wireless networks on chip architecturesAmlan Ganguly, Kevin Chang, Partha Pratim Pande, Benjamin Belzer, Alireza Nojeh. 350-355 [doi]
- Validating physical access layer of WiMAX using SystemVerilogAlbert Chiang, Wei-Hua Han, Bhanu Kapoor. 356-359 [doi]
- Accelerating jitter tolerance qualification for high speed serial interfacesYongquan Fan, Zeljko Zilic. 360-365 [doi]
- Improving the accuracy of rule-based equivalence checking of system-level design descriptions by identifying potential internal equivalencesHiroaki Yoshida, Masahiro Fujita. 366-370 [doi]
- Efficient SAT-based techniques for Design of Experiments by using static variable orderingMiroslav N. Velev, Ping Gao 0002. 371-376 [doi]
- An abstraction mechanism to maximize stimulus portability across RTL, FPGA, software models and silicon of SoCsMrinal Bose, Prashant Naphade, Jayanta Bhadra, Hillel Miller. 377-381 [doi]
- Timing yield estimation of digital circuits using a control variate techniqueJavid Jaffari, Mohab Anis. 382-387 [doi]
- A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variationsKoustav Bhattacharya, Nagarajan Ranganathan. 388-393 [doi]
- TuneLogic: Post-silicon tuning of dual-Vdd designsStephen Bijansky, Sae Kyu Lee, Adnan Aziz. 394-400 [doi]
- A case for exploiting complex arithmetic circuits towards performance yield enhancementShingo Watanabe, Masanori Hashimoto, Toshinori Sato. 401-407 [doi]
- A systematic approach to modeling and analysis of transient faults in logic circuitsNatasa Miskov-Zivanov, Diana Marculescu. 408-413 [doi]
- ESD event simulation automation using automatic extraction of the relevant portion of a full chipThorsten Weyl, Dave Clarke, Karl Rinne, James A. Power. 414-418 [doi]
- Parametric analysis to determine accurate interconnect extraction corners for design performanceAyhan A. Mutlu, Jiayong Le, Ruben Molina, Mustafa Celik. 419-423 [doi]
- Exploratory study on circuit and architecture design of very high density diode-switch phase change memoriesShu Li, Tong Zhang. 424-429 [doi]
- Adaptive voltage controlled nanoelectronic addressing for yield, accuracy and resolutionBao Liu. 430-435 [doi]
- Defect characterization in magnetic field coupled arraysAnita Kumari, Javier F. Pulecio, Sanjukta Bhanja. 436-441 [doi]
- CAD utilities to comprehend layout-dependent stress effects in 45 nm high- performance SOI custom macro designAkif Sultan, John Faricelli, Sushant Suryagandh, Hans vanMeer, Kaveri Mathur, James Pattison, Sean Hannon, Greg Constant, Kalyana Kumar, Kevin Carrejo, Joe Meier, Rasit Onur Topaloglu, Darin Chan, Uwe Hahn, Thorsten Knopp, Victor Andrade, Bill Gardiol, Steve Hejl, David Wu, James Buller, Larry Bair, Ali Icel, Yuri Apanovich. 442-446 [doi]
- A 1.2 volt, 90nm, 16-bit three way segmented digital to analog converter (DAC) for low power applicationsMaruthi Chandrasekhar Bh, Sudeb Dasgupta. 447-450 [doi]
- Design methodology of high performance on-chip global interconnect using terminated transmission-lineYulei Zhang, Ling Zhang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng. 451-458 [doi]
- New word-line driving scheme for suppressing oxide-tunneling leakage in sub-65-nm SRAMsJi-Hye Bong, Yong Jin Kwon, Kyeong-Sik Min, Sung-Mo Kang. 459-464 [doi]
- Adaptive leakage control on body biasing for reducing power consumption in CMOS VLSI circuitXin He, Syed Al-Kadry, Afshin Abdollahi. 465-470 [doi]
- Standby power reduction and SRAM cell optimization for 65nm technologyS. Lakshminarayanan, J. Joung, G. Narasimhan, R. Kapre, M. Slanina, J. Tung, M. Whately, C.-L. Hou, W.-J. Liao, S.-C. Lin, P.-G. Ma, C.-W. Fan, M. C. Hsieh, F.-C. Liu, K.-L. Yeh, W.-C. Tseng, S. W. Lu. 471-475 [doi]
- Optimization strategies to improve statistical timingParimala Viswanath, Pranav Murthy, Debajit Das, R. Venkatraman, Ajoy Mandal, Arvind Veeravalli, H. Udayakumar. 476-481 [doi]
- Clock gating effectiveness metrics: Applications to power optimizationJithendra Srinivas, Madhusudan Rao, Sukumar Jairam, H. Udayakumar, Jagdish C. Rao. 482-487 [doi]
- Buffer/flip-flop block planning for power-integrity-driven floorplanningHsin-Hua Pan, Hung-Ming Chen, Chia-Yi Chang. 488-493 [doi]
- On temperature planarization effect of copper dummy fills in deep nanometer technologyBasab Datta, Wayne Burleson. 494-499 [doi]
- Fast characterization of parameterized cell libraryUday Doddannagari, Shiyan Hu, Weiping Shi. 500-505 [doi]
- Cell shifting aware of wirelength and overlapLiu Dawei, Qiang Zhou, Jinian Bian, Yici Cai, Xianlong Hong. 506-510 [doi]
- Lagrangian relaxation based register placement for high-performance circuitsMei-Fang Chiang, Takumi Okamoto, Takeshi Yoshimura. 511-516 [doi]
- Implementation of power managed hyper transport system for transmission of HD videoAdithya V. Kodati, Koneswara S. Vemuri, Lili He, Morris Jones. 517-521 [doi]
- Power aware placement for FPGAs with dual supply voltagesZohreh Karimi, Majid Sarrafzadeh. 522-526 [doi]
- VLSI architectures of perceptual based video watermarking for real-time copyright protectionSaraju P. Mohanty, Elias Kougianos, Wei Cai, Manish Ratnani. 527-534 [doi]
- VeriC: A semi-hardware description language to bridge the gap between ESL design and RTL modelsShu-Hsuan Chou, Che-Neng Wen, Yan-Ling Liu, Tien-Fu Chen. 535-540 [doi]
- Power estimation methodology for a high-level synthesis frameworkSumit Ahuja, Deepak Mathaikutty, Gaurav Singh, Joe Stetzer, Sandeep K. Shukla, Ajit Dingankar. 541-546 [doi]
- Variability aware modeling of SoCs: From device variations to manufactured system yieldMiguel Miranda, B. Dierickx, P. Zuber, P. Dobrovoln, F. Kutscherauer, P. Roussel, P. Poliakov. 547-553 [doi]
- Kriging Model combined with latin hypercube sampling for surrogate modeling of analog integrated circuit performanceHailong You, Maofeng Yang, Dan Wang, Xinzhang Jia. 554-558 [doi]
- Retrospective on electronics technology and prospective methods for co-design of IC packaging and manufacturing improvementsJoseph Fjelstad. 559-564 [doi]
- 50GB/s signaling on organic substrates using PMTL technologyFarhang Yazdani, Jamal S. Izadian. 565-568 [doi]
- Die/wafer stacking with reciprocal design symmetry (RDS) for mask reuse in three-dimensional (3D) integration technologySyed M. Alam, Robert E. Jones, Scott Pozder, Ankur Jain. 569-575 [doi]
- Parallel flow to analyze the impact of the voltage regulator model in nanoscale power distribution networkAmirali Shayan Arani, Xiang Hu, He Peng, Wenjian Yu, Wanping Zhang, Chung-Kuan Cheng, Mikhail Popovich, Xiaoming Chen, Lew Chua-Eoan, Xiaohua Kong. 576-581 [doi]
- An analytic model for Ge/Si core/shell nanowire MOSFETs considering drift-diffusion and ballistic transportLining Zhang, Jin He, Jian Zhang, Feng Liu, Yue Fu, Yan Song, Xing Zhang. 582-587 [doi]
- Zero clock skew synchronization with rotary clocking technologyVinayak Honkote, Baris Taskin. 588-593 [doi]
- Place and route considerations for voltage interpolated designsKevin Brownell, Ali Durlov Khan, David Brooks, Gu-Yeon Wei. 594-600 [doi]
- Crosstalk pessimism reduction with path base analysisGenichi Tanaka, Koichi Nakashiro. 601-606 [doi]
- The impact of BEOL lithography effects on the SRAM cell performance and yieldYing Zhou, Rouwaida Kanj, Kanak Agarwal, Zhuo Li, Rajiv V. Joshi, Sani R. Nassif, Weiping Shi. 607-612 [doi]
- Process variation impact on FPGA configuration memoryYanzhong Xu, Lin-Shih Liu, Mark Chan, Jeff Watt. 613-616 [doi]
- Efficient statistical analysis of read timing failures in SRAM circuitsSoner Yaldiz, Umut Arslan, Xin Li, Larry T. Pileggi. 617-621 [doi]
- Increasing memory yield in future technologies through innovative designCostas Argyrides, Ahmad A. Al-Yamani, Carlos Arthur Lang Lisbôa, Luigi Carro, Dhiraj K. Pradhan. 622-626 [doi]
- An efficient current-based logic cell model for crosstalk delay analysisDebasish Das, William Scott, Shahin Nazarian, Hai Zhou. 627-633 [doi]
- An application-specific adjoint sensitivity analysis framework for clock mesh sensitivity computationXiaoji Ye, Peng Li. 634-640 [doi]
- Early clock prototyping for design analysis and quality entitlementRamamurthy Vishweshwara, Ramakrishnan Venkatraman, Vipul Kadodwala. 641-646 [doi]
- Automatic register banking for low-power clock treesWenting Hou, Dick Liu, Pei-Hsin Ho. 647-652 [doi]
- A study of decoupling capacitor effectiveness in power and ground grid networksAida Todri, Malgorzata Marek-Sadowska, Francois Maire, Christophe Matheron. 653-658 [doi]
- A 0.56-V 128kb 10T SRAM using column line assist (CLA) schemeShunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto. 659-663 [doi]
- Design and implementation of a sub-threshold BFSK transmitterSuganth Paul, Rajesh Garg, Sunil P. Khatri, Sheila Vaidya. 664-672 [doi]
- A universal level converter towards the realization of energy efficient implantable drug delivery Nano-Electro-Mechanical-SystemsSaraju P. Mohanty, Dhruva Ghai, Elias Kougianos, Bharat Joshi. 673-679 [doi]
- Temperature effects on energy optimization in sub-threshold circuit designBasab Datta, Wayne Burleson. 680-685 [doi]
- Charge recovery logic as a side channel attack countermeasureAmir Moradi, Mehrdad Khatir, Mahmoud Salmasizadeh, Mohammad T. Manzuri Shalmani. 686-691 [doi]
- Impact of SoC power management techniques on verification and testingBhanu Kapoor, Shankar Hemmady, Shireesh Verma, Kaushik Roy, Manuel A. d Abreu. 692-695 [doi]
- A study on impact of loading effect on capacitive crosstalk noiseAlodeep Sanyal, Abhisek Pan, Sandip Kundu. 696-701 [doi]
- Simultaneous test pattern compaction, ordering and X-filling for testing power reductionJu-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He. 702-707 [doi]
- Markov source based test length optimized SCAN-BIST architectureAftab Farooqi, Richard O. Gale, Sudhakar M. Reddy, Brian Nutter, Chris Monico. 708-713 [doi]
- Calculation of stress probability for NBTI-aware timing analysisAlexander Stempkovsky, Alexey Glebov, Sergey Gavrilov. 714-718 [doi]
- Derating for static timing analysis: Theory and practiceAli Dasdan, Santanu Kolay, Mustafa Yazgan. 719-727 [doi]
- An information theoretic framework to compute the MAX/MIN operations in parameterized statistical timing analysisNikolay Rubanov. 728-733 [doi]
- A generalized V-shaped multilevel method for large scale floorplanningSong Chen, Zheng Xu, Takeshi Yoshimura. 734-739 [doi]
- Simultaneous buffer and interlayer via planning for 3D floorplanningXu He, Sheqin Dong, Yuchun Ma, Xianlong Hong. 740-745 [doi]
- IR-drop management CAD techniques in FPGAs for power grid reliabilityAkhilesh Kumar, Mohab Anis. 746-752 [doi]
- Functionally valid gate-level peak power estimation for processorsSriram Sambamurthy, Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham. 753-758 [doi]
- On-chip DC-DC converters for three-dimensional ICsJonathan Rosenfeld, Eby G. Friedman. 759-764 [doi]
- Active decap design considerations for optimal supply noise reductionXiongfei Meng, Resve A. Saleh. 765-769 [doi]
- Efficient power network analysis with complete inductive modelingShan Zeng, Wenjian Yu, Wanping Zhang, Jian Wang, Xianlong Hong, Chung-Kuan Cheng. 770-775 [doi]
- Parallel partitioning based on-chip power distribution network analysis using locality accelerationZhiyu Zeng, Peng Li, Zhuo Feng. 776-781 [doi]
- SRAM supply voltage scaling: A reliability perspectiveAnimesh Kumar, Jan M. Rabaey, Kannan Ramchandran. 782-787 [doi]
- Low power adaptive pipeline based on instruction isolationSeung Eun Lee, Chris Wilkerson, Ming Zhang, Rajendra Yavatkar, Shih-Lien Lu, Nader Bagherzadeh. 788-793 [doi]
- Post-Silicon Clock-nvert (PSCI) for reducing process-variation induced skew in buffered clock networksCharbel J. Akl, Rafic A. Ayoubi, Magdy A. Bayoumi. 794-798 [doi]
- Variation-tolerant hierarchical voltage monitoring circuit for soft error detectionAshay Narsale, Michael C. Huang. 799-805 [doi]
- SEU hardened clock regeneration circuitsRajballav Dash, Rajesh Garg, Sunil P. Khatri, Gwan S. Choi. 806-813 [doi]
- PVT variation impact on voltage island formation in MPSoC designSohaib Majzoub, Resve Saleh, Rabab Ward. 814-819 [doi]
- Uncriticality-directed scheduling for tackling variation and power challengesToshinori Sato, Shingo Watanabe. 820-825 [doi]
- Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs)Avinash Karanth Kodi, Ahmed Louri, Janet Meiling Wang. 826-832 [doi]
- NBTI aware workload balancing in multi-core systemsJin Sun, Avinash Karanth Kodi, Ahmed Louri, Janet Meiling Wang. 833-838 [doi]
- Joint write policy and fault-tolerance mechanism selection for caches in DSM technologies: Energy-reliability trade-offMehrtash Manoochehri, Alireza Ejlali, Seyed Ghassem Miremadi. 839-844 [doi]