Abstract is missing.
- Stack based sense amplifier designs for reducing input-referred offsetJames Boley, Benton H. Calhoun. 1-4 [doi]
- Designing low-VTh STT-RAM for write energy reduction in scaled technologiesFarah B. Yahya, Mohammad Mansour, James Tschanz, Muhammad M. Khellah. 5-9 [doi]
- High-performance and high-yield 5 nm underlapped FinFET SRAM design using P-type access transistorsRoohollah Yarmand, Behzad Ebrahimi, Hassan Afzali-Kusha, Ali Afzali-Kusha, Massoud Pedram. 10-17 [doi]
- An energy-efficient on-chip memory structure for variability-aware near-threshold operationJun Shiomi, Tohru Ishihara, Hidetoshi Onodera. 23-28 [doi]
- Thermal sensor allocation for SoCs based on temperature gradientsJun Yong Shin, Fadi J. Kurdahi, Nikil D. Dutt. 29-34 [doi]
- Clock skew optimization for maximizing time margin by utilizing flexible flip-flop timingHyungjung Seo, Jeongwoo Heo, Taewhan Kim. 35-39 [doi]
- Large-scale multi-corner leakage optimization under the sign-off timing environmentGeorge Gonzalez, Murari Mani, Mahesh Sharma. 40-45 [doi]
- Fast obstacle-avoiding octilinear steiner minimal tree construction algorithm for VLSI designXing Huang, Wenzhong Guo, Guolong Chen. 46-50 [doi]
- A router for via configurable structured ASIC with standard cells and relocatable IPsChiung-Chih Ho, Hsin-Pei Tsai, Liang-Chi Lai, Rung-Bin Lin. 51-56 [doi]
- Circuit design perspectives for Ge FinFET at 10nm and beyondS. Sinha, Lucian Shifren, Vikas Chandra, Brian Cline, Greg Yeric, Robert C. Aitken, Bingjie Cheng, Andrew R. Brown, Craig Riddet, C. Alexandar, Campbell Millar, Asen Asenov. 57-60 [doi]
- Electrical characteristic and power consumption fluctuations of trapezoidal bulk FinFET devices and circuits induced by random line edge roughnessChieh-Yang Chen, Wen-Tsung Huang, Yiming Li. 61-64 [doi]
- Study of the impact of aging on many-core energy-efficient DSP systemsMeeta Srivastav, Leyla Nazhandali. 66-70 [doi]
- GlYFF: A framework for global yield and floorplan aware design optimizationShuo Wang, Yue Gao, Melvin A. Breuer. 70-76 [doi]
- Method for efficient flash bit cell current compression in deeply erased bitsJon Nafziger, Dan Burggraf. 77-81 [doi]
- A simplified single-inductor dual-output DC-DC buck converter architecture with a fully digital Σ-Δ based controllerNijad Anabtawi, Rony Ferzli. 82-85 [doi]
- A CMOS hysteretic DC-DC buck converter with a low output ripple voltageTae-Jin Chung, Kwang S. Yoon. 86-89 [doi]
- A 4-14 Gbps inductor-less adaptive linear equalizer using hybrid filter in 65 nm CMOS technologyGovardhana Rao Talluri, K. K. Rakesh, Maryam Shojaei Baghini. 90-97 [doi]
- A digitally-controlled power-aware low-dropout regulator to reduce standby current drain in ultra-low-power MCUKaushik Mazumdar, Steven Bartling, Sudhanshu Khanna, Mircea R. Stan. 98-102 [doi]
- A radiation-hardened-by-design phase-locked loop using feedback voltage controlled oscillatorSeok Min Jung, Janet Meiling Roveda. 103-106 [doi]
- Design of a sigma-delta modulator in standard CMOS process for wide-temperature applicationsYucai Wang, Vamsy P. Chodavarapu. 107-111 [doi]
- Architectural reliability estimation using design diversityZheng Wang, Liu Yang, Anupam Chattopadhyay. 112-117 [doi]
- Tabu search based multiple voltage scheduling under both timing and resource constraintsJianmo Ni, Nan Wang, Takeshi Yoshimura. 118-122 [doi]
- Cache-aware SPM allocation algorithms for hybrid SPM-cache architecturesLan Wu, Wei Zhang. 123-129 [doi]
- Task partitioning optimization algorithm for energy saving and load balance on NoC-based MPSoCsMarco P. Stefani, Thais Webber, Ramon Fernandes, Rodrigo Cataldo, Leticia B. Poehls, César A. M. Marcon. 130-134 [doi]
- Improved pipeline data flow for DySER-based platformZijian Hou, Xin Chen, Weifeng He. 135-140 [doi]
- Rapid heterogeneous prototyping from SimulinkShen Feng, Chris Driscoll, Jerediah Fevold, Hao Jiang, Gunar Schirner. 141-146 [doi]
- LBIST pattern reduction by learning ATPG test cube propertiesGustavo K. Contreras, Yang Zhao, Nisar Ahmed, LeRoy Winemberg, Mohammad Tehranipoor. 147-153 [doi]
- Preemptive built-in self-test for in-field structural testingPanagiotis Sismanoglou, Vlasis Pitsios, Dimitris Nikolos. 154-161 [doi]
- A scan shifting method based on clock gating of multiple groups for low power scan testingSungyoul Seo, Yong Lee 0002, Joohwan Lee, Sungho Kang. 162-166 [doi]
- Designing effective scan compression solutions for industrial circuitsSubramanian Chebiyam, Anshuman Chandra, Rohit Kapur. 167-172 [doi]
- Low power scan bypass technique with test data reductionHyunyul Lim, Wooheon Kang, Sungyoul Seo, Yong Lee, Sungho Kang. 173-176 [doi]
- Incremental ATPG methods for multiple faults under multiple fault modelsMasahiro Fujita, Naoki Taguchi, Kentaro Iwata, Alan Mishchenko. 177-180 [doi]
- Energy reduction by built-in body biasing with single supply voltage operationNorihiro Kamae, Islam A. K. M. Mahfuzul, Akira Tsuchiya, Tohru Ishihara, Hidetoshi Onodera. 181-185 [doi]
- Design of an incoherent IR-UWB receiver front-end in 180-nm CMOS technologyJihai Duan, Qiangyu Hao, Yu Zheng, Baolin Wei, Weilin Xu, Shichao Xu. 186-190 [doi]
- Analysis and optimization of flip-flops under process and runtime variationsMohammad Saber Golanbari, Saman Kiamehr, Mehdi Baradaran Tahoori, Sani R. Nassif. 191-196 [doi]
- Energy efficient design of DVB-T2 constellation demapperNourhan M. Bahgat, DiaaEldin S. Khalil, Salwa H. El-Ramly. 197-200 [doi]
- Advanced encryption system with dynamic pipeline reconfiguration for minimum energy operationSrivatsan Chellappa, Chandarasekaran Ramamurthy, Vinay Vashishtha, Lawrence T. Clark. 201-206 [doi]
- Temperature aware refresh for DRAM performance improvement in 3D ICsMenglong Guan, Lei Wang 0003. 207-211 [doi]
- Adaptive tracking channel control for GNSS receivers under renewable energyWenjie Huang, Lei Wang. 212-216 [doi]
- Novel SAT-based invariant-directed low-power synthesisMahmoud Elbayoumi, Michael S. Hsiao, Mustafa ElNainay. 217-222 [doi]
- Application and OS unconscious power manager for SoC systemsHend Affes, Amal Chaker, Michel Auguin. 223-226 [doi]
- Orchestrated application quality and energy storage management in solar-powered embedded systemsNga Dang, Hossein Tajik, Nikil D. Dutt, Nalini Venkatasubramanian, Eli Bozorgzadeh. 227-233 [doi]
- Optimal choice of FinFET devices for energy minimization in deeply-scaled technologiesMohammad Saeed Abrishami, Alireza Shafaei, Yanzhi Wang, Massoud Pedram. 234-238 [doi]
- Ultra-fast variability-aware optimization of mixed-signal designs using bootstrapped krigingSaraju P. Mohanty, Elias Kougianos, Venkata P. Yanambaka. 239-242 [doi]
- Novel technique for P-hit single-event transient mitigation using enhance dummy transistorTianqi Wang, Liyi Xiao, Mingxue Huo, Chunhua Qi, Shanshan Liu. 243-249 [doi]
- Signal domain based reachability analysis in RTL circuitsSharad Bagri, Kelson Gent, Michael S. Hsiao. 250-256 [doi]
- Equivalence checking of scheduling in high-level synthesisTun Li, Jian Hu, Yang Guo, Sikun Li, Qingping Tan. 257-262 [doi]
- Design and analysis of low pass microstrip filters using MATLABLuv Tomar, Saurabh Gupta, Raghuvir Tomar, Prakash Bhartia. 263-266 [doi]
- Employing dynamic body-bias for short circuit power reduction in SRAMsYakup Murat Mert, Osman Seckin Simsek. 267-271 [doi]
- Accurate standard cell characterization and statistical timing analysis using multivariate adaptive regression splinesTaizhi Liu, Chang-Chih Chen, Linda S. Milor. 272-279 [doi]
- Design optimization of sense amplifiers using deeply-scaled FinFET devicesAlireza Shafaei, Yanzhi Wang, Antonio Petraglia, Massoud Pedram. 280-283 [doi]
- A fault prediction module for a fault tolerant NoC operationJarbas Silveira, Mathieu Bodin, Joao Marcelo Ferreira, Alan Cadore Pinheiro, Thais Webber, César A. M. Marcon. 284-288 [doi]
- User power-delay budget driven PSO based design space exploration of optimal k-cycle transient fault secured datapath during high level synthesisAnirban Sengupta, Saumya Bhadauria. 289-292 [doi]
- A distinctive O(mn) time algorithm for optimal buffer insertionsXinsheng Wang, Wenpan Liu, Mingyan Yu. 293-297 [doi]
- Design and analysis of novel SRAM PUFs with embedded latch for robustnessJae-Won Jang, Swaroop Ghosh. 298-302 [doi]
- Fast synthesis of low power clock trees based on register clusteringChao Deng, Yici Cai, Qiang Zhou. 303-309 [doi]
- Irregularly shaped voltage islands generation with hazard and heal strategyZhen Meng, Song Chen, Lu Huang. 310-315 [doi]
- Impact of geometry parameter on electromigration reliability in FCBGA packageLihua Liang, Yuanxiang Zhang, Richard Rao. 316-321 [doi]
- Enhancing system-wide power integrity in 3D ICs with power gatingHailang Wang, Emre Salman. 322-326 [doi]
- Temperature-aware thread assignment of many-core processorSheXiao Xuan, Y. Yang. 332-336 [doi]
- Separation of concerns for hardware components of embedded systems in BIPMaya H. Safieddine, Rouwaida Kanj, Fadi A. Zaraket, Ali S. Elzein, Mohamad Jaber. 337-344 [doi]
- Unreachable code identification for improved line coverageLuke Pierce, Spyros Tragoudas. 345-351 [doi]
- Fail-safe I/O to control RESET# pin of DDR3 SDRAM and achieve ultra-low system powerRajat Chauhan, Prajkta Vyavahare, Siva Kothamasu. 357-360 [doi]
- On-line reliability-aware dynamic power management for real-time systemsMing Fan, Qiushi Han, Shuo Liu, Gang Quan. 361-365 [doi]
- Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technologySylvain Clerc, Fady Abouzeid, Darayus Adil Patel, Jean-Marc Daveau, Cyril Bottoni, Lorenzo Ciampolini, Fabien Giner, David Meyer, Robin Wilson, Philippe Roche, Sylvie Naudet, Arnaud Virazel, Alberto Bosio, Patrick Girard. 366-370 [doi]
- Efficient static D-latch standard cell characterization using a novel setup time modelArvind Sharma, Yogendra Sharma, Sudeb Dasgupta, Bulusu Anand. 371-378 [doi]
- TDTB error detecting latches: Timing violation sensitivity analysis and optimizationMatheus T. Moreira, Dylan Hand, Peter A. Beerel, Ney Laert Vilar Calazans. 379-383 [doi]
- Adaptive mode assignment in performance-critical cyber-physical systemsZhaohui Cyril Yuan, Rong Zhu, Yiqin Cao, Guifen Jiang. 384-391 [doi]
- Trading-off system load and communication in mapping heuristics for improving NoC-based MPSoCs reliabilityMarcelo Mandelli, Luciano Ost, Gilles Sassatelli, Fernando Gehm Moraes. 392-396 [doi]
- A 2-layer laser multiplexed photonic network-on-chipDharanidhar Dang, Biplab Patra, Rabi N. Mahapatra. 397-401 [doi]
- Exploring shared memory and cache to improve GPU performance and energy efficiencyHao Wen, Wei Zhang. 402-405 [doi]
- Enhancing performance of wireless NoCs with distributed MAC protocolsKarthi Duraisamy, Ryan Gary Kim, Partha Pratim Pande. 406-411 [doi]
- Exploiting abstraction, learning from random simulation, and SVM classification for efficient dynamic prediction of software health problemsMiroslav N. Velev, Chaoqiang Zhang, Ping Gao 0002, Alex David Groce. 412-418 [doi]
- Optimum domain partitioning to increase functional verification coverageJomu George Mani Paret, Otmane Aït Mohamed. 419-423 [doi]
- Crosstalk-aware signal probability-based dynamic statistical timing analysisYao Chen, Andrew B. Kahng, Bao Liu, Wenjun Wang. 424-429 [doi]
- A low area calibration technique of TDC using variable clock generator for accurate on-line delay measurementKentaroh Katoh, Kazuteru Namba. 430-434 [doi]
- Near optimal repair rate built-in redundancy analysis with very small hardware overheadWoosung Lee, Keewon Cho, Jooyoung Kim, Sungho Kang. 435-439 [doi]
- A survey on memristor modeling and security applicationsM. T. Arafin, Carson Dunbar, Gang Qu, N. McDonald, L. Yan. 440-447 [doi]
- Digital PUF using intentional faultsTeng Xu, Miodrag Potkonjak. 448-451 [doi]
- Side channel attacks in embedded systems: A tale of hostilities and deterrenceJude Angelo Ambrose, Roshan G. Ragel, Darshana Jayasinghe, Tuo Li 0001, Sri Parameswaran. 452-459 [doi]
- Fault-tolerant methods for a new lightweight cipher SIMONJaya Dofe, Connor Reed, Ning Zhang, Qiaoyan Yu. 460-464 [doi]
- Novel self-calibrating recycling sensor using Schmitt-Trigger and voltage boosting for fine-grained detectionCheng-Wei Lin, Swaroop Ghosh. 465-469 [doi]
- The low power design of SM4 cipher with resistance to differential power analysisYanbo Niu, Anping Jiang. 470-474 [doi]
- Comparative evaluation of FPGA and ASIC implementations of bufferless and buffered routing algorithms for on-chip networksYu Cai, Ken Mai, Onur Mutlu. 475-484 [doi]
- Hardened design based on advanced orthogonal Latin code against two adjacent multiple bit upsets (MBUs) in memoriesLiyi Xiao, Jiaqiang Li, Jie Li, Jing Guo. 485-489 [doi]
- Scratch-pad memory banking by dynamic programming for embedded data-intensive applicationsFlorin Balasa, Noha Abuaesh, Ilie I. Luican, Hongwei David Zhu. 490-494 [doi]
- A hypervisor approach with real-time support to the MIPS M5150 processorSamir Zampiva, Carlos Moratelli, Fabiano Hessel. 495-501 [doi]
- RT-MIL-STD-1553+: Remote terminal controller for MIL-STD-1553B at 100-Mb/s data ratePrateek Pendyala, Vijaya Sankara Rao Pasupureddi. 502-506 [doi]
- Low power scheduling in high-level synthesis using dual-Vth librarySamaneh Ghandali, Bijan Alizadeh, Zainalabedin Navabi. 507-511 [doi]
- A novel approach to IC, package and board co-optimizationGary Brist, John Park. 512-518 [doi]
- An effective model for evaluating vertical propagation delay in TSV-based 3-D ICsMasayuki Watanabe, Nanako Niioka, Tetsuya Kobayashi, Rosely Karel, Masa-Aki Fukase, Masashi Imai, Atsushi Kurokawa. 519-523 [doi]
- Automatic die placement and flexible I/O assignment in 2.5D IC designDaniel P. Seemuth, Azadeh Davoodi, Katherine Morrow. 524-527 [doi]
- Resource allocation methodology for through silicon vias and sleep transistors in 3D ICsHailang Wang, Emre Salman. 528-532 [doi]
- Recovery of faulty TSVs in 3D ICsSurajit Kumar Roy, Kaustav Roy, Chandan Giri, Hafizur Rahaman. 533-536 [doi]
- Novel adaptive power gating strategy of TSV-based multi-layer 3D ICSeungwon Kim, Seokhyung Kang, Ki Jin Han, Youngmin Kim. 537-541 [doi]
- A low-power field-programmable analog array for wireless sensingBrandon Rumberg, David W. Graham. 542-546 [doi]
- On improving the range of inductive proximity sensors for avionic applicationsPaul Leons, Aryan Yaghoubian, Glenn Cowan, Jelena Trajkovic, Yvon Nazon, Samar Abdi. 547-551 [doi]
- A new single inductor bipolar multiple output (SIBMO) boost converter using pulse frequency modulation (PFM) control for OLED drivers and optical transducersChun-Kai Chang, Chung-Hsin Su, Yung-Hua Kao, Ming-Hung Yu, Thilo Sauter, Paul C.-P. Chao. 552-555 [doi]
- RFID indoor localization based on Doppler effectDeivid A. Tesch, Everton L. Berz, Fabiano Hessel. 556-560 [doi]
- A novel physical failure analysis of MEMS motion sensor for interface inspectionChun-An Huang, Li-Chuang, Kim Hsu, Steel Chung, Tim Chan. 561-564 [doi]
- Exploring memory controller configurations for many-core systems with 3D stacked DRAMsFen Ge, Jia Zhan, Yuan Xie 0001, Vijaykrishnan Narayanan. 565-570 [doi]
- Virtual logic netlist: Enabling efficient RTL analysisSpandana Rachamalla, Arun Joseph, Rahul Rao, Diwesh Pandey. 571-576 [doi]
- A logic difference generator with spare cells consideration for ECO synthesisJui-Hung Hung, Yu-Cheng Lin, Wei-Kai Cheng, Tsai-Ming Hsieh. 577-580 [doi]
- Cells reconfiguration around defects in CMOS/nanofabric circuits using simulated evolution heuristicAbdalrahman M. Arafeh, Sadiq M. Sait. 581-588 [doi]
- Layout-aware analog synthesis environment with yield considerationHsin-Ju Chang, Yen-Lung Chen, Conan Yeh, Chien-Nan Jimmy Liu. 589-593 [doi]
- A comparative analysis of symmetric and asymmetric dual-k spacer FinFETs from device and circuit perspectivesPankaj Kumar Pal, B. K. Kaushik, B. Anand, S. DasGupta. 594-598 [doi]
- Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology nodeChenyun Pan, Praveen Raghavan, Francky Catthoor, Zsolt Tokei, Azad Naeemi. 599-603 [doi]
- Domain wall motion-based low power hybrid spin-CMOS 5-bit Flash Analog Data ConverterKarthik Yogendra, Mei-Chin Chen, Xuanyao Fong, Kaushik Roy. 604-609 [doi]
- 6-T SRAM performance assessment with stacked silicon nanowire MOSFETsYa-Chi Huang, Meng-Hsueh Chiang, Wei-Chou Hsu, Shiou-Ying Cheng. 610-614 [doi]
- Partially depleted silicon-on-ferroelectric insulator field effect transistor (PD-SOFFET)Azzedin D. Es-Sakhi, Masud H. Chowdhury. 615-619 [doi]