Table of Contents

• Swarm - A VLSI Timing, Fanout-aware Clustering AlgorithmChristos P. Sotiriou, George Rafael Goudroumanis, Nikolaos Sketopoulos, Christos Georgakidis. 1-8 [doi]
• MORE-Router+: Multilayer Multi-capacity ORdered Escape Routing via Bus-oriented Layer AssignmentZhenyi Gao, Sheqin Dong, Zifei Cheng, Wenjian Yu. 1-7 [doi]
• A Comparative Analysis of Microrings Based Incoherent Photonic GEMM AcceleratorsSairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Oluwaseun Adewunmi Alo, Ishan G. Thakkar. 1-8 [doi]
• A multi band flexible N-path filter suited for non-contiguous channel aggregationChadi Jabbour. 1-6 [doi]
• Ultra-Low Voltage Enablement for Standard Cells with Moment based LVFRohit Kumar Gupta, Chiranjeev Grover, Etienne Maurin, Jean-Arnaud Francois, Olivier Minez, Sébastien Marchal. 1-5 [doi]
• Exploring Model Poisoning Attack to Convolutional Neural Network Based Brain Tumor Detection SystemsKusum Lata, Prashant Singh, Sandeep Saini. 1-7 [doi]
• RTKWS: Real-Time Keyword Spotting Based on Integer Arithmetic for Edge DeploymentPrakash Dhungana, Sayed Ahmad Salehi. 1-7 [doi]
• DESPINE: NAS generated Deep Evolutionary Adaptive Spiking Network for Low Power Edge Computing ApplicationsB. S. Ajay, Phani Pavan K, Madhav Rao. 1-8 [doi]
• GridVAE: Fast Power Grid EM-Aware IR Drop Prediction and Fixing Accelerated by Variational AutoEncoderYibo Liu, Sheldon X.-D. Tan. 1-6 [doi]
• Trojan Attacks on Variational Quantum Circuits and CountermeasuresSubrata Das, Swaroop Ghosh. 1-8 [doi]
• Timing-Driven High-Level Synthesis for Continuous-Flow Microfluidic BiochipsZhengyang Ye, Zhisheng Chen, Youlin Pan, Genggeng Liu, Wenzhong Guo, Tsung-Yi Ho, Xing Huang. 1-6 [doi]
• SLO-ECO: Single-Line-Open Aware ECO Detailed Placement and Detailed Routing Co-OptimizationJoong-Won Jeon, Andrew B. Kahng, Jaehyun Kang, Jaehwan Kim, Mingyu Woo. 1-8 [doi]
• Design-Technology Co-Optimization with Standard Cell Layout Generator for Pin ConfigurationsJunghyun Yoon, Heechun Park. 1-7 [doi]
• FastPASE: An AI-Driven Fast PPA Speculation Engine for RTL Design Space OptimizationAkash Levy, Joe Walston, Sourav Samanta, Priyanka Raina, Stelios Diamantidis. 1-8 [doi]
• HISPE: High-Speed Configurable Floating-Point Multi-Precision Processing ElementB. N. Tejas, Rakshit Bhatia, Madhav Rao. 1-8 [doi]
• Thinking Outside the Clock: Physical Design for Field-coupled Nanocomputing with Deep Reinforcement LearningSimon Toni Hofmann, Marcel Walter, Lorenzo Servadei, Robert Wille. 1-8 [doi]
• QuEST: Quantum Circuit Output Estimation using Gaussian Distribution AnalysisShamik Kundu, Navnil Choudhury, Kanad Basu. 1-8 [doi]
• Multi-ALM: Run-time Multi-Level Reconfigurable Approximate Logarithmic MultiplierMaliha Tasnim, Chinmay Raje, Sheldon X.-D. Tan. 1-6 [doi]
• A Needle in the Haystack: Inspecting Circuit Layout to Identify Hardware TrojansXingyu Meng, Abhrajit Sengupta, Kanad Basu. 1-8 [doi]
• Enhanced Detection of Thermal Covert Channel Attacks in Multicore ProcessorsKrithika Dhananjay, Vasilis F. Pavlidis, Ayse K. Coskun, Emre Salman. 1-7 [doi]
• Graph Neural Network-Based Detailed Placement Optimization FrameworkDho Ui Lim, Heechun Park. 1-6 [doi]
• Composite Sub-surface Model for RF GaN-HEMTsX. Zhou, W. Yang, S. B. Chiah. 1 [doi]
• SpotLight: A Hotspot-Greedy, Light-Weighted, and Automated Thermal Modeling Framework for Early Smartphone DesignChin-Wei Wu, Yu-Min Lee, Pei-Yu Huang, Bo-Jiun Yang, Tai-Yu Chen, Ting-Chang Huang, Yen-Lin Lee. 1-8 [doi]
• Fused Functional Units for Area-Efficient CGRAsRon Jokai, Cheng Tan 0002, Jeff Jun Zhang. 1-8 [doi]
• Trojan Assets and Attack Vectors in ProcessorsCzea Sie Chuah, Alexander Hepp, Christian Appold, Tim Leinmüller. 1-10 [doi]
• An Energy-Efficient Time Domain Based Compute In-Memory Architecture for Binary Neural NetworkSubhradip Chakraborty, Dinesh Kushwaha, Abhishek Goel, Anmol Singla, Anand Bulusu, Sudeb Dasgupta. 1-6 [doi]
• Bring it On: Kinetic Energy Harvesting to Spark Machine Learning Computations in IoTsSanket Shukla, Sai Manoj Pudukotai Dinakarrao. 1-6 [doi]
• A 5T Half-SRAM Design for Cold CMOS Physical Unclonable Function Applications and BeyondRouwaida Kanj, Jamil Kawa. 1-8 [doi]
• Time-Domain-Based Non-volatile In-Memory Computing Architecture Using FeFETs for Binary Neural NetworkAditya Sharma, Vatsal Dixit, Dinesh Kushwaha, Nitanshu Chauhan, Vishal Kumar Saxena, Sudeb Dasgupta, Anand Bulusu. 1-8 [doi]
• An Automated Exhaustive Fault Analysis Technique guided by Processor Formal Verification MethodsEndri Kaja, Nicolas Gerlin, Bihan Zhao, Daniela Sanchez Lopera, Jad Al Halabi, Azam Sher Khan, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker. 1-8 [doi]
• Parasitic Capacitance Patterns Grid Density Binarization and Shifted Reflection Step Sequence Encoding for Dimensionality ReductionPing Li, Zhong Guan. 1-8 [doi]
• Non-parametric Greedy Optimization of Parametric Quantum CircuitsKoustubh Phalak, Swaroop Ghosh. 1-7 [doi]
• High-Level Synthesis for Microfluidic Biochips Considering Actual Volume Management and Channel StorageZhengyang Chen, Yuhan Zhu, Zhen Chen, Zhisheng Chen, Genggeng Liu. 1-8 [doi]
• RTL Simulation Acceleration with Machine Learning ModelsSurajit Das, Hetang Patel, Chandan Karfa, Kartheek Bellamkonda, Rahul Reddy, Disha Puri, Anshul Jain, Arijit Sur, Pradip Prajapati. 1-7 [doi]
• Intelligent Malware Detection based on Hardware Performance Counters: A Comprehensive SurveyHossein Sayadi, Zhangying He, Hosein Mohammadi Makrani, Houman Homayoun. 1-10 [doi]
• PSO Optimized Design of Error Balanced Weight Stationary Systolic Array Architecture for CNNDantu Nandini Devi, Gandi Ajay Kumar, Bindu G. Gowda, Madhav Rao. 1-8 [doi]
• RTL Interconnect Obfuscation By Polymorphic Switch Boxes For Secure Hardware GenerationHaimanti Chakraborty, Ranga Vemuri. 1-8 [doi]
• Trimming The Fat: A Minimum-Security Architecture for Protecting SoC Designs Against Supply Chain ThreatsKshitij Raj, Aritra Bhattacharyay, Swarup Bhunia, Sandip Ray. 1 [doi]
• Single-Ferroelectric FET based Associative Memory for Data-Intensive Pattern MatchingJiayi Wang, Songyu Sun, Xunzhao Yin. 1-7 [doi]
• nvXNOR Design with Enhanced Store Capability for BNN ApplicationsZeinab Soueidan, Rouwaida Kanj. 1-7 [doi]
• Full Stage Delay Calculation Using Full Waveform Propagation and Standard Library CCS ModelStavros Simoglou, Iordanis Lilitsis, Nikolaos Blias, Christos P. Sotiriou. 1-8 [doi]
• QNSA: Quantum Neural Simulated Annealing for Combinatorial OptimizationSeongbin Kwon, Dohun Kim, Sunghye Park, Seojeong Kim, Seokhyeong Kang. 1-7 [doi]
• Routing Intent Aware Pin Access Point Selection for Standard Cell DesignsPo-Chun Wang, Kai-Jie Ton, Rung-Bin Lin. 1-8 [doi]
• SRAM-PG: Power Delivery Network Benchmarks from SRAM CircuitsShan Shen, Zhiqiang Liu, Wenjian Yu. 1-7 [doi]
• A novel virtual prototyping methodology for timing-accurate simulation of AMS circuitsTeo Vallone, Hayri Verner Hasou, Ernesto Colizzi, Sara Vinco, Davide Zoni. 1-8 [doi]
• BMX-FPCA: 3D Beyond-Moore Flexible Field Programmable Crossbar Array ArchitectureHasita Veluri, Dilip Vasudevan. 1-9 [doi]
• HiCTL: High Fan-in Differential Capacitive-Threshold-Logic Gate Implementation With an Offset-Compensated ComparatorAbdullah Sahruri, Martin Margala, Ugur Çilingiroglu. 1-7 [doi]
• DECOR: Enhancing Logic Locking Against Machine Learning-Based AttacksYinghua Hu, Kaixin Yang, Subhajit Dutta Chowdhury, Pierluigi Nuzzo 0002. 1-8 [doi]
• Performance-Aware Design of Approximate Integrated MAC Factored Systolic Array AcceleratorsDantu Nandini Devi, Gandi Ajay Kumar, Bindu G. Gowda, Madhav Rao. 1-8 [doi]
• SCORCH: Neural Architecture Search and Hardware Accelerator Co-design with Reinforcement LearningSiqin Liu, Avinash Karanth. 1-8 [doi]
• An FPGA-based Max-K-Cut Accelerator Exploiting Oscillator Synchronization ModelMohammad Khairul Bashar, Zheyu Li, Vijaykrishnan Narayanan, Nikhil Shukla. 1-8 [doi]
• Temporal-encoded 6T-RRAM with Bidirectional Control for Future Neuromorphic SystemsKang Jun Bai, Hao Jiang 0014, Zhuwei Qin, Clare Thiem. 1-6 [doi]
• Sensitivity Analysis of SOT-MTJs to Manufacturing Process Variation: A Hardware Security PerspectiveMousam Hossain, Muhtasim Alam Chowdhury, Ronald F. DeMara, Soheil Salehi. 1-5 [doi]
• Reprogrammable Time-Domain RRAM Based Vector Matrix Multiplier for In-Memory ComputingBipul Boro, Rushik Parmar, Ashvinikumar Dongre, Gaurav Trivedi. 1-8 [doi]
• A 0.186 pJ/bit, 6-Gb/s, Energy-Efficient, Half-Rate Hybrid Circuit Topology in 1.2V, 65 nm CMOSPrema Kumar Govindaswamy, Mursina Khatun, Vijay Shankar Pasupureddi. 1-5 [doi]
• Dual Use Circuitry for Early Failure Warning and TestAlexander Coyle, Hui Jiang, Jennifer Dworak, Theodore W. Manikas, Kundan Nepal. 1-8 [doi]
• Peephole Optimization for Quantum Approximate SynthesisJoseph Clark, Himanshu Thapliyal. 1-8 [doi]
• Automated Assertion Checker Generator and Information Flow Tracking for Security VerificationMiguel Angel Alfaro Zapata, Amirhossein Shahshahani, Zeljko Zilic. 1-6 [doi]
• NAND Flash-Based Digital Fingerprinting for Robust and Secure Hardware AuthenticationKamrul Hasan, Sara Tehranipoor, Nima Karimian, Surbhi Vasudeva. 1-6 [doi]
• LLM-FIN: Large Language Models Fingerprinting Attack on Edge DevicesNajmeh Nazari, Furi Xiang, Chongzhou Fang, Hosein Mohammadi Makrani, Aditya Puri, Kartik Patwari, Hossein Sayadi, Setareh Rafatirad, Chen-Nee Chuah, Houman Homayoun. 1-6 [doi]
• Lightweight Multicast Authentication in NoC-based SoCsHansika Weerasena, Prabhat Mishra 0001. 1-8 [doi]
• Efficient Radix-4 Approximated Modified Booth Multiplier for Signal Processing and Computer Vision: A Probabilistic Design ApproachBindu G. Gowda, Prashanth H. C., V. N. Muralidhara, Madhav Rao. 1-8 [doi]
• A 1.2 V Double-Tail StrongARM Latch Comparator with 51 fJ/comparison and 380 μV Input Noise in 65 nm CMOS TechnologySrinivasa Rao Maram, Subrahmanyam Boyapati, Vijay Shankar Pasupureddi. 1-7 [doi]
• Learning Client Selection Strategy for Federated Learning across Heterogeneous Mobile DevicesSai Qian Zhang, Jieyu Lin, Qi Zhang, Yu-Jia Chen. 1-7 [doi]
• Always be Pre-Training: Representation Learning for Network Intrusion Detection with GNNsZhengyao Gu, Diego Troy Lopez, Lilas Alrahis, Ozgur Sinanoglu. 1-8 [doi]
• TEE-Time: A Dynamic Cache Timing Analysis Tool for Trusted Execution EnvironmentsQuentin Forcioli, Sumanta Chaudhuri, Jean-Luc Danger. 1-8 [doi]
• Error Distribution Estimation for Fixed-point Arithmetic using Program DerivativesSoramichi Akiyama, Ryota Shioya, Yuto Miyatake, Tongxin Yang. 1-9 [doi]
• Fast Current Constraints Generation for Chip SafetyCedric Feghali, Farid N. Najm. 1-8 [doi]
• Emerging Reconfigurable Logic Device Based FPGA Design and OptimizationSheng Lu, Liuting Shang, Sungyong Jung, Chenyun Pan. 1-8 [doi]
• Enhancing Self-sustaining IoT Systems with Autonomous and Smart UAV Data FerryMason Conkel, Wen Zhang, Chen Pan. 1-7 [doi]
• Fake Timer: An Engine for Accurate Timing Estimation in Register Transfer Level DesignsDaniela Sanchez Lopera, Robert Kunzelmann, Endri Kaja, Wolfgang Ecker. 1-8 [doi]
• Exploring Hardware Activation Function Design: CORDIC Architecture in Diverse Floating FormatsMahati Basavaraju, Vinay Rayapati, Madhav Rao. 1-8 [doi]
• Thermo-Attack Resiliency: Addressing a New Vulnerability in Opto-Electrical Network-on-ChipsMahdi Hasanzadeh, Meisam Abdollahi, Amirali Baniasadi, Ahmad Patooghy. 1-9 [doi]
• Deep Learning Based IoT System for Real-time Traffic Risk NotificationsSahidul Islam, Seth Klupka, Ramin Mohammadi, Yu-Fang Jin, Mimi Xie. 1-6 [doi]
• Hyperdimensional Computing vs. Neural Networks: Comparing Architecture and Learning ProcessDongning Ma, Cong Hao, Xun Jiao. 1-5 [doi]
• Toward Early Stage Dynamic Power Estimation: Exploring Alternative Machine Learning Methods and Simulation SchemesPhilipp Fengler, Sani R. Nassif, Ulf Schlichtmann. 1-8 [doi]
• Side-Channel-Driven Intrusion Detection System for Mission Critical Unmanned Aerial VehiclesAlejandro Almeida, Muneeba Asif, Md Tauhidur Rahman, Mohammad Ashiqur Rahman. 1-9 [doi]
• Unleashing Energy-Efficiency: Neural Architecture Search without Training for Spiking Neural Networks on Loihi ChipShiya Liu, Yang Yi. 1-7 [doi]
• Code-Based Cryptography for Confidential Inference on FPGAs: An End-to-End MethodologyRupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu. 1-8 [doi]
• Roofline Performance Analysis of DNN Architectures on CPU and GPU SystemsPrashanth H. C., Madhav Rao. 1-8 [doi]
• DNN Memory Footprint Reduction via Post-Training Intra-Layer Multi-Precision QuantizationBehnam Ghavami, Amin Kamjoo, Lesley Shannon, Steve Wilton. 1-7 [doi]
• EASI-CiM: Event-driven Asynchronous Stream-based Image classifier with Compute-in-Memory kernelsRahul Sreekumar, Minseong Park, Mohammad Nazmus Sakib, Bhupendra S. Reniwal, Kyusang Lee, Mircea R. Stan. 1-8 [doi]
• Comparative Analysis of Graph Isomorphism and Graph Neural Networks for Analog Hierarchy LabelingZhengfeng Wu, Ioannis Savidis. 1-7 [doi]
• A SPICE-based Emulator Framework for Quantum Error Correction Circuits using LC ResonatorsMd. Mazharul Islam 0006, Md. Shafayat Hossain, Ahmedullah Aziz. 1-5 [doi]
• Design and Evaluation of Parametric NTT Hardware Unit using different Multiplier based Modular Reduction TechniquesLokesh Maji, Aman Prajapati, Madhav Rao. 1-6 [doi]
• Model Extraction Attack against On-device Deep Learning with Power Side ChannelJialin Liu, Han Wang. 1-5 [doi]
• Quantum Circuit Simulation with Fast Tensor Decision DiagramQirui Zhang 0001, Mehdi Saligane, Hun-Seok Kim, David T. Blaauw, Georgios Tzimpragos, Dennis Sylvester. 1-8 [doi]
• Deep Learning Enhanced Side Channel Analysis on CRYSTALS-KyberAnh Tuan Hoang, Mark Kennaway, Dung Tuan Pham, Thai Son Mai, Ayesha Khalid, Ciara Rafferty, Máire O'Neill. 1-8 [doi]
• A Low-Dissipation and Scalable GEMM Accelerator with Silicon Nitride PhotonicsVenkata Sai Praneeth Karempudi, Sairam Sri Vatsavai, Ishan G. Thakkar, Oluwaseun Adewunmi Alo, Jeffrey Todd Hastings, Justin Scott Woods. 1-8 [doi]
• Hardware Trojans in Quantum Circuits, Their Impacts, and DefenseRupshali Roy, Subrata Das, Swaroop Ghosh. 1-8 [doi]
• FAST-GO: Fast, Accurate, and Scalable Hardware Trojan Detection using Graph Convolutional NetworksAli Imangholi, Mona Hashemi, Amirabbas Momeni, Siamak Mohammadi, Trevor E. Carlson. 1-8 [doi]
• Advancing Analog Reservoir Computing through Temporal Attention and MLP IntegrationKhalil Sedki, Yang Cindy Yi. 1-8 [doi]
• SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design MethodologyDinesh Kushwaha, Ashish Joshi, Abhishek Goel, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu. 1-8 [doi]
• Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN AcceleratorsMahdi Taheri, Natalia Cherezova, Mohammad Saeed Ansari, Maksim Jenihhin, Ali Mahani 0001, Masoud Daneshtalab, Jaan Raik. 1-8 [doi]
• Merits of Time-Domain Computing for VMM - A Quantitative ComparisonFlorian Freye, Jie Lou, Christian Lanius, Tobias Gemmeke. 1-8 [doi]
• Learning-Based Secure Spectrum Sharing for Intelligent IoT NetworksAmir Alipour Fanid, Monireh Dabaghchian, Long Jiao, Kai Zeng 0001. 1-8 [doi]
• Blending Scheduling Barriers: A Hybrid Approach for FPGA-based Post-Quantum CryptographyCapucine Mien Verone Berger-Sigrist, Andrea Guerrieri. 1 [doi]
• A Low-cost keyword spotting architecture based on wavelet packets feature extraction for edge deviceSayed Ahmad Salehi, Prakash Dhungana. 1 [doi]
• Hardware Support for Trustworthy Machine Learning: A SurveyMd. Shohidul Islam, Ihsen Alouani, Khaled N. Khasawneh. 1-6 [doi]
• Optimizing Layer-Fused Scheduling of Transformer Networks on Multi-accelerator PlatformsSteven Colleman, Arne Symons, Victor J. B. Jung, Marian Verhelst. 1-6 [doi]
• AutoAnnotate: Reinforcement Learning based Code Annotation for High Level SynthesisHafsah Shahzad, Ahmed Sanaullah, Sanjay Arora, Ulrich Drepper, Martin C. Herbordt. 1-9 [doi]
• EDA-ML: Graph Representation Learning Framework for Digital IC Design AutomationPratik Shrestha, Ioannis Savidis. 1-7 [doi]
• sLLM: Accelerating LLM Inference using Semantic Load Balancing with Shared Memory Data StructuresJieyu Lin, Sai Qian Zhang, Alberto Leon-Garcia. 1-6 [doi]
• RASH: Reliable Deep Learning Acceleration using Sparsity-based HardwareShamik Kundu, Arnab Raha, Deepak A. Mathaikutty, Kanad Basu. 1 [doi]
• Write Intensity based Foresightful Page Migration for Hybrid memoriesN. S. Aswathy, Hemangee K. Kapoor. 1-8 [doi]
• Obfuscating Quantum Hybrid-Classical Algorithms for Security and PrivacySuryansh Upadhyay, Swaroop Ghosh. 1-8 [doi]
• A SIMD Dynamic Fixed Point Processing Engine for DNN AcceleratorsGopal Raut, Pranose J. Edavoor, David Selvakumar, Ritambhara Thakur. 1-8 [doi]