Abstract is missing.
- Algorithm for Fast Statistical Timing AnalysisJakob Salzmann, Frank Sill, Dirk Timmermann. 1-4 [doi]
- Is Your Low Power Design Switched On?Mark Croft, Stephen Bailey. 1-4 [doi]
- A Novel Emulation Technique that Preserves Circuit Structure and TimingLeos Kafka, Martin Danek, Ondrej Novák. 1-4 [doi]
- Managing Concurrency by Supporting Object-oriented Programming with Hybrid Data-driven Control-flow ProcessorRaimo Mäkelä, Olli Vainio. 1-4 [doi]
- Energy-Optimal Circuit DesignScott Hanson, Bo Zhai, David T. Blaauw, Dennis Sylvester. 1-4 [doi]
- The Bulk Built In Current Sensor Approach for Single Event Transient DetectionGilson I. Wirth, Christian Fayomi. 1-4 [doi]
- Optimal Subset Mapping And Convergence Evaluation of Mapping Algorithms for Distributing Task Graphs on Multiprocessor SoCHeikki Orsila, Erno Salminen, Marko Hännikäinen, Timo Hämäläinen 0001. 1-6 [doi]
- The NoCRay Graphic Accelerator: a Case-study for MP-SoC Network-on-Chip Design MethodologySergio Tota, Mario R. Casu, Paolo Motto Ros, Massimo Ruo Roch, Maurizio Zamboni. 1-4 [doi]
- Heuristics for Scenario Creation to Enable General Loop TransformationsMartin Palkovic, Henk Corporaal, Francky Catthoor. 1-4 [doi]
- Intelligent cameras and embedded reconfigurable computing: a case-study on motion detectionClaudio Mucci, Luca Vanzolini, Antonio Deledda, Fabio Campi, Gerard Gaillat. 1-4 [doi]
- Using a Linear Sectioned Bus And a Communication Processor to Reduce Energy Costs in Synchronous On-Chip CommunicationKris Heyrman, Antonis Papanikolaou, Francky Catthoor, Peter Veelaert, Wilfried Philips. 1-4 [doi]
- A Configuration Locking Technique to Reduce the Configuration Overhead of Run-Time Reconfigurable DevicesYang Qu, Juha-Pekka Soininen, Jari Nurmi. 1-5 [doi]
- MiGra: A Task Migration Algorithm for Reducing Temperature Gradient in Multiprocessor Systems on ChipSalvatore Carta, Fabio Mereu, Andrea Acquaviva, Giovanni De Micheli. 1-6 [doi]
- Sensor Network-On-ChipGirish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones. 1-4 [doi]
- Control and datapath decoupling in the design of a NoC switch: area, power and performance implicationsSimone Medardoni, Davide Bertozzi, Luca Benini, Enrico Macii. 1-4 [doi]
- A New Look at Reversible Logic Implementation of Decimal AdderRekha K. James, Shahana Thottathikkulam Kassim, K. Poulose Jacob, Sreela Sasi. 1-4 [doi]
- A New LMMSE Receiver Architecture With Dynamic Filter Length OptimisationMark P. Tennant, Ahmet T. Erdogan, Tughrul Arslan, John S. Thompson. 1-4 [doi]
- A Real-Time Learning Processor Based on K-means Algorithm with Automatic Seeds GenerationHirotsugu Shikano, Kiyoto Ito, Kazuhide Fujita, Tadashi Shibata. 1-4 [doi]
- Mapping streaming applications on a reconfigurable MPSoC platform at run-timePhilip K. F. Hölzenspies, Gerard J. M. Smit, Jan Kuper. 1-4 [doi]
- Power Management and Clock Generator for a Novel Passive UWB TagMajid Baghaei Nejad, Hannu Tenhunen, Lirong Zheng 0001. 1-4 [doi]
- Reduce SOC Energy Consumption through Processor ISA ExtensionSteve Leibson. 1-4 [doi]
- A System-level Design Method for Cognitive Radio on a Reconfigurable Multi-processor ArchitectureQiwei Zhang, André B. J. Kokkeler, Gerard J. M. Smit. 1-4 [doi]
- Rendezvous-based MoC for untimed TLMRohit Jindal, Laurent Maillet-Contoz. 1 [doi]
- Configurable Hardware/Software Support for Single Processor Real-Time KernelsSusanna Nordstrom, Lars Asplund. 1-4 [doi]
- Development of Complex SoC Devices Require New Design TechnologiesGuido Schreiner. 1 [doi]
- FPGA Prototype of the REALJava Co-ProcessorTero Säntti, Joonas Tyystjärvi, Juha Plosila. 1-4 [doi]
- A Feature-Based Optical Flow Processor Architecture Featuring Single-Motion-Vector/Cycle GenerationKazuhide Fujita, Kiyoto Ito, Tadashi Shibata. 1-4 [doi]
- Mixed-Signal Focal-Plane Image Processor Employing Tme-domaiin Computation ArchitectureKiyoto Ito, Tadashi Shibata. 1-4 [doi]
- 3-Gb/s, Single-ended Adaptive Equalization of Bidirectional Data over a Multi-drop BusHenrik Fredriksson, Christer Svensson. 1-4 [doi]
- Multi-ASIP SoCs - or how to design ultra-low power architectures for wireless and multi-media systemsGert Goossens. 1 [doi]
- Implementing the conjugate gradient algorithm on multi-core systemsW. A. Wiggers, Vincent Bakker, André B. J. Kokkeler, Gerard J. M. Smit. 1-4 [doi]
- Managing Reconfigurable Resources in Heterogeneous Cores Using Portable Pre-Synthesized TemplatesMarco D. Santambrogio, Matteo Giani, Seda Ogrenci Memik. 1-4 [doi]
- CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOCMaher Assaad, David R. S. Cumming. 1-4 [doi]
- Run-Time Scheduled Hardware Acceleration of MPEG-4 Video DecodingJani Boutellier, Pekka Jääskeläinen, Olli Silvén. 1-4 [doi]