Abstract is missing.
- A Uniform Optimization Technique for Offset Assignment ProblemsRainer Leupers, Fabian David. 3-8 [doi]
- Code Generation for Compiled Bit-True Simulation of DSP ApplicationsLuc De Coster, Marleen Adé, Rudy Lauwereins, J. A. Peperstraete. 9-14 [doi]
- Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement ArchitectureWei-Kai Cheng, Youn-Long Lin. 15-22 [doi]
- Issues in Embedded DRAM Development and ApplicationsDoris Keitel-Schulz, Norbert Wehn. 23-30 [doi]
- A Processor Description Language Supporting Retargetable Multi-Pipeline DSP Program Development ToolsChuck Siska. 31-36 [doi]
- Intellectual Property Re-use in Embedded System Co-design: An Industrial Case StudyEnrica Filippi, Luciano Lavagno, L. Licciardi, A. Montanaro, M. Paolini, Roberto Passerone, Marco Sgroi, Alberto L. Sangiovanni-Vincentelli. 37-42 [doi]
- Incorporating Cores into System-Level SpecificationFrank Vahid, Tony Givargis. 43-50 [doi]
- HDL-Based Modeling of Embedded Processor Behavior for Retargetable CompilationRainer Leupers. 51 [doi]
- False Path Analysis Based on a Hierarchical Control RepresentationApostolos A. Kountouris, Christophe Wolinski. 55-59 [doi]
- Resource Constrained Modulo Scheduling with Global Resource SharingChristoph Jäschke, Rainer Laur. 60-65 [doi]
- Statistical Performance-Driven Module Binding in High-Level SynthesisHiroyuki Tomiyama, Akihiko Inoue, Hiroto Yasuura. 66-71 [doi]
- Concurrent Error Detection at Architectural LevelCristiana Bolchini, William Fornaciari, Fabio Salice, Donatella Sciuto. 72-75 [doi]
- Communication and Interface Synthesis on a Rapid Prototyping Hardware/Software Codesign SystemYin-Tsung Hwang, Yuan-Hung Wang. 76-82 [doi]
- Application-Specific Heterogeneous Multiprocessor Synthesis Using Differential-EvolutionAllan Rae, Sri Parameswaran. 83-88 [doi]
- Proposal for Unified System Design Meta Flow in Task-Level and Instruction-Level Design Technology Research for Multi-Media ApplicationsFrancky Catthoor, Diederik Verkest, Erik Brockmeyer. 89-95 [doi]
- Data-Path Synthesis of VLIW Video Signal ProcessorsZhao Wu, Wayne Wolf. 96-104 [doi]
- Synchronization Detection for Multi-Process Hierarchical SynthesisOliver Bringmann, Wolfgang Rosenstiel, Dirk Reichardt. 105-110 [doi]
- Interface Exploration for Reduced Power in Core-Based SystemsTony Givargis, Frank Vahid. 117-124 [doi]
- Instruction Encoding Techniques for Area Minimization of Instruction ROMTakanori Okuma, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar, Hiroto Yasuura. 125-130 [doi]
- Application of Instruction Analysis/Synthesis Tools to x86 s Functional Unit AllocationIng-Jer Huang, Ping-Huei Xie. 131-136 [doi]
- Memory Efficient Software Synthesis from Dataflow GraphWonyong Sung, Junedong Kim, Soonhoi Ha. 137-144 [doi]
- A Tool for Partitioning and Pipelined Scheduling of Hardware-Software SystemsKaram S. Chatha, Ranga Vemuri. 145-151 [doi]
- A Three-Step Approach to the Functional Partitioning of Large Behavioral ProcessesFrank Vahid. 152-157 [doi]
- Fine Grain Incremental Rescheduling Via Architectural RetimingSoha Hassoun. 158-163 [doi]