Abstract is missing.
- The Challenge of Testing VLSI in the 1980 sWilliam P. Thurston. 3
- A Unified Test Plan for LSI or VLSI ComponentsKent Lunneborg. 9-14
- BELLMACT-32 : A Testable 32 bit MicroprocessorWilliams Ludwell Harrison, Robert P. Davidson, R. L. Wadsack. 15-20
- Analytical Testing of Data Processing Sections of Integrated CPUsBernard Courtois. 21-30
- System to Optimize Test Quality and Efficiency for Memories and LSIRobert G. Dunn, A. Kwan, David P. Rodgers, D. Sandstrom, C. Sie. 31-37
- Importance of Asynchronous Refreshing in Memory TestingE. Kurzweil, L. Jambut. 38-43
- Paragons for Memory TestSteven Winegarden, Donald Pannell. 44-48
- Testing Repairable RAMs and Mostly Good MemoriesRobert C. Evans. 49-55
- An Approach to Memory Testing, Diagnostics and AnalysisJoan M. Morrissey, Ching-Hua Chow, Ronald C. Devries, C. Megivern. 56-67
- Electron-Beam Testing of VLSI Dyrnamic RAMsG. K. Lukianoff, J. S. Wolcott, Joan M. Morrissey. 68-78
- A Self-Test Method for Digital CircuitsM. T. M. Segers. 79-85
- Fault Diagnosis in an LSSD EnvironmentY. Arzoumanian, John A. Waicukauski. 86-88
- Designing Testable Synchronous LogicChung-Ho Chen. 89-94
- A Calculus of Testability Measure at the Functional LevelShigeru Takasaki, Masato Kawai, S. Funatsu, Akihiko Yamoda. 95-101
- VLSI Self-Testing Based on Syndrome TechniquesZeev Barzilai, Jacob Savir, George Markowsky, Merlin G. Smith. 102-109
- Hardware Test Pattern Generation for Built-In TestingWilfried Daehn, Joachim Mucha. 110-120
- An Enhanced Analog/Digital GPIB Based PCB Test SystemDave Peachey, Robert O Harold. 121-123
- In-Circuit Test Techniques Applied to Complex Digital AssembliesAldo Mastrocola. 124-131
- Automatic Testing of Speech Synthesis Integrated CircuitsDavid K. Oka, Bradford Robbins, William Bowhers. 132-139
- A CCD Imager Test SystemCharles Koehler. 140-142
- Analysis and Definition of Overall Timing Accuracy in VLSI Test SystemShigeru Sugamori, Kenji Yoshida, Hiromi Maruyama, Shinpei Kamata, Tsuneta Sudo. 143-153
- The PIN Module: A High Accuracy Concept in Very High Frequency Pin ElectronicsPaul Chang, Ed Richards, David Richter. 154-168
- A Correlation Study of Modern Techniques Applied to the Testing of Telecommunication CircuitsRichard Adams. 169-176
- A Working Approach to Volume CODEC TestingJohn C. Lundy. 177-185
- A High-Performance Integrated Analog/Digital Test and Characterization Test SystemR. A. Hum, D. L. Williams, J. W. Lamonde. 186-192
- Digital Signal Processing Considerations in Filter-Codec TestingFranc Brglez. 193-202
- The Self-Assist Test Approach to Embedded ArraysDouglas W. Westcott. 203-207
- Self-Testing by Polynomial DivisionDilip K. Bhavsar, Richard W. Heckelman. 208-216
- CMOS Is Most TestableMark W. Levi. 217-220
- Internal Diagnostics for Tektronix Graphics TerminalsWilliam R. Cook. 221-225
- Parametric Relationships for Self-Contained Test for Digital Avionics FunctionsSamuel Kitces, John E. Bauer. 226-230
- Completely Self-Checking Checkers in PLAsKyushik Son, Dhiraj K. Pradhan. 231-240
- Implications of Board Testing at SpeedGeoffrey J. Bunza. 241-243
- Dynamic Memory Array Card Burn-In and High Speed Functional Card TestingJohn J. Allard. 244-248
- High-Speed Functional Testing of Microprocessor-Based Circuit BoardsEric Sacher. 249-252
- Computer-Guided Probing TechniquesStephen Jochan, Norman Landis, Duke Monson. 253-270
- An 18-Bit Precision DC Measurement SystemRobert B. Craven, E. Rachel Morris. 271-289
- An NBS Calibration Service for A/D and D/A ConvertersT. Michael Souders, D. R. Flach. 290-303
- A System for Converter Testing Using Walsh Transform TechniquesE. A. Sloane. 304-311
- A New Technique for Testing Settling Time in a Production EnvironmentJ. Anson Whealler. 312-318
- Automated Measurement of 12 to 16-Bit ConvertersMatthew V. Mahoney. 319-330
- Applying Quality Curves for Economic Comparison of Alternative Test StrategiesKemon P. Taschioglou. 331-339
- Preparation of Product Test PlansG. W. Jacob. 340-347
- The Economics of the Memory Tester DecisionG. A. Perone, P. A. LaBerge. 348-367
- Hidden Cost Considerations in Long Term Use of ATE ProgramsJoseph A. Ruggieri. 368-369
- Documentation for Testability : The Supplier s Responsibility to the UserEugene R. Hnatek. 370-372
- Planning for Test of Custom IC DevicesMicahel R. Saleno. 373-376
- The Series/1 as a Test System Controller for System Verification and CalibrationDonald L. Wheater, Richard Soderman. 377-380
- Data Management for Large Memory Device CharacterizationRobert S. Broughton. 381-387
- IBM s VLSI Logic Test SystemR. N. Powell. 388-392
- A Method for Testing Subnanosecond ECLBeau R. Wilson Jr.. 393-401
- High-Volume Production Testing and Its Impact on the Development of Microprocessor Prototyping ToolsRobert M. Rolfe. 402-406
- Driving Forces Behind Field-Based System TestingJ. Thomas Zender. 407-410
- The IBM Maintenance DeviceJohn W. Marvill. 411-419
- Field System Test Strategies for the 1980 sCharles P. Frusterio. 420-424
- DIAL : An Automated ATE Service Support SystemGerald C. Goshaw. 425-432
- State Diagram Approach for Functional Testing of Control SectionChi-Chang Liaw, Stephen Y. H. Su, Yashwant K. Malaiya. 433-446
- Testing Functional Faults in Digital Systems Described by Register Transfer LanguageStephen Y. H. Su, Yu-I Hsieh. 447-457
- Microprocessor Modeling for Logic SimulationJames Y. O. Fong. 458-460
- Functional Level Test Generation for Complex Digital SystemsJacob A. Abraham. 461-462
- Functional Testing Folklore and FactPeter S. Bottorff. 463-466
- A Data Management System for Testing Memory DevicesC. P. Ancheta, J. C. Helland. 467-475
- A Test Analysis Program for Memory TestingNalin Shah, Hira Ranga. 476-483
- ANGEL : Algorithmic Pattern Generation SystemBrad Snoulten, John Peacock. 484-488
- A Three Mode Command Language for ATEArthur E. Downey. 489-496
- Fault Spectrum: An Analysis of System Level Test with Proposed SolutionsBruce G. MacAloney. 497-500
- Final Test of an LSI Populated System: A Pragmatic ApproachWilliam K. Jones. 501-507
- Today a Collection of Modules: Tomorrow a SystemD. C. Jessep Jr.. 508-514
- Factory Final Test SystemsJ. L. Saathoff. 515-520
- Single Testability Figure of MeritPredrag G. Kovijanic. 521-529
- Efficient Logic Verification and Test Validation for MOS LSI CircuitsKaoru Okazaki, Toshihiko Yahara. 530-535
- Functional-Level Test Generation for Stuck-Open Faults in CMOS VLSIYacoub M. El-Ziq, Richard J. Cloutier. 536-546
- VLSI : How Much Fault Coverage Is Enough ?R. L. Wadsack. 547-554
- DORA : A System of CAD Post-Processors Providing Test Programs and Automatic Diagnostics Data for Digital Device and Board ManufactureR. W. Allen, C. D. Chen, M. M. Ervin-Willis, K. R. Rahlfs, R. F. Thulloss, S. L. Wu. 555-560
- Test Generation for Highly Sequential Scan-Testable Circuits Through Logic TransformationM. Ray Mercer, Vishwani D. Agrawal, Carlos M. Roman. 561-565