Table of Contents

• DeltaI vs. DeltaY : A Quantitative Analysis of the Trade-offs Between Higher Capital Investment and Higher Yield in PCB TestingMark A. Myers. 8-19
• An Analysis of the Economics of Self TestPrab Varma, Anthony P. Ambler, Keith Baker. 20-30
• Test Logic Economic Considerations in a Commercial VLSI Chip EnvironmentJ. S. Pittman, W. C. Bruce. 31-39
• Low Cost Testers : Are They Really Low Cost ?Gordon H. Bowers Jr, B. G. Pratt. 40-51
• An Analysis of the Multiple Fault Detection Capabilities of Single Stuck-at Fault Test SetsJoseph L. A. Hughes, Edward J. McCluskey. 52-58
• Test Generation for FET Switching CircuitsJ. Paul Roth, Vojin G. Oklobdzija, John F. Beetem. 59-62
• Automatic Test Pattern Generation for Asynchronous NetworksBrian J. Heard, Ramu N. Sheshadri, Ronald B. David, Arvid G. Sammuli. 63-69
• Test Generation for MOS CircuitsHarry H. Chen, Robert G. Mathews, John A. Newkirk. 70-79
• ATWIG, An Automatic Test Pattern Generator with Inherent GuidanceErwin Trischler. 80-87
• Logic Design Verification Using Automated Test GenerationTohru Sasaki, Shunichi Kato, Nobuyoshi Nomizu, Hidetoshi Tanaka. 88-95
• High Resolution, High Linearity Interpolating A/D ConverterAlexander Holland. 96-104
• Time Specification Conformance of VLSI Test Systems O5William B. Abbott IV. 105-112
• A New Timing Calibration Method for High Speed Memory TestY. Nishimura, M. Hamada, Y. Hayasaka. 113-117
• Software Convergence of Test Program ParametersAnthony J. Burke. 118-122
• 21-Bit Precision and High-Speed DC Measurement SystemTadaaki Satoh, Akira Takagi, Masami Kita, Katsuhiko Shirakawa, Shimpei Takeshita. 123-133
• Can We Eliminate Fault Escape in Self-Testing by Polynomial Division (Signature Analysis) ?Dilip K. Bhavsar, Balakrishnan Krishnamurthy. 134-139
• Higher Certainty of Error Coverage by Output Data ModificationYervant Zorian, Vinod K. Agarwal. 140-147
• Self-Testing of Embedded RAMsZuhi Sun, Laung-Terng Wang. 148-156
• Random Testing for Stuck-At Storage Cells in an Embedded MemoryWilliam H. McAnney, Paul H. Bardell, V. P. Gupta. 157-166
• Sufficient Testing In A Self-Testing EnvironmentTom W. Williams. 167-173
• On Coosing a Hardware Descriptive Language for Digital Systems Testing/VerificationBulent I. Dervisoglu. 184-187
• A Method for Test System Diagnostics Based on the Principles of Artificial IntelligenceA. Jesse Wilkinson. 188-195
• An Expert System for VLSI Tester DiagnosticsRobert Mullis. 196-199
• Artificial Intelligence and TestingGordon D. Robinson. 200-205
• Adapting CAE Design Information for In-Circuit Test GenerationBrian C. Crosby. 206-211
• Information and Material Flow Within a Production Test CellGraeme R. Kinsey. 212-217
• Comprehensive Fault Model and Testing of CMOS CircuitsDharma P. Agrawal, Sami A. Al-Arian. 218-223
• Methodology for and Results from the Use of a Hardware Logic Simulation Engine for Fault SimulationLeslie Turner Smith, Roy R. Rezac. 224-228
• Using Simulation in the Design Process - A Case StudyArthur Babitz, Kurt Lender. 229-236
• The Coverage Problem for Random TestingYashwant K. Malaiya, Shoubao Yang. 237-245
• Functional Test Pattern Generation for Integrated CircuitsRamin Khorram. 246-249
• CVT-FERT : Automatic Generator of Analytical Faults at Register Transfer Level from Electrical and Topological DescriptionsM. Melgara, M. Paolini, R. Roncella, S. Morpurgo. 250-257
• Instant On Semiconductor Memories: Reality or MythFrederick G. Hall, Robert G. Hillman, John M. Bednarczyk. 258-262
• Access Time Evaluation of Fast Static MOS MemoriesE. Kurzweil, L. Jambut. 263-270
• Built-in Testing of Memory Using On-chip Compact Testing SchemeKozo Kinoshita, Kewal K. Saluja. 271-281
• High Speed Redundancy ProcessorGene P. Bosse. 282-286
• A Fault-Driven, Comprehensive Redundancy Algorithm for Repair of Dynamic RAMsJohn R. Day. 287-293
• Testing a 317K bit High Speed Video Memory with a VSLI Test SystemF. Pool, J. Hop, J. P. L. Lagerberg, C. Da Costa. 294-301
• Parallel Pseudorandom Sequences for Built-In TestPaul H. Bardell, William H. McAnney. 302-308
• Built-In Test for CMOS CircuitsCorot W. Starke. 309-314
• Design of Test Pattern Generators for Built-In TestRamaswami Dandapani, Janak H. Patel, Jacob A. Abraham. 315-319
• Pseudo-Exhaustive Testing of Sequential Machines Using Signature AnalysisSyed Zahoor Hassan, Edward J. McCluskey. 320-326
• A Built-In Test Methodology for VLSI Data PathsCharles R. Kime, H. H. Kwan, J. K. Lemke, Gerald B. Williams. 327-337
• Impact of Mixed-Mode Self Test on Life Cycle Cost of VLSI Based DesignYacoub M. El-Ziq, Hamid H. Butt. 338-349
• Exploratory Data Analysis Makes Testing More Valuable for Semiconductor ManufacturingDean Bandes. 350-358
• A Flexible Database System and Its Application in VLSI Process DevelopmentKou Wada, Satoshi Tazawa, Katsutoshi Kubota. 359-366
• Logic Device Characterization Using Computer-Aided Test and AnalysisRobert W. Atherton, Leonard Ekkelkamp, Chuck Schmitz. 367-383
• MOS Gate Oxide Quality Control and Reliability Assessment by Voltage RampingSushil K. Malik, E. F. Chace. 384-389
• Systematic Characterization of Physical Defects for Fault Analysis of MOS IC CellsWojciech Maly, F. Joel Ferguson, John Paul Shen. 390-399
• Measuring Thermal Rises Due to Digital Device OverdrivingG. Siva Bushanam, Vance R. Harwood, Philip N. King, Roger D. Story. 400-425
• Transfer Function Estimation Part I : Theoretical and Practical ConsiderationsE. A. Sloane. 426-439
• Transfer Function Estimation Part II : Some Experimental ResultsJames F. Campbell Jr.. 440-446
• CODEC Testing Using Synchronized Analog and Digital SignalsDouglas K. Shirachi. 447-454
• In-Circuit Analog Component Testing at High FrequenciesTerence Lee. 455-461
• The Future is Now: Extending CAE into Test of Custom VLSIRobert S. Broughton, Michael G. Brashler. 462-465
• IBM s Cost Performance Array Tester Architecture for the 80 sDonald L. Wheater. 466-470
• Compaction Technique Universal Pin ElectronicsPhilip C. Jackson, Gregory de Mare, Albert Esser. 471-481
• PBX System Test: Fast Functional Testing Without System AssemblyR. F. Voitus. 482-488
• Component Level Fault-Isolation Techniques in a Systems Test EnvironmentEric Sacher. 489-492
• The Role of the Engineering Work Station in Test Program DevelopmentTodd Westerhoff, Andre DiMino. 493-496
• An Information Processing Software System for ATEJames T. Healy. 497-505
• Disc Drive Testing InstrumentM. V. Limaye, K. Rajanikanth, H. S. Jamadagni. 506-512
• An Automated Test of a Disk Product Power System Independent of the Primary Function of the MachineGerard FitzPatrick, David F. Peach, Richard P. Cushman. 513-517
• Monitored Burn-In (A Case Study for In-Situ Testing and Reliability Studies)Michael J. Campbell. 518-523
• A Rational Basis for Setting Burn-In Yield CriteriaA. P. van den Heuvel, N. F. Khory. 524-530
• Thoughts on VLSI Burn-inEugene R. Hnatek. 531-535
• An Automated Laser Prober to Determine VLSI Internal Node Logic StatesFrancois J. Henley. 536-542
• Electron Beam Prober for LSI Testing with 100ps Time ResolutionY. Goto, K. Ozaki, T. Ishizuka, A. Ito, Y. Furukawa, T. Inagaki. 543-549
• Automated Electron Beam Testing of VLSI CircuitsP. Küollensperger, A. Krupp, M. Sturm, R. Weyl, F. Widulla, F. Wolfgang. 550-557
• Automatic Visual Testing: A New, Comprehensive Element of Cost-Effective PCB Testing StrategiesStephen P. Denker, Judy Cobb. 558-563
• Using a Synchronous High-Speed Sensor System to Diagnose Microprocessor BoardsStephen R. Teta. 564-571
• In-Circuit Testability Factors: Shoot With a RifleDouglas W. Raymond. 572-580
• Conquering Testability Problems by Combining In-Circuit and Functional TechniquesStephen Caplow. 581-588
• Channel Card Architecture for Multimode Board Test SystemsMark S. Hoffman, Joseph F. Wrinn. 589-597
• Test Strategy for a 32-Bit Microprocessor Module with Memory ManagementRamaswamy Balasubramaniam, Peretz Feder. 598-605
• Advanced Test System Software Architecture Blends High Speed with User FriendlinessTerence King. 606-613
• Behavioral Simulation of VLSI Test System Aids Debugging and Analysis of Test ProgramsS. Daniel Lee, Tom Middleton. 614-620
• Software Verification TechniquesVin Ratford, Mike Gill. 621-626
• A Real-time Executive for a Distributed Processing SystemG. Heretz, L. T. Matlock. 627-629
• Multi-Port Test Data Supply SystemR. E. Kizis, G. C. Wickham. 630-635
• C : An Important Tool for Test Software DevelopmentSteven L. Watkins, Kenny Liu, Mitchell Schrift, Robert Patrie. 636-641
• CMOS VLSI Challenges to TestKenneth D. Mandl. 642-648
• A Design for Machines with Built-In Tolerance to Soft ErrorsYvon Savaria, Vinod K. Agarwal, Nicholas C. Rumin, Jeremiah F. Hayes. 649-659
• Functional Test Generation of Digital LSI/VLSI Systems Using Machine Symbolic Execution TechniqueTonysheng Lin, Stephen Y. H. Su. 660-668
• Fault Simulation at the Architectural LevelScott Davidson. 669-679
• CADOC : A System for Computer Aided Functional TestCatherine Bellon, Gabriele Saucier. 680-689
• Testability Analysis of MOS VLSI CircuitsDavid M. Singer. 690-696
• Correlating Testability with Fault DetectionBill Underwood, M. Ray Mercer. 697-704
• Applications of Testability Analysis: From ATPG to Critical Delay Path TracingFranc Brglez, Philip Pownall, Robert Hum. 705-712
• Improve Yield and Quality Through Testability Analysis of VLSI CircuitsDavid M. Wu, Charles E. Radke, C. C. Beh. 713-717
• Will Testability Analysis Replace Fault Simulation ?Vishwani D. Agrawal. 718-718
• A Vote in Favor of Fault SimulationJ. Lawrence Carter. 719-721
• Testability Analysis will not Replace Fault SimulationPrabhakar Goel. 722-724
• Testability Analysis: What Role Should it Play in IC Design ?F. C. Wang. 725-727
• The Importance of Fault SimulationRobert Willoner. 728-729
• Automating Functional Programming for Micro-Based BoardsSteve Broyles. 730-736
• A Multimode Programming Strategy for VLSI BoardsPeter Hansen. 737-742
• PAL and Logic Array In-Circuit Testing ConsiderationsRobert G. Jacobson. 743-746
• Design Verification, Product Characterization and Production Testing of Hybrids and Printed Circuit Cards Using High-Sensitivity Thermography SystemsHerb Boulton. 747-751
• The Need for Real-Time Intelligence When Testing VLSIJeff Angwin, Paul Drake, Glenn Reader. 752-761
• TPG2 : An Automatic Test Program Generator for Custom ICsD. P. Ahrens, P. J. Bednarczyk, D. L. Denburg, R. M. Robertson. 762-767
• Device Models : A New Methodology for a Perennial ProblemDavid Giles, Gregory A. Maston. 768-772
• Knowledge Representation in an In-Circuit Test Program GeneratorEdward S. Hirgelt. 773-777
• Problems Encountered in Developing VLSI Test Programs for COT (A Practical Outlook)Beau R. Wilson Jr., Eugene R. Hnatek. 778-788
• Processing of Test Data between Design and TestingA. J. Kombol. 789-793
• Functional Characterization of MicroprocessorsAxel Hunger, Axel Gaertner. 794-803
• Hardware and Software Tools for Microprocessor Functional TestC. Bellon, Raoul Velazco. 804-820
• Testability Features of the MC68020John Kuban, John Salick. 821-826
• Parallel Testing of Random Logic LSIsNobuo Arai, Yoshio Yamanaka. 827-833
• Scan Path in CMOS Semicustom LSI Chips ?M. Gerner, H. Nertinger. 834-841
• A Technique for Making Asynchronous Sequential Circuits Readily TestableAlfred K. Susskind. 842-846
• Logical Modeling of Physical Failures and Their Inherent Syndrome Testability in MOS LSI/VLSI NetworksBhargab B. Bhattacharya, Bidyut Gupta. 847-855
• Lower Overhead Design for Testability of Programmable Logic ArraysSaied Bozorgui-Nesbat, Edward J. McCluskey. 856-865
• On CMOS Totally Self-Checking CircuitsSridhar R. Manthani, Sudhakar M. Reddy. 866-877
• A Totally Universal Reset, Initialization (and) Nodal Observation CircuitJon Turino. 878-884