Table of Contents

• A design flow to maximize yield/area of physical devices via redundancyMohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta. 1-10 [doi]
• Improved volume diagnosis throughput using dynamic design partitioningXiaoxin Fan, Huaxing Tang, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Brady Benware. 1-10 [doi]
• On-chip diagnosis for early-life and wear-out failuresMatthew Beckler, R. D. (Shawn) Blanton. 1-10 [doi]
• Impact of Radial defect clustering on 3D stacked IC yield from wafer to wafer stackingEshan Singh. 1-7 [doi]
• On pinpoint capture power management in at-speed scan test generationXiaoqing Wen, Y. Nishida, Kohei Miyase, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang. 1-10 [doi]
• DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacksSergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen. 1-10 [doi]
• Hybrid selector for high-X scan compressionPeter Wohl, John A. Waicukauski, Frederic Neuveux, J. E. Colburn. 1-10 [doi]
• How are failure modes, defect types and test methods changing for 32nm/28nm technologies and beyond?Phil Nigh. 1-4 [doi]
• Spatial estimation of wafer measurement parameters using Gaussian process modelsNathan Kupp, Ke Huang, John M. Carulli Jr., Yiorgos Makris. 1-8 [doi]
• Algorithm for dramatically improved efficiency in ADC linearity testZhongjun Yu, Degang Chen. 1-10 [doi]
• BS 1149.1 extensions for an online interconnect fault detection and recoverySomayeh Sadeghi Kohan, Majid Namaki-Shoushtari, Fatemeh Javaheri, Zainalabedin Navabi. 1-9 [doi]
• A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validationYuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue. 1-8 [doi]
• DART: Dependable VLSI test architecture and its implementationYasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura. 1-10 [doi]
• Multi-gigahertz arbitrary timing generator and data pattern serializer/formatterDavid C. Keezer, Te-Hui Chen, Carl Edward Gray, Hyun Woo Choi, Sungyeol Kim, Seongkwan Lee, Hosun Yoo. 1-11 [doi]
• Modeling, verification and pattern generation for reconfigurable scan networksRafal Baranowski, Michael A. Kochte, Hans-Joachim Wunderlich. 1-9 [doi]
• A built-in self-test scheme for 3D RAMsYun-Chao You, Che-Wei Chou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu. 1-9 [doi]
• Low cost high-speed test data acquisition: Accurate period estimation driven signal reconstruction using incoherent subsamplingThomas Moon, Hyun Woo Choi, Abhijit Chatterjee. 1-9 [doi]
• Making predictive analog/RF alternate test strategy independent of training set sizeHaithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Olivier Potin, Michel Renovell. 1-9 [doi]
• Driver sharing challenges for DDR4 high-volume testing with ATEJose Moreira, Marc Moessinger, Koji Sasaki, Takayuki Nakamura. 1-10 [doi]
• Design validation of RTL circuits using evolutionary swarm intelligenceMin Li, Kelson Gent, Michael S. Hsiao. 1-8 [doi]
• FPGA-based synthetic instrumentation for board testIgor Aleksejev, Artur Jutman, Sergei Devadze, Sergei Odintsov, Thomas Wenzel. 1-10 [doi]
• Event-driven framework for configurable runtime system observability for SOC designsJong Chul Lee, Faycel Kouteib, Roman Lysecky. 1-10 [doi]
• Board assisted-BIST: Long and short term solutions for testpoint erosion - Reaching into the DFx toolboxZoe Conroy, James J. Grealish, Harrison Miles, Anthony J. Suto, Alfred L. Crouch, Skip Meyers. 1-10 [doi]
• RNA: Advanced phase tracking method for digital waveform reconstructionTakashi Ito, Hideo Okawara, Jinlei Liu. 1-9 [doi]
• Functional test of small-delay faults using SAT and Craig interpolationMatthias Sauer, Stefan Kupferschmid, Alexander Czutro, Ilia Polian, Sudhakar M. Reddy, Bernd Becker. 1-8 [doi]
• A digital method for phase noise measurementAllan Ecker, Kenneth Blakkan, Mani Soma. 1-10 [doi]
• Testing high-frequency and low-power designs: Do the standard rules and tools apply?Scott Davidson. 1 [doi]
• Experiences with non-intrusive sensors for RF built-in testLouay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Christophe Kelma. 1-8 [doi]
• Screening customer returns with multivariate test analysisNik Sumikawa, Jeff Tikkanen, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir. 1-10 [doi]
• Are industrial test problems real problems? I thought research has resolved them all!Xinli Gu. 1 [doi]
• Systematic defect screening in controlled experiments using volume diagnosisB. Seshadri, P. Gupta, Y. T. Lin, B. Cory. 1-7 [doi]
• Are the IC guys helping or hindering board test?Zoe Conroy. 1 [doi]
• Real-time testing method for 16 Gbps 4-PAM signal interfaceMasahiro Ishida, Kiyotaka Ichiyama, Daisuke Watanabe, Masayuki Kawabata, Toshiyuki Okayasu. 1-10 [doi]
• Adaptive test selection for post-silicon timing validation: A data mining approachMing Gao, Peter Lisherness, Kwang-Ting (Tim) Cheng. 1-7 [doi]
• The DFT challenges and solutions for the ARM® Cortex™-A15 MicroprocessorTeresa L. McLaurin, Frank Frederick, Rich Slobodnik. 1-9 [doi]
• In-system constrained-random stimuli generation for post-silicon validationAdam B. Kinsman, Ho Fai Ko, Nicola Nicolici. 1-10 [doi]
• Methodology for fault grading high speed I/O interfaces used in complex Graphics Processing UnitA. Khare, P. Kishore, S. Reddy, K. Rajan, A. Sanghani. 1-8 [doi]
• Low power test application with selective compaction in VLSI designsDariusz Czysz, Janusz Rajski, Jerzy Tyszer. 1-10 [doi]
• Functional test content optimization for peak-power validation - An experimental studyVinayak Kamath, Wen Chen, Nik Sumikawa, Li-C. Wang. 1-10 [doi]
• Vulnerability-based Interleaving for Multi-Bit Upset (MBU) protection in modern microprocessorsMichail Maniatakos, Maria K. Michael, Yiorgos Makris. 1-8 [doi]
• Power integrity control of ATE for emulating power supply fluctuations on customer environmentMasahiro Ishida, Toru Nakura, Toshiyuki Kikkawa, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada. 1-10 [doi]
• An experiment of burn-in time reduction based on parametric test analysisNik Sumikawa, Li-C. Wang, Magdy S. Abadir. 1-10 [doi]
• On-die instrumentation to solve challenges for 28nm, 28Gbps timing variability and stressingWeichi Ding, Mingde Pan, Wilson Wong, Daniel Chow, Mike Peng Li, Sergey Shumarayev. 1-7 [doi]
• Root cause identification of an hard-to-find on-chip power supply coupling failFranco Stellari, Thomas Cowell, Peilin Song, Michael Sorna, Zeynep Toprak Deniz, John F. Bulzacchelli, Nandita A. Mitra. 1-7 [doi]
• Automated system level functional test program generation on ATE from EDA using Functional Test AbstractionMotoo Ueda, Shinichi Ishikawa, Masaru Goishi, Satoru Kitagawa, Hiroshi Araki, Shuichi Inage. 1-7 [doi]
• Calibration of a flexible high precision Power-On Reset during production testGerald Hilber, Dominik Gruber, Michael Sams, Timm Ostermann. 1-7 [doi]
• DC temperature measurements for power gain monitoring in RF power amplifiersJosep Altet, Diego Mateo, Didac Gómez, Xavier Perpiñà, Miquel Vellvehí, Xavier Jordà. 1-8 [doi]
• Radic: A standard-cell-based sensor for on-chip aging and flip-flop metastability measurementsXiaoxiao Wang, Dat Tran, Saji George, LeRoy Winemberg, Nisar Ahmed, Steve Palosh, Allan Dobin, Mohammad Tehranipoor. 1-9 [doi]
• On modeling faults in FinFET logic circuitsYuxi Liu, Qiang Xu. 1-9 [doi]
• Testing strategies for a 9T sub-threshold SRAMHao-Yu Yang, Chen-Wei Lin, Hung-Hsin Chen, Mango Chia-Tso Chao, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang. 1-10 [doi]
• A memory yield improvement scheme combining built-in self-repair and error correction codesTze-Hsin Wu, Po-Yuan Chen, Mincent Lee, Bin-Yen Lin, Cheng-Wen Wu, Chen-Hung Tien, Hung-Chih Lin, Hao Chen, Ching-Nen Peng, Min-Jer Wang. 1-9 [doi]
• Low-cost wideband periodic signal reconstruction using incoherent undersampling and back-end cost optimizationNicholas Tzou, Debesh Bhatta, Sen-Wen Hsiao, Hyun Woo Choi, Abhijit Chatterjee. 1-10 [doi]
• An ATE architecture for implementing very high efficiency concurrent testingTakahiro Nakajima, Takeshi Yaguchi, Hajime Sugimura. 1-10 [doi]
• Capacitive sensing testability in complex memory devicesKenneth P. Parker. 1-6 [doi]
• A dynamic programming solution for optimizing test delivery in multicore SOCsMukesh Agrawal, Michael Richter, Krishnendu Chakrabarty. 1-10 [doi]
• "Managing process variance in analog designs"Eugene R. Atwood. 1 [doi]
• Improving test compression by retaining non-pivot free variables in sequential linear decompressorsSreenivaas S. Muthyala, Nur A. Touba. 1-7 [doi]
• Scan test of die logic in 3D ICs using TSV probingBrandon Noia, Shreepad Panth, Krishnendu Chakrabarty, Sung Kyu Lim. 1-8 [doi]
• A unified method for parametric fault characterization of post-bond TSVsYu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter. 1-10 [doi]
• On efficient silicon debug with flexible trace interconnection fabricXiao Liu, Qiang Xu. 1-9 [doi]
• Test/ATE vision 2020 - Entrepreneurship in test CEO panelKen Lanier. 1 [doi]
• Cell-aware Production test results from a 32-nm notebook processorFriedrich Hapke, M. Reese, Jason Rivers, A. Over, V. Ravikumar, Wilfried Redemund, Andreas Glowatz, Jürgen Schlöffel, Janusz Rajski. 1-9 [doi]
• Packet-based JTAG for remote testingMichele Portolan. 1-6 [doi]
• Integrated optimization of semiconductor manufacturing: A machine learning approachNathan Kupp, Yiorgos Makris. 1-10 [doi]
• Low power programmable PRPG with enhanced fault coverage gradientJedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski. 1-9 [doi]
• FALCON: Rapid statistical fault coverage estimation for complex designsShahrzad Mirkhani, Jacob A. Abraham, Toai Vo, Hong Shin Jun, Bill Eklow. 1-10 [doi]
• Low-power SRAMs power mode control logic: Failure analysis and test solutionsLeonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine. 1-10 [doi]
• Higher than Nyquist test waveform synthesis and digital phase noise injection using time-interleaved mixed-mode data convertersXian Wang, Hyun Woo Choi, Thomas Moon, Nicholas Tzou, Abhijit Chatterjee. 1-10 [doi]
• A frequency measurement BIST implementation targeting gigahertz applicationMatthieu Dubois, Emeric de Foucauld, Christopher Mounet, Serigne Dia, Cedric Mayor. 1-8 [doi]
• 8Gbps CMOS pin electronics hardware macro with simultaneous bi-directional capabilityShoji Kojima, Yasuyuki Arai, Tasuku Fujibe, Tsuyoshi Ataka, Atsushi Ono, Ken-ichi Sawada, Daisuke Watanabe. 1-9 [doi]