Table of Contents

• Low power low voltage wide frequency resonant clock and data circuits for power reductionsIgnatius Bezzam, Shoba Krishnan, Tezaswi Raja, Chakravarthy Mathiazhagan. 1-4 [doi]
• A power optimized decimator for sigma-delta data convertersDionisio de Carvalho, João Navarro. 1-4 [doi]
• Mixed-mode biquad filter employing single active elementFirat Kaçar, Ayten Kuntman, Hakan Kuntman. 1-4 [doi]
• Sinusoidal signal generation for mixed-signal BIST using a harmonic-cancellation techniqueManuel J. Barragan, Gildas Léger, Diego Vázquez, Adoración Rueda. 1-4 [doi]
• ACO approach in static routing for network-on-chips with 3D mesh topologyLuneque Silva Junior, Nadia Nedjah, Luiza de Macedo Mourelle. 1-4 [doi]
• Inductor characterization in RF LC-VCOsRicardo Doldán, Antonio J. Ginés, Adoración Rueda. 1-4 [doi]
• Implementation and evaluation of an adaptive method for reduce the respiration influence on Heart Rate VariabilityRaymundo Cassani, Juan-Carlos Sanchez, Raul Martinez. 1-4 [doi]
• A 0.18µm CMOS switched-capacitor amplifier using current-starving inverter based op-amp for low-power biosensor applicationsRyan Selby, Kern Tucker, William Wilson, Tom Chen 0001. 1-4 [doi]
• A frequency to voltage converter based on an accurate pulse width modulator for frequency locked loopsCagri Gurleyuk, Burcin Pak, Devrim Yilmaz Aksin. 1-4 [doi]
• High-level design and synthesis of a MPEG-4 AAC IMDCT moduleRenato Coral Sampaio, Pedro de Azevedo Berger, Ricardo P. Jacobi. 1-4 [doi]
• Signal integrity design of TSV and interposer in 3D-ICJonghyun Cho, Joungho Kim. 1-4 [doi]
• Efficient hardware architecture for embedded radionuclide identificationMarcos Santana Farias, Nadia Nedjah, Luiza de Macedo Mourelle. 1-4 [doi]
• A low-power, offset-corrected potentiostat for chemical imaging applicationsKern Tucker, Tom Chen. 1-4 [doi]
• A scalable parallel reconfigurable hardware architecture for DNA matchingEdgar J. Garcia Neto Segundo, Nadia Nedjah, Luiza de Macedo Mourelle. 1-4 [doi]
• A 60 GHz up-conversion mixer using asymmetric layout with -41.1 dBc LO leakageYuki Tsukui, Kenichi Okada, Akira Matsuzawa. 1-4 [doi]
• Pedestrian dead reckoning with attitude estimation using a fuzzy logic tuned adaptive kalman filterMariana Natalia Ibarra-Bonilla, Ponciano Jorge Escamilla-Ambrosio, Juan Manuel Ramírez-Cortés, Carlos Vianchada. 1-4 [doi]
• A configurable analog buffer dedicated to a wafer-scale prototyping platform of electronic systemsNicolas Laflamme-Mayer, Mohamad Sawan, Yves Blaquière. 1-4 [doi]
• Fully integrated single-inductor multiple-output (SIMO) DC-DC converter in CMOS 65 nm technologyAngel J. Soto, Esteban O. Lindstrom, Alejandro R. Oliva, Pablo Sergio Mandolesi, Fortunato Carlos Dualibe. 1-4 [doi]
• Configurable frequency agile filter application of balanced differential pair based CCCII circuit in 28nm processEmrah Armagan, Hakan Kuntman. 1-4 [doi]
• A family of memristive transfer functions of negative feedback nullor-based amplifiersCarlos Hernández-Mejía, Arturo Sarmiento-Reyes, Hector Vazquez-Leal. 1-4 [doi]
• A new delay distribution model to take long-term degradation into accountShuji Tsukiyama, Masahiro Fukui, Takashi Kambe. 1-4 [doi]
• Designing MEMS pressure sensors with integrated circuitry on silicon for miscellaneous applicationsWolfgang Schreiber-Prillwitz, Reinhart Job. 1-4 [doi]
• Program for symbolic analysis of mechatronic systemsZdenek Kolka, Jaroslav Kalous, Viera Biolková, Dalibor Biolek. 1-4 [doi]
• Non-stationary statistical simulation of blind-oversampling CDR circuitsZdenek Kolka, Michal Kubícek, Viera Biolková, Dalibor Biolek. 1-4 [doi]
• An efficient data fusion architecture for infrared and ultrasonic sensors, using FPGAMilton E. Conde, Sérgio Cruz, Daniel M. Muñoz, Carlos H. Llanos, Eugenio L. F. Fortaleza. 1-4 [doi]
• nd derivative Gaussian IRUWB transmitter module using n/p-latches as PDs in CMOS technologyLuiz Carlos Moreira, Jose Fontebasso Neto, Wilhelmus A. M. Van Noije, Emmanuel Torres-Rios. 1-4 [doi]
• Closed form design of nearly equiripple low-pass FIR filtersPavel Zahradnik, Boris Simák, Miroslav Vlcek. 1-4 [doi]
• Fast floorplanning with placement constraintsShantesh Pinge, Rajeev K. Nain, Malgorzata Chrzanowska-Jeske. 1-4 [doi]
• On fault classification in rotating machines using fourier domain features and neural networksAmaro A. de Lima, Thiago de M. Prego, Sergio L. Netto, Eduardo A. B. da Silva, Ricardo H. R. Gutierrez, Ulisses A. Monteiro, Antonio C. R. Troyman, Francisco J. da C. Silveira, Luiz Vaz. 1-4 [doi]
• A dual core low power microcontroller with openMSP430 architecture for high reliability lockstep applications using a 180 nm high voltage technology nodeSantiago Sondon, Pablo Sergio Mandolesi, Favio R. Masson, Pedro Julián, Felix Palumbo. 1-4 [doi]
• Vector analysis of a four-phase induction machineJulio Viola, Flavio Quizhpi, Gustavo Parra. 1-4 [doi]
• Optimization of 65nm CMOS passive devices to design a 16 dBm-Psat 60 GHz power amplifierSofiane Aloui, Bernardo Leite, Nejdat Demirel, Robert Plana, Didier Belot, Eric Kerherve. 1-4 [doi]
• Reducing the Hamming distance of encoded FFT twiddle factors using improved heuristic algorithmsAngelo Goncalves da Luz, Eduardo A. C. da Costa, Sidinei Ghissoni. 1-4 [doi]
• Behavioral modeling of continuous-time ΣΔ modulators in matlab/simulinkPaulo César C. de Aguirre, Vinicius Camargo, Hamilton Klimach, Altamiro Amadeu Susin, Cesar Prior. 1-4 [doi]
• Hardware realization of a lightweight 2D cellular automata-based cipher for image encryptionCésar Torres-Huitzil. 1-4 [doi]
• A motion detection pixel system using an inductorless UWB transmitter on standard 0.35µm/CMOS technologyMarcelo Macchi da Silva, Jose Fontebasso Neto, Luiz Carlos Moreira, Jacobus W. Swart. 1-4 [doi]
• A strategy for mapping reconfigurable cores in NoCsJonas Gomes Filho, Marius Strum, Wang Jiang Chau. 1-4 [doi]
• Narrow-band FIR filter setsPavel Zahradnik, Boris Simák, Miroslav Vlcek. 1-4 [doi]
• ASIC implementation of a modified QR decomposition for tree search based MIMO detectionChristina Gimmler-Dumont, Philipp Schläfer, Norbert Wehn. 1-4 [doi]
• An efficient CMOS configurable Bias Current Generator with wide dynamic rangeDavid Cordova, Eric E. Fabris, Renato Campana V.. 1-4 [doi]
• Systematic configuration of coarsely discretized 3D EM solvers for reliable and fast simulation of high-frequency planar structuresJosé Ernesto Rayas-Sánchez, Zabdiel Brito-Brito, Juan C. Cervantes-González, Carlos A. Lopez. 1-4 [doi]
• A current-starved inverter-based differential amplifier design for ultra-low power applicationsWilliam Wilson, Tom Chen 0001, Ryan Selby. 1-4 [doi]
• Symbolic nodal analysis of fully-differential analog circuitsCarlos Sánchez-López, Rocío Ochoa-Montiel, A. Ruiz-Pastor, B. M. Gonzalez-Contreras. 1-4 [doi]
• Very-low-tranconductance CMOS amplifier using multi-tanh bulk-driven input stage with gate-controlled assymetry for Gm-C applicationsÓscar Robles, Fernando Baruqui. 1-4 [doi]
• Electrostatic generators for vibrational energy harvestingAntônio Carlos M. de Queiroz. 1-4 [doi]
• A programmable charge pump voltage converter for implantable medical devices in a HV technologyJoel Gak, Matías R. Miguez, Alfredo Arnaud. 1-4 [doi]
• A biopotential amplifier with improved common mode gainReza Abdullah, Edgar Sánchez-Sinencio. 1-4 [doi]
• A fast hardware-friendly motion estimation algorithm and its VLSI design for real time ultra high definition applicationsGustavo Sanchez, Marcelo Schiavon Porto, Luciano Agostini. 1-4 [doi]
• Design of NCL gates with the ASCEnD flowMatheus T. Moreira, Carlos Henrique Menezes Oliveira, Ricardo C. Porto, Ney Laert Vilar Calazans. 1-4 [doi]
• Analysis of a broadband beamformer based on trapezoidal filters and nested arraysIman Moazzen, Panajotis Agathoklis. 1-4 [doi]
• Realization of 4D lattice structured digital filtersM. T. Kousoulis, G. E. Antoniou. 1-4 [doi]
• A system clock precision frequency to code converter for low power supply dependence ROICRaul Aragonés, Joan Oliver, Carles Ferrer 0001. 1-4 [doi]
• Design of locally-clocked asynchronous finite state machines using synchronous CAD toolsDuarte Lopes de Oliveira, Diego Bompean, Tiago S. Curtinhas, Lester de Abreu Faria. 1-4 [doi]
• Accuracy vs simulation speed trade-off enhancements in the generation of chaotic attractorsCarlos Sánchez-López, Jorge Mendoza-Lopez, Carlos Muñiz-Montero, Luis Abraham Sánchez-Gaspariano, Jesús M. Muñoz-Pacheco. 1-4 [doi]
• A mesh-based method for wavelet video coding using edge-detection in low frequency subbandMiok Kim, Nam Ling, John D. Ralston, Li Song. 1-4 [doi]
• Development of a stereo vision measurement architecture for an underwater robotCamilo Sánchez-Ferreira, Jones Yudi Mori, Carlos H. Llanos, Eugenio Fortaleza. 1-4 [doi]
• Design of a massively parallel computing architecture for dense matrix multiplicationWilson Jose, Ana Rita Silva, Mário P. Véstias, Horácio C. Neto. 1-4 [doi]
• An application of the empirical mode decomposition to brain magnetic resonance images classificationSalim Lahmiri, Mounir Boukadoum. 1-4 [doi]
• A design technique for distributed dual-band bandpass filtersThiago P. R. Goes, Robson Nunes de Lima, Luciana Martinez, Fernando Rangel de Sousa. 1-4 [doi]
• Low power low noise bio-amplifier with adjustable gain for digital bio-signals acquisition systemsOdilon O. Dutra, Tales C. Pimenta. 1-4 [doi]
• Fixed-point adaptive filter architecture for the harmonics power line interference cancellingGustavo Seibel, Fabio Itturriet, Eduardo Costa 0001, Sérgio Almeida 0001. 1-4 [doi]
• Parallel GPU-based implementation of high dimension Particle Swarm OptimizationsRogério M. Calazan, Nadia Nedjah, Luiza de Macedo Mourelle. 1-4 [doi]
• Design of a multiband full-rate ultra-wideband receiver in FPGAMário P. Véstias, Horácio C. Neto, Helena Sarmento. 1-4 [doi]
• Efficient online estimation of electromechanical modes in large power systemsF. J. De Marco, J. A. Apolinario, P. C. Pellanda, N. Martins. 1-4 [doi]
• Analog circuits for modeling and controlling synchrony in arrays of coupled oscillatorsAndrius Petrovas, Elena Tamaseviciute, Gytis Mykolaitis, Arünas Tamasevicius, Ruedi Stoop. 1-4 [doi]
• Transistor-level optimization of CMOS complex gatesVinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas. 1-4 [doi]
• Novel redundant logic design for noisy low voltage scenariosLancelot Garcia-Leyva, Antonio Calomarde, Francesc Moll, Antonio Rubio. 1-4 [doi]
• Error coded affine projection algorithmJuan Gerardo Ávalos Ochoa, Juan Carlos Sánchez-García, José Velázquez López. 1-4 [doi]
• Low cost and high throughput FME interpolation for the HEVC emerging video coding standardVladimir Afonso, Henrique Maich, Luciano Agostini, Denis Franco. 1-4 [doi]
• Ultra low power pulse generator based on a ring oscillator with direct path current avoidanceFrancisco Veirano, Pablo Perez-Nicoli, Sebastian Besio, Pablo Castro-Lisboa, Fernando Silveira. 1-4 [doi]
• VLSI architectures for Digital Modulation Classification using Support Vector MachinesEdson Sorato, Renan Netto, Pedro Michel, José Luís Güntzel, Adalbery R. Castro, Aldebaro Klautau. 1-4 [doi]
• Multiple stage capacitor multiplier using dual-output differential amplifiersCarlos Rivera-Escobar, Fransisco Silva-Del-Rosario, Miguel Silva-Martinez, Ivan Padilla-Cantoya. 1-3 [doi]
• Analysis of the effects of coupling through substrate and the calculus of the Q factorEmmanuel Torres-Rios, Svetlana Carsof Sejas Garcia, Luiz Carlos Moreira, Reydezel Torres-Torres, Wilhelmus A. M. Van Noije. 1-4 [doi]
• Optimization of a self-converging algorithm at assembly level to improve SEU fault-toleranceGreicy Marques-Costa, Wassim Mansour, Fabrice Pancher, Raoul Velazco, Alain Bui, Devan Sohier. 1-4 [doi]
• 61 pJ/sample near-threshold notch filter with pole-radius variationLeonardo Bandeira Soares, Kleber Stangherlin, Jorge de Mello, Sergio Bampi. 1-4 [doi]
• Specific processor in FPGA for BLAKE algorithmVictor Ferreira Pereira, Edward David Moreno, Wanderson Roger Azevedo Dias, Dellano Oliveira D. dos Santos. 1-5 [doi]
• Managing signal and power integrity using power transmission lines and alternative signaling schemesSatyanarayana Telikepalli, Sang Kyu Kim, Sung Joo Park, Madhavan Swaminathan, Youkeun Han. 1-4 [doi]
• 8912-bit Montgomery multipliers using radix-8 booth encoding and coded-digitClaudia Patricia Renteria-Mejia, Vladimir Trujillo-Olaya, Jaime Velasco-Medina. 1-4 [doi]
• FinFET basic cells evaluation for regular layoutsCristina Meinhardt, Ricardo Reis 0001. 1-4 [doi]
• Code compression using Multi-Level DictionaryWanderson Roger Azevedo Dias, Edward David Moreno. 1-4 [doi]
• Phase-locked loop simulations using the latency insertion methodJosé E. Schutt-Ainé, Patrick Goh. 1-4 [doi]
• A 2.535 GHz fully integrated Doherty power amplifier in CMOS 65nm with constant PAE in backoffMarcos L. Carneiro, Nathalie Deltimple, Didier Belot, Paulo H. P. de Carvalho, Eric Kerherve. 1-4 [doi]
• Application-specific arithmetic circuit design for a particle tracking applicationTakashi Kambe, Kohsei Takehara, Shuji Tsukiyama. 1-4 [doi]
• QoS 3D-HoC hybrid-on-chip communication structure for dynamic 3D-MPSoCsJohanna Sepúlveda, Guy Gogniat, Ricardo Pires, César Pedraza, Wang Jiang Chau, Marius Strum. 1-4 [doi]
• Analysis of process variations' impact on a 2.4 GHz 90 nm CMOS LNAJ. Gonzalez, J. Cruz, Diego Vázquez, Adoración Rueda. 1-4 [doi]
• Efficient parallel scheduler for circuit simulation exploiting binary link formulationsDouglas Paul, Ramachandra Achar, Michel S. Nakhla, Natalie Nakhla. 1-4 [doi]
• Communication in star coupled network with fractional hyperchaotic nodesO. R. Acosta del Campo, César Cruz-Hernández, Adrian Arellano-Delgado, Rosa Martha López-Gutiérrez. 1-4 [doi]
• Long range dependence in intrachip transaction level trafficJorge González, Gustavo Patino Alvarez, Marius Strum, Wang Jiang Chau. 1-4 [doi]
• Systolic architectures to evaluate polynomials of degree n using the Horner's ruleGianluca Forte, John M. Espinosa-Duran, Jaime Velasco-Medina. 1-4 [doi]
• Fully integrated boost converter for thermoelectric energy harvestingHugo Daniel Hernández, Sergio Takeo Kofuji, Wilhelmus A. M. Van Noije. 1-3 [doi]
• A robust to PVT fully-differential amplifier in 45nm SOI-CMOS technologyAndres Amaya, Francisco Villota, Guillermo Espinosa. 1-4 [doi]
• Voltage reference design using 1 V power supply in 0.13 µm CMOS technologyDalton M. Colombo, Gilson I. Wirth, Sergio Bampi, Purushothaman Srinivasan. 1-4 [doi]
• A resistorless switched bandgap reference topologyHamilton Klimach, Moacir Fernandes Cortinhas Monteiro, Arthur Liraneto Torres Costa, Sergio Bampi. 1-4 [doi]
• Algorithms for energy efficient reconstruction of a process with a multihop Wireless Sensor NetworkFelipe da Rocha Henriques, Lisandro Lovisolo, Marcelo Gonçalves Rubinstein. 1-4 [doi]
• Capacitance measurements of an SOI based CMUTJonathan Hernandez, Tugrul Zure, Sazzadur Chowdhury. 1-4 [doi]
• DC and AC electrical characterization temperature dependence of Ag/Porous Silicon/p-Si/AlEdward Steven Oliveros Ortiz, Faruk Fonthal Rico, Gilberto M. Bolaños P.. 1-4 [doi]
• A low voltage CMOS voltage reference based on partial compensation of MOSFET threshold voltage and mobility using current subtractionLuis Eduardo Toledo, Pablo A. Petrashin, Walter J. Lancioni, Fortunato Carlos Dualibe, Luis Rafael Canali. 1-4 [doi]
• Massively parallel scalable reconfigurable hardware for fuzzy controllersPaulo Renato de Souza Silva Sandres, Nadia Nedjah, Luiza de Macedo Mourelle. 1-4 [doi]
• Enhanced DC gain amplifier using no miller capacitor feedforward compensationHector Ivan Gomez Ortiz. 1-4 [doi]
• Sensor signal linearization techniques: A comparative analysisAntonio J. López-Martín, Alfonso Carlosena. 1-4 [doi]
• A circuit synthesis algorithm for coarse grained dynamic reconfigurable circuitsNobuyuki Araki, Takashi Kambe. 1-4 [doi]
• A real time high definition architecture for the Variable-Length Reference Frame DecoderDieison Silveira, Marcelo Schiavon Porto, Luciano Agostini. 1-4 [doi]
• Fully-differential offset-cancelling circuit with configurable output common-mode voltageEnrique Alvarez 0001, Diego Avila, Hernan Campillo, Angel Abusleme. 1-3 [doi]
• Hardware design of an eigensolver based on the QR methodJorge E. Guerrero-Ramirez, Jaime Velasco-Medina, Julio C. Arce-Clavijo. 1-4 [doi]
• Design of an OTA-Miller for a 96dB SNR SC multi-bit Sigma-Delta modulator based on gm/ID methodologyHeiner Alarcon Cubas, Joao Navarro Soares Jr.. 1-4 [doi]
• A low-power configurable VLSI architecture for sum of absolute differences calculationIsmael Seidel, Bruno George de Moraes, José Luís Güntzel. 1-4 [doi]
• Formalism and reuse in NoC designDayanne K. F. R. Escale, Karla D. N. Ramos, Claudia M. F. A. Ribeiro. 1-4 [doi]
• 233)Fernando Aparicio Urbano-Molano, Vladimir Trujillo-Olaya, Jaime Velasco-Medina. 1-4 [doi]
• 7-bit 2.56 GS/s folding ADC with nanometric compatible architecture by using a high dynamic I/O folding amplifierLuis Antonio Carrillo-Martínez, Guillermo Espinosa Flores-Verdad. 1-4 [doi]
• A voltage-mode boost DC-DC converter with a constant-duty-cycle pulse controlChin-Long Wey, Chung-Hsien Hsu, Tai-Wei Chang. 1-4 [doi]
• FPGA implementation of a sequential Extended Kalman Filter algorithm applied to mobile robotics localization problemSérgio Cruz, Daniel M. Muñoz, Milton E. Conde, Carlos H. Llanos, Geovany A. Borges. 1-4 [doi]
• A wireless medical system prototype for implantable applicationsJesús Efraín Gaxiola Sosa, Kamran Entesari. 1-4 [doi]
• Design of synchronous pipeline digital systems operating in double-edge of the clockDuarte Lopes de Oliveira, Tiago S. Curtinhas, Lester de Abreu Faria, Leonardo Romano. 1-4 [doi]
• Analysis and design of ultra-low-voltage inductive ring oscillators for energy-harvesting applicationsMarcio Bender Machado, Márcio Cherem Schneider, Carlos Galup-Montoro. 1-4 [doi]
• Codebook improvements for a CMOS imager with focal-plane vector quantizationRoberto de Moura Estevão Filho, José Gabriel Rodríguez Carneiro Gomes, Antonio Petraglia. 1-4 [doi]